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41. 发明公开

EP1905043A2 MEMORY ARCHITECTURE WITH ENHANCED OVER-ERASE TOLERANT CONTROL GATE SCHEME 审中-公开
标题翻译：有关火患容错控制栅极方案的扩展内存架构
公开(公告)号：EP1905043A2
公开(公告)日：2008-04-02
申请号：EP06773011.9
申请日：2006-06-13
申请人： Atmel Corporation
发明人： TELECO, Nicola , NGUYEN, Victor
IPC分类号： G11C11/34
CPC分类号： G11C16/3468 , G11C16/26 , G11C16/3477
摘要： The present invention is related to semiconductor memories, and in particular to a nonvolatile or flash memory and method that reduces the effect of any over- erased memory cells in a memory array (301) . When a memory cell (Ml 231, M2 232) is read, a read voltage (306) is applied to the control gate (CGN) of at least one target memory cell, and a negative bias voltage (308) that is lower than a threshold voltage of an over-erased memory cell is also applied to the control gate (CGN-2, CGN+2, ...) of at least one other memory cell that is in the same row as the target memory cell . Applying a negative bias voltage to these other memory cells shuts off nearby cells to isolate current that may come from over-erased memory cells during a read, program, or erase operation.

42. 发明公开

EP1864293A1 ERASING NON-VOLATILE MEMORY USING INDIVIDUAL VERIFICATION AND ADDITIONAL ERASING OF SUBSETS OF MEMORY CELLS 有权转让
标题翻译：不要删除易失性存储器使用单独的验证和记忆细胞亚群的附加擦除
公开(公告)号：EP1864293A1
公开(公告)日：2007-12-12
申请号：EP06739859.4
申请日：2006-03-29
申请人： SanDisk Corporation
发明人： HEMINK, Gerrit, Jan , KAMEI, Teruhiko
IPC分类号： G11C16/34
CPC分类号： G11C16/344 , G11C11/5628 , G11C11/5635 , G11C16/0483 , G11C16/12 , G11C16/16 , G11C16/3404 , G11C16/3409 , G11C16/3445 , G11C16/345 , G11C16/3454 , G11C16/3468 , G11C16/3472 , G11C16/3477 , G11C2211/5621 , G11C2216/18
摘要： A set of non-volatile storage elements is divided into subsets for erasing in order to avoid over-erasing faster erasing storage elements. The entire set of elements is erased until a first subset of the set of elements is verified as erased. The first subset can include the faster erasing cells. Verifying the first subset includes excluding a second subset from verification. After the first subset is verified as erased, they are inhibited from erasing while the second subset is further erased. The set of elements is verified as erased when the second subset is verified as erased. Verifying that the set of elements is erased can include excluding the first subset from verification or verifying both the first and second subsets together. Different step sizes are used, depending on which subset is being erased and verified in order to more efficiently and accurately erase the set of elements.

43. 发明公开

EP1812932A1 HIGH SPEED PROGRAMMING SYSTEM WITH REDUCED OVER PROGRAMMING 有权转让
标题翻译： WITH减少了编程的快速编程系统
公开(公告)号：EP1812932A1
公开(公告)日：2007-08-01
申请号：EP05817284.2
申请日：2005-11-03
申请人： SanDisk Corporation
发明人： HEMINK, Gerrit, Jan
IPC分类号： G11C16/34 , G11C16/10
CPC分类号： G11C11/5628 , G11C16/10 , G11C16/3468 , G11C16/3486 , G11C2216/14
摘要： A program pulse is applied to a set of non-volatile storage elements. The magnitude of the program pulse is chosen to be low enough such that no non-volatile storage elements will be over programmed. The non-volatile storage elements are tested to determine whether at least one non-volatile storage element (or some other minimum number) has been programmed past a test threshold. If so, the set of non-volatile memory elements is considered to have one or more fast programming non-volatile storage elements and future programming is performed using a smaller increment value for subsequent program pulses. If the set of non-volatile memory elements is not determined to have one or more fast programming non-volatile storage elements, then a larger increment value is used for subsequent program pulses until one non-volatile storage element (or some other minimum number) has been programmed past the test threshold, at which point the smaller increment value is used for subsequent program pulses.

44. 发明公开

EP1622164A2 Method of operating a block of flash memory 有权
标题翻译： NichtflüchtigerSpeicher mitBlocklöschung
公开(公告)号：EP1622164A2
公开(公告)日：2006-02-01
申请号：EP05077354.8
申请日：2002-08-23
申请人： MICRON TECHNOLOGY, INC.
发明人： Keays, Brady L.
IPC分类号： G11C16/14
CPC分类号： G11C16/14 , G11C16/16 , G11C16/344 , G11C16/3468 , G11C2216/18
摘要： A method for erase operations of a flash memory block. In one embodiment, a method comprises
applying at least one erase pulse to the block, wherein the block has a plurality of memory cells arranged in rows;
verifying each row to determine if the memory cells associated with each row are erased after each erase pulse; and
completing erase of the block when a predetermined number of rows in the block have been verified as being erased, wherein the predetermined number of rows is less than the total number of rows in the block.
摘要翻译：一种用于闪速存储器块的擦除操作的方法。在一个实施例中，一种方法包括向块施加至少一个擦除脉冲，其中该块具有排成行的多个存储单元; 验证每行以确定每个擦除脉冲之后是否擦除与每行相关联的存储单元; 以及当所述块中的预定行数被验证为被擦除时，完成所述块的擦除，其中所述预定行数小于所述块中的总行数。

45. 发明授权

EP0899744B1 Apparatus and method for programming a memory device such as a virtual ground EPROM array cell 失效
标题翻译：方法和装置用于存储装置的编程诸如具有虚拟接地阵列EPROM细胞
公开(公告)号：EP0899744B1
公开(公告)日：2004-09-15
申请号：EP98301715.3
申请日：1998-03-09
申请人： Macronix International Co., Ltd.
发明人： Lin, Chin-Hsi , Al, Shi-Charng , Lee, Chien-Sing , Ni, Ful-Long , Wang, Mam-Tsung , Huang, Chin-Yi
IPC分类号： G11C16/06
CPC分类号： G11C16/3481 , G11C8/14 , G11C11/5621 , G11C11/5628 , G11C16/0491 , G11C16/08 , G11C16/10 , G11C16/30 , G11C16/34 , G11C16/3468

46. 发明授权

EP0833348B1 Method and circuit for checking multilevel programming of floating-gate nonvolatile memory cells, particlarly flash cells 失效
标题翻译：的方法及装置的浮动栅极存储器单元的多级编程的测试，尤其是闪存单元
公开(公告)号：EP0833348B1
公开(公告)日：2003-07-09
申请号：EP96830612.6
申请日：1996-12-05
申请人： STMicroelectronics S.r.l.
发明人： Kramer Alan , Canegallo Roberto , Chinosi Mauro , Gozzini Giovanni , Rolandi Pier Luigi , Sabatini Marco
IPC分类号： G11C29/00
CPC分类号： G11C16/3486 , G06F2201/81 , G11C11/5621 , G11C11/5628 , G11C16/04 , G11C16/3459 , G11C16/3468 , G11C16/3481 , G11C27/005 , G11C29/50 , G11C2211/5621 , G11C2211/5624
摘要： To check the programming of a nonvolatile memory cell (1) storing an actual threshold value, the drain terminal (2) of the cell is biased at a constant voltage; the gate terminal (4) is biased at a check voltage; the cell is supplied with a predetermined current (IS) to determine a gate-source voltage drop related to the actual threshold value; and the voltage at the source terminal is supplied to an input of an operational amplifier (6). In an open-loop solution, the desired threshold value (VTH) of the set predetermined current is supplied as the check voltage; the amplifier compares the source voltage with the ground; and switching of the amplifier indicates the desired threshold value has been reached. In a closed-loop solution, the output (11) of the operational amplifier is connected directly to the gate terminal (4) of the cell, and supplies the desired threshold value directly.

47. 发明公开

EP0863514A2 Low current programming of floating gate memory 失效
标题翻译：低功耗编程浮栅记忆
公开(公告)号：EP0863514A2
公开(公告)日：1998-09-09
申请号：EP98301649.4
申请日：1998-03-05
申请人： Macronix International Co., Ltd.
发明人： Chen, Han-Sung , Shiau, Tzeng-Huei , Lin, Yu-Shen , Tsai, Chung-Cheng , Lin, Jin-Lien , Wan, Ray-Lin , Liu, Yuan-Chang , Hung, Chun Hsiung
IPC分类号： G11C16/06
CPC分类号： G11C16/3486 , G11C16/10 , G11C16/3459 , G11C16/3468
摘要： A system for programming arrays of floating gate memory cells is provided that reduces programming current requirements, and reduces wordline and bitline stress during programming. A word-to-be-programmed into a floating gate memory array is divided into a plurality of smaller subwords. Only one subword is programmed at a time, thereby reducing programming current requirements. Additionally, subwords which are successfully programmed are not reprogrammed even if bits in other subwords do not program properly. This creates less wordline stress than previous systems which program an entire word at once, thereby requiring subwords which program successfully to be reprogrammed along with subwords which fail to program. Finally, within each subword only those bits which failed to program are reprogrammed, thereby reducing bitline stress during reprogramming for those bits which were successfully programmed.

48. 发明授权

EP0463378B1 An electrically-erasable, electrically-programmable read-only memory cell with a selectable threshold voltage and methods for its use 失效
标题翻译：电可擦除电可编程只读与可选择的阈值电压和它们的使用方法仅存储单元
公开(公告)号：EP0463378B1
公开(公告)日：1997-03-05
申请号：EP91108494.5
申请日：1991-05-24
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Kaya, Cetin
IPC分类号： G11C16/06
CPC分类号： G11C16/3477 , G11C16/10 , G11C16/3468 , G11C16/3472 , G11C16/3481 , G11C16/3486 , G11C27/005 , H01L27/115

49. 发明公开

EP0759622A2 Nonvolatile memory and method of programming the same 失效
标题翻译： NichtflüchtigerSpeicher und Verfahren zu seiner Programmierung
公开(公告)号：EP0759622A2
公开(公告)日：1997-02-26
申请号：EP96113258.6
申请日：1996-08-19
申请人： LG Semicon Co., Ltd.
发明人： Choi, Woong-Lim
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/3486 , G11C11/5621 , G11C11/5628 , G11C16/0416 , G11C16/0441 , G11C16/3468 , G11C16/3481 , G11C2211/5613 , G11C2211/5624
摘要： A nonvolatile memory cell includes a floating gate (31); a programming region (32) having a first current path to the floating gate (31) for programming by providing charge carriers to the floating gate (31) through the first current path or extracting charge carriers stored in the floating gate (31); and a verification region (34 to 37) having a second current path separated from the first current path, for verifying the charge amount of the floating gate (31) through the second current path.
摘要翻译：非易失性存储单元包括浮动栅极（31）; 编程区域（32）具有到浮动栅极（31）的第一电流路径，用于通过经由第一电流路径向浮动栅极（31）提供电荷载流或者提取存储在浮动栅极（31）中的电荷载流子来进行编程; 以及具有与第一电流路径分离的第二电流路径的验证区域（34至37），用于通过第二电流路径验证浮置栅极（31）的电荷量。

50. 发明公开

EP0621603A1 Method and circuit for tunnel-effect programming of floating-gate MOSFETS 失效转让
标题翻译： Verfahren und Schaltung zur Tunneleffektprogrammierung von schwebenden Gatter-MOSFET。
公开(公告)号：EP0621603A1
公开(公告)日：1994-10-26
申请号：EP93830172.8
申请日：1993-04-22
申请人： SGS-THOMSON MICROELECTRONICS S.r.l.
发明人： Ricco, Bruno , Lanzoni, Massimo , Briozzo, Luciano
IPC分类号： G11C16/06
CPC分类号： G11C16/3477 , G11C16/12 , G11C16/14 , G11C16/3468 , G11C16/3486
摘要： The present programming method exploits the close dependence of tunneling current on the voltage drop (V ox ) across the tunnel oxide layer, for which purpose, a bootstrapped capacitor (3) connected to the drain terminal (D) of the transistor (1) is employed, the charge state of which determines the bias of the tunnel oxide and is in turn determined by the charge state in the floating gate (FG). Biasing by the bootstrapped capacitor is such as to permit passage of the tunneling current (I TUN ) and, hence, a change in the threshold voltage of the transistor until the floating gate reaches the desired charge level, and to prevent passage of the tunneling current upon the transistor reaching the desired threshold. Programming is thus performed automatically and to a predetermined degree of accuracy, with no need for a special circuit for arresting the programming operation when the desired threshold is reached.
摘要翻译：本编程方法利用隧道电流对隧道氧化物层的电压降（Vox）的密切依赖性，为此，采用连接到晶体管（1）的漏极端子（D）的自举电容器（3），其充电状态决定了隧道氧化物的偏压，又由浮栅（FG）中的电荷状态确定。通过自举电容器的偏置使得能够通过隧穿电流（ITUN），从而允许晶体管的阈值电压的变化，直到浮栅达到期望的电荷水平，并且防止隧道电流通过晶体管达到所需的阈值。因此，自动执行编程并达到预定的准确度，当达到期望的阈值时，不需要用于阻止编程操作的特殊电路。

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