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1. 发明授权

EP2369593B1 Channel hot electron injection programming method and related device 有权转让
标题翻译：使用热通道电注入编程和相关联的装置的方法
公开(公告)号：EP2369593B1
公开(公告)日：2014-10-15
申请号：EP11150599.6
申请日：2011-01-11
申请人： eMemory Technology Inc.
发明人： Chen, Ying-Je , Ting, Yun-Jen , Sun, Wein-Town , Hsiao, Kai-Yuan , Liu, Cheng-Jye
IPC分类号： G11C16/34
CPC分类号： G11C16/10 , G11C16/3468

2. 发明公开

EP2760026A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译： NICHTFLÜCHTIGEHALBLEITERSPEICHERVORRICHTUNG
公开(公告)号：EP2760026A1
公开(公告)日：2014-07-30
申请号：EP12833384.6
申请日：2012-09-18
申请人： Floadia Corporation
发明人： SHINAGAWA, Yutaka , KASAI, Hideo , TANIGUCHI, Yasuhiro
IPC分类号： G11C16/04 , G11C16/02
CPC分类号： H01L27/11517 , G11C16/0416 , G11C16/0483 , G11C16/24 , G11C16/3468
摘要： A non-volatile semiconductor memory device is proposed whereby voltage can be more flexibly set in accumulating electric charges into a selected memory cell transistor in comparison with a conventional device. In a non-volatile semiconductor memory device (1), when a selected memory cell transistor (115) is caused to accumulate electric charges, high voltage as writing prevention voltage is applied from a PMOS transistor (9b) while low voltage as writing voltage is applied from an NMOS transistor (15a). Thus, a role of applying voltage to either the selected memory cell transistor (115) or a non-selected memory cell transistor (116) is shared by the PMOS transistor (9b) and the NMOS transistor (15a). Therefore, the gate voltage and the source voltage of the PMOS transistor (9b) and those of the NMOS transistor (15a) can be separately adjusted, and gate-to-substrate voltage thereof can be finally set to be, for instance, 4[V] or etc.
摘要翻译：提出了一种非易失性半导体存储器件，与常规器件相比，可以更灵活地将电压累积到选定的存储单元晶体管中。在非易失性半导体存储器件（1）中，当选择的存储单元晶体管（115）累积电荷时，作为写入电压的高电压从PMOS晶体管（9b）施加，而作为写入电压的低电压是从NMOS晶体管（15a）施加。因此，向所选存储单元晶体管（115）或非选择存储单元晶体管（116）施加电压的作用由PMOS晶体管（9b）和NMOS晶体管（15a）共享。因此，可以分别调整PMOS晶体管（9b）的栅极电压和源极电压，并且可以分别调整NMOS晶体管（9b）的栅极电压和源极电压，并且可以最终将其栅极至衬底电压设置为例如4μm， V]等

3. 发明授权

EP1866928B1 FASTER PROGRAMMING OF HIGHER LEVEL STATES IN MULTI-LEVEL CELL FLASH MEMORY 有权
标题翻译：父层级的多级快闪存储单元编程速度更快
公开(公告)号：EP1866928B1
公开(公告)日：2013-07-17
申请号：EP06740306.3
申请日：2006-03-31
申请人： SanDisk Technologies Inc.
发明人： HEMINK, Gerritt
IPC分类号： G11C11/56 , G11C16/10
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/10 , G11C16/12 , G11C16/3468 , G11C16/3481 , G11C16/3486 , G11C2211/5621 , G11C2216/14

4. 发明授权

EP2306463B1 Word line compensation in non-volatile memory erase operations 有权转让
标题翻译：字线补偿缺失的非易失性存储器
公开(公告)号：EP2306463B1
公开(公告)日：2013-01-23
申请号：EP10012052.6
申请日：2005-12-15
申请人： SanDisk Technologies Inc.
发明人： Wan, Jun , Pang, Chan-sui , Lutze, Jeffrey W.
IPC分类号： G11C16/16 , G11C16/04 , G11C16/34 , G11C8/08
CPC分类号： G11C8/08 , G11C16/0483 , G11C16/16 , G11C16/3468

5. 发明授权

EP1812932B1 HIGH SPEED PROGRAMMING SYSTEM WITH REDUCED OVER PROGRAMMING 有权转让
标题翻译： WITH减少了编程的快速编程系统
公开(公告)号：EP1812932B1
公开(公告)日：2010-12-22
申请号：EP05817284.2
申请日：2005-11-03
申请人： SanDisk Corporation
发明人： HEMINK, Gerrit, Jan
IPC分类号： G11C16/34 , G11C16/10
CPC分类号： G11C11/5628 , G11C16/10 , G11C16/3468 , G11C16/3486 , G11C2216/14
摘要： A program pulse is applied to a set of non-volatile storage elements. The magnitude of the program pulse is chosen to be low enough such that no non-volatile storage elements will be over programmed. The non-volatile storage elements are tested to determine whether at least one non-volatile storage element (or some other minimum number) has been programmed past a test threshold. If so, the set of non-volatile memory elements is considered to have one or more fast programming non-volatile storage elements and future programming is performed using a smaller increment value for subsequent program pulses. If the set of non-volatile memory elements is not determined to have one or more fast programming non-volatile storage elements, then a larger increment value is used for subsequent program pulses until one non-volatile storage element (or some other minimum number) has been programmed past the test threshold, at which point the smaller increment value is used for subsequent program pulses.

6. 发明授权

EP1864292B1 ERASING NON-VOLATILE MEMORY UTILIZING CHANGING WORD LINE CONDITIONS TO COMPENSATE FOR SLOWER FRASING MEMORY CELLS 有权转让
标题翻译：清除非易失性存储器使用变量WORD线路条件，以抵消SLOW写作MEMORY CELL
公开(公告)号：EP1864292B1
公开(公告)日：2010-02-10
申请号：EP06784329.2
申请日：2006-03-29
申请人： SanDisk Corporation
发明人： HIGASHITANI, Masaaki
IPC分类号： G11C16/04 , G11C16/16
CPC分类号： G11C16/3445 , G11C8/08 , G11C11/5628 , G11C11/5635 , G11C16/0483 , G11C16/08 , G11C16/12 , G11C16/16 , G11C16/3404 , G11C16/3409 , G11C16/345 , G11C16/3454 , G11C16/3468 , G11C16/3472 , G11C16/3477 , G11C2211/5621 , G11C2216/18
摘要： Voltage conditions applied to the memory cells of a non-volatile memory system are changed during erase operations in order to equalize the erase behavior of the select memory cells with other memory cells of the system that are being concurrently erased. The changed conditions can compensate for capacitively coupled voltages within a NAND string. After biasing a NAND string for an erase operation and beginning application of the erase voltage pulse, the word lines of one or more interior memory cells can be floated. By floating the selected interior word lines, the peak erase potential created across the tunnel dielectric region of the cells coupled thereto is decreased from its normal level. Consequently, the erase rates of these cells are slowed to substantially match that of the slower erasing end memory cells of the string. Different word lines can be floated at different times to alter the erase behavior of different memory cells b different amounts.

7. 发明授权

EP1869681B1 USE OF DATA LATCHES IN MULTI-PHASE PROGRAMMING OF NON-VOLATILE MEMORIES 失效转让
标题翻译：中的数据LOCK多相编程非易失性内存使用
公开(公告)号：EP1869681B1
公开(公告)日：2009-08-19
申请号：EP06739682.0
申请日：2006-03-27
申请人： SanDisk Corporation
发明人： LI, Yan , CERNEA, Raul-Adrian
IPC分类号： G11C16/34
CPC分类号： G11C16/3468
摘要： A non-volatile memory device includes circuitry for governing a multi-phase programming process in a non-volatile memory. The exemplary embodiment uses a quick pass write technique where a single programming pass is used, but the biasing of the selected memory cells is altered to slow programming as the memory cells approach their target values by raising the voltage level of the channels of the selected memory cells. A principle aspect of the present invention introduces a latch associated with the read/write circuitry connectable to each selected memory cell along a corresponding bit line for the storage of the result of the verify at this lower level.

8. 发明授权

EP1751773B1 ERASE VERIFICATION FOR NON-VOLATILE MEMORY BY TESTING THE CONDUCTION OF THE MEMORY ELEMENTS IN A FIRST AND A SECOND DIRECTION 有权
标题翻译：删除非挥发性存储器验证通过检查一个第一存储元件和变速器的第二方向
公开(公告)号：EP1751773B1
公开(公告)日：2009-01-14
申请号：EP05752106.4
申请日：2005-05-20
申请人： SanDisk Corporation
发明人： TRAN, Dat , PONNURU, Kiran , CHEN, Jian , LUTZE, Jeffrey, W. , WANG, Jun
IPC分类号： G11C16/34
CPC分类号： G11C16/3468
摘要： Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to better detect defective and/or insufficiently erased storage elements of the group. For example, the results of erasing a NAND string can be verified by testing charging of the string in a plurality of directions with the storage elements biased to turn on if in an erased state. If a string of storage elements passes a first test process or operation but fails a second test process or operation, the string can be determined to have failed the erase process and possibly be defective. By testing charging or conduction of the string in a first (380) and a second (382) direction, defects in any transistors of the Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements in verified using a plurality of test conditions to better detect defective and/or insufficiently erased storage elements of the group. For example, the results of erasing a NAND string can be verified by testing charging of the string in a plurality of directions with the storage elements biased to turn on if in an erased state. If a string of storage elements passes a first test process or operation but fails a second test process or operation, the string can be determined to have failed the erase process and possibly be defective. By testing charging or conduction of the string in a plurality of directions, defects in any transistors of the string that are masked under one set of conditions may be exposed under a second set of bias conditions. For example, a string may pass an erase verification operation but then be read as including one or more programmed storage elements. Such a string can be defective and mapped out of the memory device.

9. 发明公开

EP1866928A2 FASTER PROGRAMMING OF HIGHER LEVEL STATES IN MULTI-LEVEL CELL FLASH MEMORY 有权
标题翻译：父层级的多级快闪存储单元编程速度更快
公开(公告)号：EP1866928A2
公开(公告)日：2007-12-19
申请号：EP06740306.3
申请日：2006-03-31
申请人： SanDisk Corporation
发明人： HEMINK, Gerritt
IPC分类号： G11C11/56 , G11C16/10
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/10 , G11C16/12 , G11C16/3468 , G11C16/3481 , G11C16/3486 , G11C2211/5621 , G11C2216/14
摘要： A program voltage signal implemented as a series of increasing program voltage pulses is applied to a set of non- volatile storage elements. Different increment values can be used when programming memory cells to different memory states. A smaller increment value can be used when programming memory cells to lower threshold voltage memory states and a larger increment value used when programming memory cells to higher threshold voltage memory states such as the highest memory state in an implementation. When non-volatile storage elements of a set are programmed to different memory states under simultaneous application of a single program voltage signal, programming can be monitored to determine when lower state programming is complete. The increment value can then be increased to complete programming to the highest memory state. Coarse/fine programming methodology can be incorporated for the highest memory state when the increment value is increased to maintain the threshold distribution within a reasonable range.

10. 发明公开

EP1864294A1 SOFT PROGRAMMING NON-VOLATILE MEMORY UTILIZING INDIVIDUAL VERIFICATION AND ADDITIONAL SOFT PROGRAMMING OF SUBSETS OF MEMORY CELLS 审中-公开
标题翻译：软编程不挥发存储器使用个别认证和附加软编程存储器单元组
公开(公告)号：EP1864294A1
公开(公告)日：2007-12-12
申请号：EP06739867.7
申请日：2006-03-29
申请人： SanDisk Corporation
发明人： HEMINK, Gerrit, Jan , KAMEI, Teruhiko
IPC分类号： G11C16/34
CPC分类号： G11C16/3409 , G11C11/5628 , G11C11/5635 , G11C16/0483 , G11C16/12 , G11C16/16 , G11C16/3404 , G11C16/345 , G11C16/3454 , G11C16/3468 , G11C16/3472 , G11C16/3477 , G11C2211/5621 , G11C2216/18
摘要： A set of non-volatile storage elements is divided into subsets for soft programming in order to more fully soft-program slower soft programming elements. The entire set of elements is soft-programmed until verified as soft programmed (or until a first subset of elements is verified as soft programmed while excluding a second subset from verification). After the set is verified as soft programmed, a first subset of elements is inhibited from further soft programming while additional soft programming is carried out on a second subset of elements. The second subset can include slower soft programming elements. The second subset can then undergo soft programming verification while excluding the first subset from verification. Soft programming and verifying for the second subset can continue until it is verified as soft programmed. Different step sizes can be used for increasing the size of the soft programming signal, depending on which subset is being soft programmed and verified.

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