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41. 发明公开

EP1926241A2 Using unpredictable information to minimize leakage from smartcards and other cryptosystems 审中-公开
标题翻译：信息zur Leckminimierung von Chipkarten und anderen Kryptosystemen
公开(公告)号：EP1926241A2
公开(公告)日：2008-05-28
申请号：EP08000796.6
申请日：1999-06-03
申请人： Cryptography Research Inc.
发明人： Kocher, Paul C. , Jaffe, Joshua M. , Jun, Benjamin C.
IPC分类号： H04K1/00
CPC分类号： G07F7/082 , G06F21/755 , G06F2207/7219 , G06K19/073 , G06K19/07363 , G06Q20/341 , G07F7/1008 , H04L9/003 , H04L9/004 , H04L2209/08 , H04L2209/127
摘要： Methods and apparatuses for securing cryptosystems against external monitoring attacks reduce the amount (and signal to noise ratio) of useful information leaked during processing. This is generally accomplished by incorporating unpredictable information (100, 200) into the cryptographic processing. An embodiment of the invention use clock skipping in which a clock decorrelator (240) coupled to a source of unpredictable information generates a second clock signal (260) from a first clock signal (220) using the unpredictable information, such that the second clock signal cannot be reliably predicted from the first clock signal; The techniques may be implemented in hardware or software, may use a combination of digital and analog techniques, and may be deployed in a variety of cryptographic devices.
摘要翻译：用于保护密码系统免受外部监控攻击的方法和设备减少了处理过程中泄漏的有用信息的数量（和信噪比）。这通常通过将不可预测的信息（100,200）并入加密处理来实现。本发明的实施例使用时钟跳跃，其中耦合到不可预测信息的源的时钟解相关器（240）使用不可预测的信息从第一时钟信号（220）生成第二时钟信号（260），使得第二时钟信号不能从第一时钟信号可靠地预测; 这些技术可以在硬件或软件中实现，可以使用数字和模拟技术的组合，并且可以部署在各种加密设备中。

42. 发明公开

EP1920374A1 CIRCUIT ARRANGEMENT WITH NON-VOLATILE MEMORY MODULE AND METHOD FOR REGISTERING ATTACKS ON SAID NON-VOLATILE MEMORY MODULE 审中-公开
标题翻译：与用于登记与非易失性存储器模块的攻击非易失性存储器模块和方法的电路安排
公开(公告)号：EP1920374A1
公开(公告)日：2008-05-14
申请号：EP06780334.6
申请日：2006-08-09
申请人： NXP B.V.
发明人： BUHR, Wolfgang
IPC分类号： G06F21/00
CPC分类号： G06F21/79 , G06F21/75 , G06F21/755
摘要： In order to further develop a circuit arrangement (100), in particular an integrated circuit, for electronic data processing as well as a method for detecting and/or for registering and/or for signaling the irradiation of at least one non- volatile memory module (10) with at least one light source in order to be capable of securely averting an attack, in particular an E[lectro]M[agnetic] radiation attack, for example a side-channel attack, or in particular a crypto-analysis, for example a current trace analysis or a D[ifferential]P[ower]A[nalysis], such attack or such analysis in particular being targeted on finding out a private key, it is proposed that an access timing for at least one read access to the memory module (10) is generated, in particular that at least one additional read access to the memory module (10) is added in at least one test mode (T), in particular in at least one D[isable]A[ll]W[ordline] mode, this test mode (T) preferably allowing to detect if the memory module (10) is currently exposed to any light of a certain energy.

43. 发明公开

EP1904946A1 DETECTION D'UNE FAUTE PAR PERTURBATION LONGUE 有权
标题翻译：错开始的很长发现故障
公开(公告)号：EP1904946A1
公开(公告)日：2008-04-02
申请号：EP06777304.4
申请日：2006-06-12
申请人： GEMPLUS
发明人： BENOIT, Olivier
IPC分类号： G06F21/06
CPC分类号： G06F21/755
摘要： The invention concerns the field of fault detection in an electronic component. The invention concerns a method for detecting faults by perturbations during execution of a computerized code in an electronic device, said computer code comprising a so-called sensitive process, the method including a step of executing a redundant procedure of said sensitive process and a step of inserting a delay between the sensitive process and the redundant procedure. The invention is characterized in that it further comprises a step of executing a trapping means during the delay, said means being sensitive to perturbations and supplying, in the absence of perturbation, a predictable result.

44. 发明授权

EP1247186B1 SPEICHERZUGRIFFSVERFAHREN UND SCHALTUNGSANORDUNG 有权
标题翻译：存储器访问方法及电路装置
公开(公告)号：EP1247186B1
公开(公告)日：2007-10-17
申请号：EP00992081.0
申请日：2000-12-22
申请人： Infineon Technologies AG
发明人： GAMMEL, Berndt , SMOLA, Michael
IPC分类号： G06F12/08
CPC分类号： G06F21/79 , G06F12/0888 , G06F21/75 , G06F21/755 , G06F2207/7219
摘要： The invention relates to a microprocessor (1). A cache memory (21) serves for accelerating access to an external memory (3). Cache miss is signalled to the microprocessor (1) instead of the actually present cache hit event. Reversal is controlled randomly. The current profile of cache hit and cache miss events is thus masked in such a way that security is increased in relation to statistic hacking methods by means of which the current profile is evaluated.

45. 发明公开

EP1760595A1 SEMICONDUCTOR DEVICE HAVING POWER CONSUMPTION ANALYSIS PREVENTING FUNCTION 审中-公开
标题翻译：麻省理工学院麻省理工学院
公开(公告)号：EP1760595A1
公开(公告)日：2007-03-07
申请号：EP05737181.7
申请日：2005-05-09
申请人： SHARP KABUSHIKI KAISHA
发明人： OHYAMA, Shigeo
IPC分类号： G06F12/14 , G06K19/073
CPC分类号： G06K19/07363 , G06F21/755 , G06K19/073
摘要： There is a provided a semiconductor device having a high security whose power consumption is difficult to analyze even without setting up random characteristic to the processing time. The semiconductor device includes a target circuit (14), a sub-target circuit (15) having the same circuit configuration as the target circuit (14), and a dummy bit string generation circuit (11) for generating a bit string of a dummy serial input signal to be inputted to the sub-target circuit (15) according to the bit string of the serial input signal of the target circuit (14). The dummy bit string generation circuit (11) includes a hamming distance detection circuit (12) for detecting a hamming distance between two continuous bits of the serial input signal as a first hamming distance, and a conflicting signal generation circuit (13) for generating after the last bit, upon detection of the first hamming distance, an input bit having a hamming distance from the last bit of the bit string of the dummy serial input signal which distance is a second hamming distance conflicting with the first hamming distance.
摘要翻译：提供了具有高安全性的半导体器件，即使没有在处理时间内设置随机特性，其功耗难以分析。半导体器件包括目标电路（14），具有与目标电路（14）相同的电路结构的子目标电路（15），以及用于产生虚拟的位串的虚拟位串生成电路（11）串行输入信号根据目标电路（14）的串行输入信号的位串输入到子目标电路（15）。伪位串生成电路（11）包括：汉明距离检测电路（12），用于检测作为第一汉明距离的串行输入信号的两个连续位之间的汉明距离;以及冲突信号生成电路（13），用于在后在检测到第一汉明距离时，最后一位具有与虚拟串行输入信号的比特串的最后一位相距汉明距离的输入比特，该距离是与第一汉明距离相冲突的第二汉明距离。

46. 发明公开

EP1750217A1 Absicherung von Speichereinhalten eines Datenträgers 有权
标题翻译： Absicherung von Speichereinhalten einesDatenträgers
公开(公告)号：EP1750217A1
公开(公告)日：2007-02-07
申请号：EP06014293.2
申请日：2006-07-10
申请人： Giesecke & Devrient GmbH
发明人： Schmalz, Frank , Kuhn, Torge , Hildinger, Peter , Ness, Werner , Treger, Jörn , Prinzinger, Robert
IPC分类号： G06F21/00 , G07F7/10 , G11C16/22 , G06F12/14
CPC分类号： G06K19/073 , G06F21/755 , G06Q20/341 , G07F7/082 , G07F7/1008 , G11C16/22 , H04L9/004
摘要： Der Speicherinhalt eines veränderlichen Speichers (4, 5) eines mit einem Prozessor (2) ausgestatteten, portablen Datenträgers (1) wird vor Angriffen mittels physikalischen Einflüssen von außen geschützt, indem die damit verbundenen Bitfehler durch Vergleichen von zu prüfenden Speicherinhalten (14, 15, 16) mit vorgegebenen Speicherinhalten (11,12,13) erkannt werden. Diese Speichertests werden in zufällig bestimmten Zeitspannen durchgeführt, so dass der Zeitpunkt eines Speichertests nicht vorhersagbar ist.
摘要翻译：安全方法涉及要测试的存储器内容的比较（S5）和比较的连续重复，并且对于每个比较，一致地确定相应的时间段，并且执行比较步骤的时间间隔（S2）。安全方法还涉及作为可变存储器的存储器。便携式数据载体也包含独立声明。

47. 发明公开

EP1739519A1 Method to secure the execution of a program against attacks by radiation or other 审中-公开
标题翻译：方法，以确保一个程序的对抗辐射等攻击的执行
公开(公告)号：EP1739519A1
公开(公告)日：2007-01-03
申请号：EP05291422.3
申请日：2005-06-30
申请人： Axalto SA
发明人： Gombocz, Pascal c/o Axalto SA, IP Dpt , Poncelet, Olivier c/o Axalto SA, IP Dpt , Ortega, Frédéric c/o Axalto SA, IP Dpt , Pepin, Cyrille c/o Axalto SA, IP Dpt , Giraud, Nicolas c/o Axalto SA, IP Dpt
IPC分类号： G06F1/00
CPC分类号： G06F21/54 , G06F21/755
摘要： The method according to this invention concerns a method to secure the execution of a program in an electronic assembly including data processing means and data storage means. The method consists in producing a supplementary result depending on at least one of the input parameter(s) of a called function in said program in order to check the integrity of said parameter(s) when used by said function.
This invention also concerns the electronic module in which said method is implemented and the card comprising said module.
摘要翻译：雅丁本发明的方法涉及到确保程序的执行中包括装置和数据存储装置的电子数据的处理的组件的方法。在生产的补充结果，以便检查所述参数（一个或多个）的完整性取决于所述程序中的被调用函数的输入参数（一个或多个）中的至少一个在由所述功能使用的方法besteht。所以本发明涉及，其中，所述方法被实施在电子模块和所述卡包括所述模块。

48. 发明公开

EP1728152A2 PIPELINE CIRCUIT 有权
标题翻译：流水线电路
公开(公告)号：EP1728152A2
公开(公告)日：2006-12-06
申请号：EP05708837.9
申请日：2005-02-24
申请人： Koninklijke Philips Electronics N.V.
发明人： BINK, Adrianus, J. , DE CLERCQ, Mark, N., O.
IPC分类号： G06F9/38
CPC分类号： G06F9/3871 , G06F1/3203 , G06F21/755
摘要： There is provided an electronic circuit that is harder to crack using power analysis techniques, the electronic circuit comprising first and second pipeline stages and a latch positioned between the pipeline stages; wherein the electronic circuit is adapted to operate in a normal mode in which the latch is opened and closed in response to an enable signal, and a reduced mode in which the latch is held open to reduce a current peak associated with the opening and closing of the latch.

49. 发明授权

EP1046142B1 DATENVERARBEITUNGSEINRICHTUNG UND VERFAHREN ZU DESSEN BETRIEB ZUM VERHINDERN EINER DIFFERENTIELLEN STROMVERBRAUCHANALYSE 有权
标题翻译：数据处理设备和操作，以防止差分功率消耗分析方法
公开(公告)号：EP1046142B1
公开(公告)日：2005-11-16
申请号：EP99947401.8
申请日：1999-09-21
申请人： Koninklijke Philips Electronics N.V. , Philips Intellectual Property & Standards GmbH
发明人： FEUSER, Markus
IPC分类号： G07F7/10 , G06F1/00 , G06K19/073
CPC分类号： H04L9/003 , G06F21/72 , G06F21/75 , G06F21/755 , G06F21/77 , G06F2207/7219 , G06K19/07 , G06K19/073 , G06K19/07363 , H04L2209/08 , H04L2209/125
摘要： The invention relates to a data processing device (100) and to a method for operating the data processing device, notably a chip card. Said device comprises an integrated circuit which in accordance with a clock pulse carries out calculating operations, especially cryptographic operations, data inputs and outputs and data transfers from and to registers of the integrated circuit. To this end the integrated circuit (10) is controlled such that the calculating operations, on the one hand, and the input/output of data and data transfer from register to register or between registers, on the other hand, are carried out time-parallel.

50. 发明公开

EP1573541A2 PROCEDE DE MEMORISATION DE DONNEES AVEC CORRECTION D'ERREUR 审中-公开
标题翻译： FOR DATA过程以纠错STORE
公开(公告)号：EP1573541A2
公开(公告)日：2005-09-14
申请号：EP02793205.2
申请日：2002-10-31
申请人： iRoC Technologies
发明人： NICOLAIDIS, Micha[l
IPC分类号： G06F11/10
CPC分类号： G06F11/1008 , G06F21/755
摘要： The invention concerns a data storage method enabling error detection and correction in an organized storage for reading and writing words of a first number (m) of bits and optionally for modifying only part of such a word, comprising the following steps which consist in: associating an error detection and correction code with a group of a second number (k≥1) of words; and at each partial writing in the group of words, calculating a new code of the modified group of words; performing a verification operation and, if an error occurs, carrying out an error correction of the modified word and/or of the new code.

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