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    • 44. 发明公开
    • Semiconductor memory device
    • 半导体存储器件
    • EP1612806A3
    • 2006-05-10
    • EP05254075.4
    • 2005-06-29
    • SHARP KABUSHIKI KAISHA
    • Yamamoto, KaoruIto, NobuhikoYamauchi, Yoshimitsu
    • G11C16/26G11C16/24G11C16/04
    • G11C16/26G11C16/0491G11C16/24
    • A semiconductor memory device having a virtual ground line type memory array structure includes a readout circuit for selecting a pair of selected bit lines connected to the source and the drain of a memory cell to be read, applying a predetermined voltage to between the paired selected bit lines, and sensing a memory cell current flowing through the memory cell to be read, and a counter potential generation circuit for generating from an intermediate node potential, which is higher than any level of the potential on the selected bit lines and supplied from an intermediate node on a current path for feeding the memory cell current in the readout circuit, a counter potential which varies in the same direction as of the intermediate node potential depending on the memory cell current so that its variation is greater than that of the intermediate node potential, wherein the counter potential is applied to an unselected bit line allocated next to one at a high level of the paired selected bit lines.
    • 一种具有虚拟接地线型存储器阵列结构的半导体存储器件包括:读出电路,用于选择连接到待读取的存储器单元的源极和漏极的一对选择位线,将预定电压施加到成对选择位之间 并且感测流过待读取的存储器单元的存储器单元电流,以及反向电压产生电路,用于从中间节点电势产生电势,所述中间节点电势高于所选位线上的电势的任何电平,并且从中间电路 在用于馈送读出电路中的存储器单元电流的电流路径上的节点,取决于存储器单元电流而在与中间节点电势相同的方向上变化的相对电势,使得其变化大于中间节点电势 其中所述计数器电位被施加到所选择的配对的高电平之一旁边分配的未选位线 位线。
    • 45. 发明公开
    • Semiconductor memory device
    • Halbleiterspeicherbaustein
    • EP1612806A2
    • 2006-01-04
    • EP05254075.4
    • 2005-06-29
    • SHARP KABUSHIKI KAISHA
    • Yamamoto, KaoruIto, NobuhikoYamauchi, Yoshimitsu
    • G11C16/26G11C16/24G11C16/04
    • G11C16/26G11C16/0491G11C16/24
    • A semiconductor memory device having a virtual ground line type memory array structure includes a readout circuit for selecting a pair of selected bit lines connected to the source and the drain of a memory cell to be read, applying a predetermined voltage to between the paired selected bit lines, and sensing a memory cell current flowing through the memory cell to be read, and a counter potential generation circuit for generating from an intermediate node potential, which is higher than any level of the potential on the selected bit lines and supplied from an intermediate node on a current path for feeding the memory cell current in the readout circuit, a counter potential which varies in the same direction as of the intermediate node potential depending on the memory cell current so that its variation is greater than that of the intermediate node potential, wherein the counter potential is applied to an unselected bit line allocated next to one at a high level of the paired selected bit lines.
    • 具有虚拟接地线型存储器阵列结构的半导体存储器件包括读出电路,用于选择连接到要读取的存储器单元的源极和漏极的一对选定位线,将预定电压施加在成对选定位之间 并且感测流过待读取的存储器单元的存储单元电流,以及用于从中间节点电位产生的逆电位产生电路,该中间节点电位高于所选位线上的电位的任何电平并且从中间级 在电流路径上用于馈送读出电路中的存储单元电流的一个节点,取决于存储单元电流而在与中间节点电位相同的方向上变化的反电位,使得其变化大于中间节点电位的变化 ,其中所述计数器电位被施加到在所选择的所述配对的高电平处分配的旁边的未选择的位线 位线。