专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

EP1152427B1 Semiconductor memory device 有权
公开(公告)号：EP1152427B1
公开(公告)日：2004-03-10
申请号：EP01303711.4
申请日：2001-04-24
申请人： Sharp Kabushiki Kaisha
发明人： Takata, Masahiro , Takata, Hidekazu
IPC分类号： G11C7/14 , G11C16/28 , G11C7/12
CPC分类号： G11C7/14 , G11C16/28

32. 发明授权

EP0869506B1 Memory device with reduced power dissipation 失效
标题翻译：以降低的功率损耗存储器装置
公开(公告)号：EP0869506B1
公开(公告)日：2003-07-02
申请号：EP97830160.4
申请日：1997-04-03
申请人： STMicroelectronics S.r.l.
发明人： Baroni, Andrea , Rimondi, Danilo , Taliercio, Michele , Torelli, Cosimo
IPC分类号： G11C7/00 , G11C11/409
CPC分类号： G11C7/14 , G11C11/419

33. 发明公开

EP1297535A1 REFERENCE CELL FOR HIGH SPEED SENSING IN NON-VOLATILE MEMORIES 有权
标题翻译：参考单元用于读取非易失性存储器高速
公开(公告)号：EP1297535A1
公开(公告)日：2003-04-02
申请号：EP01935781.3
申请日：2001-05-14
申请人： ATMEL CORPORATION
发明人： PATHAK, Saroj , PAYNE, James, E. , PATHAK, Jagdish
IPC分类号： G11C16/28 , G11C7/06 , G11C7/14
CPC分类号： G11C16/28 , G11C7/067 , G11C7/14
摘要： A reference cell (47) for use in a high speed sensing circuit includes a first sub-circuit (73) and a second sub-circuit (71). The first sub-circuit (73) has a structure similar to memory cells within odd number rows of a main memory array. The second sub-circuit (71) has a structure similar to memory cells within even numbered rows of the main memory array. If a target cell within the main memory array lies within an odd numbered row, then the first sub-circuit is selected, and if the target cell lies within an even numbered row, then second sub-circuit is selected. Both of the first and second sub-circuits include a reference transistor (85, 75) having its control gate (99, 91) broken into two parts. A first part is a poly 1 layer and is separated from the channel region by a tunneling oxide. A second part is a metal or poly 2 layer over the first part and separated from the first part by a gate oxide. A via (101, 95) is used to connect the first part to the second part.

34. 发明公开

EP1047079A2 Semiconductor memory device generating accurate internal reference voltage 有权
标题翻译：与精确的内部基准电压产生的半导体存储器件
公开(公告)号：EP1047079A2
公开(公告)日：2000-10-25
申请号：EP00104670.5
申请日：2000-03-03
申请人： Oki Electric Industry Co., Ltd.
发明人： Miyamoto, Kenichi, c/o OKI Micro Design Co., Ltd.
IPC分类号： G11C17/12 , G11C7/14
CPC分类号： G11C17/126 , G11C7/14 , G11C17/123
摘要： A semiconductor memory device has a memory cell array that outputs cell current to data sensing amplifiers and reference current to reference amplifiers. The reference amplifiers convert the reference current to a reference voltage. The data sensing amplifiers use the reference voltage to convert the cell current to a data voltage signal. According to a first aspect of the invention, reference current is supplied to a reference amplifier from two parallel data paths, each having approximately equal numbers of transistors of two types, one type of which is always switched on, the other type switching on and off. According to a second aspect of the invention, each data sensing amplifier, and the reference amplifier to which it is connected, receive currents from parts of the memory cell array having identical layouts.

35. 发明公开

EP1031990A3 Reference voltage generator for an integrated circuit such as a dynamic random access memory (DRAM) 有权
标题翻译：用于集成电路的基准电压发生器，诸如动态随机存取存储器电路（DRAM）
公开(公告)号：EP1031990A3
公开(公告)日：2000-09-20
申请号：EP00301259.8
申请日：2000-02-17
申请人： STMicroelectronics, Inc.
发明人： Guritz, Elmer Henry
IPC分类号： G11C11/409 , G11C7/14 , G11C5/14 , G05F1/46 , G11C11/407
CPC分类号： G11C11/4074 , G05F1/465 , G11C7/14 , G11C11/4099
摘要： A reference voltage generator includes a voltage divider connected to a voltage supply and a feedback buffer amplifier. The divider supplies at least one voltage output signal to the feedback buffer amplifier under control of a feedback control signal supplied by the feedback buffer amplifier. The reference voltage generator may include a delay element coupled between the voltage divider and the feedback buffer amplifier in-line with the feedback control signal and a low impedance output buffer that receives the voltage output signal from the voltage divider and supplies the reference voltage at an output node. The reference voltage may be supplied to the reference plates of bit storage capacitors within the memory cells. The storage capacitors can be protected by including a clamping circuit that maintains the output node at a voltage between the voltages of the two voltage supply terminals.
摘要翻译：参考电压产生器包括连接到电压源和反馈缓冲放大器的分压器。除法器供应至少一个电压输出信号到下由反馈缓冲放大器提供一个反馈控制信号的控制的反馈缓冲放大器。参考电压发生器可以包括：耦合在分压器和在线与所述反馈控制信号和一低阻抗输出缓冲器中的反馈缓冲放大器之间的延迟元件那样接收来自电压分压器的电压输出信号，并且在提供参考电压在输出节点。参考电压可以被提供给位存储电容器的存储单元内的基准板。存储电容器可以通过包括一个钳位电路没有被保护保持在两个电压供电端子的电压之间的电压的输出节点。

36. 发明公开

EP0838824A1 Mémoire à temps de lecture amélioré 失效
标题翻译： Speeseher mit verbesserter Lesezeit
公开(公告)号：EP0838824A1
公开(公告)日：1998-04-29
申请号：EP97402429.1
申请日：1997-10-15
申请人： SGS-THOMSON MICROELECTRONICS S.A.
发明人： Devin, Jean
IPC分类号： G11C7/00 , G11C16/06
CPC分类号： G11C7/14
摘要： Pour améliorer le temps de lecture d'une mémoire on prévoit de détecter l'instant où une ligne de mots sera complètement chargée en réalisant en bout de cette ligne de mots une cellule mémoire supplémentaire reliée à une ligne de bits supplémentaire. Les cellules mémoires supplémentaires sont toutes dans un état de programmation tel qu'elles permettent la détection d'un courant de lecture positivement. En outre, on s'arrange, en programmant ces cellules d'une manière insuffisante, pour qu'elles se mettent à conduire avant les cellules normales du plan mémoire. On se sert de cet instant pour déclencher la validation de la lecture des cellules du plan mémoire.
摘要翻译： EPROM存储器包括多个单元（7），每个单元包括浮置栅极晶体管。单元连接到位线（8-10）和字线（11-14）以限定由连接到字线（11）的控制栅极（5）控制的阵列。地址信号（ADR）被发送到选择要读取的单元的解码器（16,17）。读取电路（18-20）连接到位线（8-10）的末端。连接仅由解码器选择的位线进行。辅助位线（22）连接到仅包括简单晶体管的附加存储器单元（23-26）。辅助位线经由晶体管（29）连接到读取电路（27）。

37. 发明公开

EP0798729A1 Reference word line and data propagation reproduction circuit, particularly for non-volatile memories provided with hierarchical decoders 失效
标题翻译：基准字线和数据运行时再现电路，特别是用于非液体存储与分层的解码器
公开(公告)号：EP0798729A1
公开(公告)日：1997-10-01
申请号：EP96830160.6
申请日：1996-03-29
申请人： SGS-THOMSON MICROELECTRONICS s.r.l.
发明人： Pascucci, Luigi , Rolandi, Paolo , Fontana, Marco , Barcella, Antonio
IPC分类号： G11C7/00 , G11C16/06
CPC分类号： G11C7/14 , G11C16/28
摘要： A reference word line and data propagation reproduction circuit, particularly for non-volatile memories provided with hierarchical decoders, characterized in that the memory is divided into at least two memory half-matrices that are arranged on different half-planes, and in that the circuit comprises, for each one of the at least two memory half-matrices, a reference unit (3 i ) for each one of the at least two memory half-matrices and an associated unit (4) for reproducing the propagation of the signals along the reference unit, the reference unit (3 i ) and the associated propagation reproduction unit (4) having a structure that is identical to each generic word line of the memory device, the reference and propagation reproduction units of one of the at least two memory half-matrices being activatable upon selection of a memory cell in the other one of the at least two memory half-matrices, in order to provide a reference that is synchronous and symmetrical with respect to the selection of the memory cell for reading it and so as to preset, according to the propagation reproduction unit (4), the conditions for starting correct and certain reading of the selected memory cell.
摘要翻译：参考字线和数据传播再生电路，尤其是用于设置有分层解码器，在DASS特点非易失性存储器管芯存储器被划分成至少两个存储器的半矩阵也被布置在不同的半平面，并且在DASS模具电路包括，对于所述至少两个存储器的半矩阵中的每一个，对于所述至少两个存储器中的每一个半矩阵和相关联的单元（4），用于沿着所述参考再现的信号的传播的参考单元的（3R）单元，参考单元（3I）和相关的传播再现单元（4）具有这样的结构确实是相同的存储装置中，至少两个存储器中的一个半矩阵的参考和传播再现单元中的每个通用字线是在一个存储器单元的选择激活的至少两个存储器的半矩阵中的另一个，以提供一个参考并是同步和对称相对于所述选择用于读取它和所述存储器单元的，以预先设定，gemäß到传播再现单元（4），用于启动和所选择的存储单元的正确阅读某些条件。

38. 发明授权

EP0497962B1 SENSE ENABLE TIMING CIRCUIT FOR A RANDOM ACCESS MEMORY 失效
标题翻译： ABFÜHLFREIGABETAKTSCHALTUNG直接访问存储器
公开(公告)号：EP0497962B1
公开(公告)日：1997-02-26
申请号：EP91915965.7
申请日：1991-08-23
申请人： ANALOG DEVICES, INCORPORATED
发明人： KOKER, Gregory, T.
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C7/22 , G11C7/14 , G11C8/18
摘要： A sense enable timing circuit for addressing data locations in a static random access memory (RAM) array provides a plurality of memory cells formed into a dummy row and a dummy column that is connected to a memory cell at a far end opposite an X-decoder input of said dummy row. The dummy row and column are constructed in conjunction on the same semiconductor chip with a RAM array comprising a plurality of memory cells formed into rows and columns. The dummy column connects to a dummy word line of the dummy row and includes dummy bit lines. Each of the dummy word and bit lines are separate from the word lines and bit lines of the array. The dummy word line is addressed at a time synchronized with the addressing of the array word lines. The occurence of a predetermined voltage change on at least one of the dummy bit lines, carrying a signal of at least one memory cell of the dummy column, is determined in response to the addressing of the dummy word line. In response to this determination, the sensing of array bit line signal is enabled. The signal carried by the dummy bit line may be generated by a plurality of adjacent memory cells. Furthermore, the circuit may include a circuit responsive to the enabling of sensing that amplifies the voltage difference between complementary high and low bit line outputs of the RAM array so that they may equal standard logic values. It may further include a signal generated in response to the predetermined voltage change that deactivates the generation of the bit line signal by a word line.

39. 发明公开

EP0477369A4 EP0477369A4 - 有权
标题翻译： EP0477369A4 - Google专利
公开(公告)号：EP0477369A4
公开(公告)日：1995-03-22
申请号：EP90908645
申请日：1990-06-08
申请人： TOKYO SHIBAURA ELECTRIC CO , TOSHIBA MICRO ELECTRONICS
发明人： IWAHASHI HIROSHI , NAKAI HIROTO , KANAZAWA KAZUHISA , SATO ISAO
IPC分类号： G11C7/14 , G11C16/28 , G11C16/32 , G11C29/00 , G11C16/06 , G11C11/409 , G11C11/413 , G11C17/18
CPC分类号： G11C29/842 , G11C7/14 , G11C16/28 , G11C16/32

40. 发明公开

EP0576046A2 Semiconductor memory device 失效
标题翻译： Halbleiterspeicheranordnung。
公开(公告)号：EP0576046A2
公开(公告)日：1993-12-29
申请号：EP93114324.2
申请日：1989-06-23
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Nakai, Hiroto, c/o Intellectual Property Div. , Iwahashi, Hiroshi, c/o Intellectual Property Div. , Kanazawa, Kazuhisa, c/o Intellectual Property Div. , Kumagai, Shigeru, c/o Intellectual Property Div. , Sato, Isao, c/o Intellectual Property Div.
IPC分类号： G11C7/00 , G11C16/06
CPC分类号： G11C7/12 , G11C7/062 , G11C7/14 , G11C16/28
摘要： In a semiconductor memory device, a first load circuit (14A) is coupled with the column lines (BL1,..., BLn). first dummy cells (DC1,..., DCm) are connected to a dummy column line (DBL), a second load circuit (14B) is connected to the dummy column line, a second dummy cell (DCm+1) is connected to the dummy column line, and a sense amplifier (15) senses the data stored in the memory cell in accordance with a potential difference between the column line and the dummy column line. In semiconductor memory devices thus arranged, the second dummy cell is set in an on state normally. The connection of the second dummy cell with the dummy line changes a current flowing to the dummy line at the time of row line switching, thereby to hold back a rise of the reference potential at the time of the row line switching.
摘要翻译：在半导体存储器件中，第一负载电路（14A）与列线（BL1，...，BLn）耦合。第一虚拟单元（DC1，...，DCm）连接到虚拟列线（DBL），第二负载电路（14B）连接到虚拟列线，第二虚设单元（DCm + 1）虚拟列线和读出放大器（15）根据列线和虚拟列线之间的电位差来感测存储在存储单元中的数据。在这样布置的半导体存储器件中，第二虚设单元被正常地设置为导通状态。第二虚拟单元与虚拟线的连接在行线切换时改变流向虚拟线的电流，从而在行线切换时保持基准电位的上升。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式