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31. 发明公开

EP0489583A2 Multiple processor cache control system 失效
标题翻译： Mehrprozessor-Cachespeichersteuerungsanordnung。
公开(公告)号：EP0489583A2
公开(公告)日：1992-06-10
申请号：EP91311264.5
申请日：1991-12-04
申请人： NCR International, Inc.
发明人： Tipon, Donald G.
IPC分类号： G06F12/08
CPC分类号： G06F15/17375 , G06F12/0813 , G06F12/0817 , G06F2212/2542
摘要： A tightly coupled, cache coherent computer system (100) utilizes a crossbar switch (182) to increase memory system and memory bus bandwidth, thus eliminating bottlenecks. Local directories (118,136,154,172), one for each node (174,176,178,180) keep track of valid data and eliminate bottlenecks associated with cache coherency. The system (100) is also scalable, easily allowing expansion by adding further processors, for example.
摘要翻译：紧密耦合的高速缓存一致计算机系统（100）利用交叉开关（182）来增加存储器系统和存储器总线带宽，从而消除瓶颈。本地目录（118,136,154,172）（每个节点一个（174,176,178,180））跟踪有效数据并消除与高速缓存一致性相关联的瓶颈。系统（100）也是可扩展的，例如通过添加其他处理器容易地允许扩展。

32. 发明公开

EP3311283A1 DATA PROCESSING APPARATUS AND METHOD WITH OWNERSHIP TABLE 有权
标题翻译：数据处理装置和具有所有权表的方法
公开(公告)号：EP3311283A1
公开(公告)日：2018-04-25
申请号：EP16720504.6
申请日：2016-04-28
申请人： ARM Limited
发明人： PARKER, Jason , GRISENTHWAITE, Richard Roy , ROSE, Andrew Christopher
IPC分类号： G06F12/14 , G06F12/10 , G06F12/02
CPC分类号： G06F12/1036 , G06F9/45533 , G06F12/0284 , G06F12/10 , G06F12/1009 , G06F12/109 , G06F12/1441 , G06F12/1475 , G06F12/1483 , G06F2212/151 , G06F2212/2542
摘要： A data processing apparatus (20) comprises processing circuitry (24, 25, 28) to execute a plurality of processes. An ownership table (50) comprises one or more entries (52) each indicating, for a corresponding block of physical addresses, which of the processes is an owner process that has exclusive control of access to the corresponding block of physical addresses.

33. 发明公开

EP2869194A4 EXTENDED CACHE COHERENCE PROTOCOL-BASED MULTI-LEVEL COHERENCE DOMAIN SIMULATION VERIFICATION AND TEST METHOD 审中-公开
标题翻译：测试和测试PROCEDURE ON与多级一致性EXTENDED缓存的一致性基于域仿真甲LOG
公开(公告)号：EP2869194A4
公开(公告)日：2016-08-03
申请号：EP13872015
申请日：2013-10-11
申请人： INSPUR ELECTRONIC INFORMATION INDUSTRY CO LTD
发明人： WANG ENDONG , HU LEIJUN , CHEN JICHENG , ZHANG FENG , ZHOU HENGZHAO , FU YUNYUE , GAN XIAOWEI
IPC分类号： G06F9/455 , G06F11/36 , G06F12/08 , G06F17/50
CPC分类号： G06F11/3608 , G06F11/3664 , G06F12/0815 , G06F12/0837 , G06F17/5009 , G06F2212/2542 , G06F2212/621

34. 发明公开

EP2909728A4 MULTISLOT LINK LAYER FLIT 审中-公开
标题翻译：多时隙，VERBINDUNGSSCHICHTFLIT
公开(公告)号：EP2909728A4
公开(公告)日：2016-06-22
申请号：EP13848818
申请日：2013-03-16
申请人： INTEL CORP
发明人： WILLEY JEFF , BLANKENSHIP ROBERT G , SWANSON JEFFREY C , SAFRANEK ROBERT J
IPC分类号： G06F12/08 , G06F9/30 , G06F9/44 , G06F9/46 , G06F13/40 , G06F13/42 , H04L12/741 , H04L12/933
CPC分类号： G06F13/4282 , G06F1/3287 , G06F8/71 , G06F8/73 , G06F8/77 , G06F9/30145 , G06F9/44505 , G06F9/466 , G06F11/1004 , G06F12/0806 , G06F12/0808 , G06F12/0813 , G06F12/0815 , G06F12/0831 , G06F12/0833 , G06F13/22 , G06F13/4022 , G06F13/4068 , G06F13/4221 , G06F13/4286 , G06F13/4291 , G06F2212/1016 , G06F2212/2542 , G06F2212/622 , H04L9/0662 , H04L12/4641 , H04L45/74 , H04L49/15 , Y02B60/1225 , Y02B60/1228 , Y02B60/1235 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Re-initialization of a link can take place without termination of the link, where the link includes, a transmitter and a receiver are to be coupled to each lane in the number of lanes, and re-initialization of the link is to include transmission of a pre-defined sequence on cach of the lanes.
摘要翻译：链路的重新初始化可以在不终止链路的链路的情况下进行，链路包括，发射机和接收机将以多个通道耦合到每个通道，并且链路的重新初始化包括传输每个通道上的预定义序列。

35. 发明授权

EP2433226B1 FILE SYSTEM 有权转让
标题翻译：文件系统
公开(公告)号：EP2433226B1
公开(公告)日：2015-08-12
申请号：EP10730310.9
申请日：2010-06-25
申请人： Simplivity Corporation
发明人： BEAVERSON, Arthur, J. , BOWDEN, Paul
IPC分类号： G06F17/30 , G06F11/14
CPC分类号： G06F12/1054 , G06F12/0246 , G06F12/0864 , G06F12/0875 , G06F12/1408 , G06F17/30097 , G06F17/30949 , G06F17/30952 , G06F2212/2542 , G06F2212/402 , G06F2212/452 , G06F2212/502 , G06F2212/6032 , G06F2212/7211

36. 发明公开

EP2869194A1 EXTENDED CACHE COHERENCE PROTOCOL-BASED MULTI-LEVEL COHERENCE DOMAIN SIMULATION VERIFICATION AND TEST METHOD 审中-公开
标题翻译：测试和测试PROCEDURE ON与多级一致性EXTENDED缓存的一致性基于域仿真甲LOG
公开(公告)号：EP2869194A1
公开(公告)日：2015-05-06
申请号：EP13872015.6
申请日：2013-10-11
申请人： Inspur Electronic Information Industry Co., Ltd.
发明人： WANG, Endong , HU, Leijun , CHEN, Jicheng , ZHANG, Feng , ZHOU, Hengzhao , FU, Yunyue , GAN, Xiaowei
IPC分类号： G06F9/455
CPC分类号： G06F11/3608 , G06F11/3664 , G06F12/0815 , G06F12/0837 , G06F17/5009 , G06F2212/2542 , G06F2212/621
摘要： An extension Cache Coherence protocol-based multi-level coherency domain simulation verification and test method. An extension Cache Coherence protocol-based multi-level coherency domain CC-NUMA (Cache Coherent Non-Uniform Memory Access) system protocol simulation model is built, a protocol table inquiring and state converting executing mechanism in a key node of a system ensures that a Cache Coherence protocol is maintained in a single computing domain and is simultaneously maintained among a plurality of computing domains, and accuracy and stability of intra-domain and inter-domain transmission are ensured; a credible protocol inlet conversion coverage rate evaluation driven verification method is provided, transactions are processed by loading an optimized transaction generator push model, a coverage rate index is obtained after the operation is ended, and the verification efficiency is increased in comparison with a random transaction promoting mechanism. Through building a multi-processor multi-level coherency domain verification system model and performing relevant simulation verification, the applicability and the effectiveness of the method are further confirmed.

37. 发明公开

EP2652612A1 METHOD AND SYSTEM FOR COMPUTATIONAL ACCELERATION OF SEISMIC DATA PROCESSING 无效
标题翻译：一种用于处理地震数据的方法和系统的名义加速
公开(公告)号：EP2652612A1
公开(公告)日：2013-10-23
申请号：EP11849738.7
申请日：2011-09-20
申请人： Chevron U.S.A. Inc.
发明人： HU, Chaoshun , WANG, Yue , NEMETH, Tamas
IPC分类号： G06F9/46 , G06F9/38
CPC分类号： G06F12/0842 , G06F2212/2542
摘要： A computer-implemented method and a system for computational acceleration of seismic data processing are described. The method includes defining a specific non-uniform memory access (NUMA) scheduling for a plurality of cores in a processor according to data to be processed; and running two or more threads through each of the plurality of cores.

38. 发明公开

EP2608044A1 Information processing apparatus and memory access method 有权
标题翻译： Informationsverarbeitungsvorrichtung und Speicherzugriffsverfahren
公开(公告)号：EP2608044A1
公开(公告)日：2013-06-26
申请号：EP12187771.6
申请日：2012-10-09
申请人： FUJITSU LIMITED
发明人： Koinuma, Hideyuki , Okada, Seishi , Sugizaki, Go
IPC分类号： G06F12/02 , G06F12/14 , G06F12/10
CPC分类号： G06F12/0284 , G06F12/1072 , G06F12/1441 , G06F2212/2542
摘要： A node includes a first converting unit (35) that performs conversion between a logical address and a physical address. The node includes a second converting unit (36) that performs conversion between the physical address and processor identification information for identifying a processor (21) included in a each of a plurality of nodes (10 to 10e). The node includes a transmitting unit (37) that transmits transmission data including the physical address and the processor identification information for accessing to a storing area indicated by the physical address. The node includes a local determining unit (36) that determines whether an access, indicated by the transmission data received from another nodes (10 to 10e), is an access to a local area or an access to a shared area based on the physical address included in the transmission data received by the receiving unit (37).
摘要翻译：节点包括执行逻辑地址和物理地址之间的转换的第一转换单元（35）。该节点包括第二转换单元（36），该第二转换单元（36）执行物理地址和处理器识别信息之间的转换，用于识别包括在多个节点（10至10e）中的每一个中的处理器（21）。节点包括发送单元（37），其发送包括物理地址和处理器识别信息的发送数据，以访问由物理地址指示的存储区域。节点包括本地确定单元（36），其确定由从另一个节点（10至10e）接收的传输数据指示的访问是基于物理地址对本地区域的访问或对共享区域的访问包括在由接收单元（37）接收的发送数据中。

39. 发明授权

EP0817080B1 Multi-level cache memory 失效
标题翻译：多级缓存
公开(公告)号：EP0817080B1
公开(公告)日：2006-12-20
申请号：EP97304726.9
申请日：1997-06-30
申请人： SUN MICROSYSTEMS, INC.
发明人： Hagersten, Erik E. , Hill, Mark D.
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0888 , G06F2212/2542 , G06F2212/272

40. 发明授权

EP1363193B1 Programmable cache for the partitioning of local and remote cache blocks 有权
标题翻译：可编程缓存本地和远程高速缓存块的分割
公开(公告)号：EP1363193B1
公开(公告)日：2006-05-03
申请号：EP03010901.1
申请日：2003-05-15
申请人： Broadcom Corporation
发明人： Rowlands, Joseph B. , Kaza, Rohini Krishna
IPC分类号： G06F12/12
CPC分类号： G06F12/121 , G06F12/0817 , G06F12/12 , G06F2212/2542

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