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1. 发明公开

EP3311281A1 ADDRESS TRANSLATION 有权
标题翻译：地址翻译
公开(公告)号：EP3311281A1
公开(公告)日：2018-04-25
申请号：EP16720505.3
申请日：2016-04-28
申请人： ARM Limited
发明人： PARKER, Jason , GRISENTHWAITE, Richard Roy , ROSE, Andrew Christopher
IPC分类号： G06F12/1018 , G06F12/14 , G06F9/46
CPC分类号： G06F12/1009 , G06F9/468 , G06F12/1018 , G06F12/1036 , G06F12/1458 , G06F12/1491 , G06F21/72 , G06F21/78 , G06F2212/1044 , G06F2212/1052 , G06F2212/151 , G06F2212/651 , G06F2212/657 , G06F2212/681
摘要： A data processing apparatus (20) comprises address translation circuitry (40) to translate a first address into a physical address directly identifying a corresponding location in a data store, and a table (50) comprising one or more entries indexed by the physical address, wherein at least one of the entries specifies the first address from which the corresponding physical address was translated by the address translation circuitry (40).

2. 发明公开

EP1540464A1 DATA PROCESSING SYSTEM HAVING EXTERNAL AND INTERNAL INSTRUCTION SETS 有权
标题翻译：外部和内部指令集数据处理系统
公开(公告)号：EP1540464A1
公开(公告)日：2005-06-15
申请号：EP03797358.3
申请日：2003-05-15
申请人： ARM Limited
发明人： FLAUTNER, Krisztian , ROSE, Andrew Christopher
IPC分类号： G06F9/318
CPC分类号： G06F9/30174 , G06F9/3808 , G06F9/3836 , G06F9/3844 , G06F9/3861
摘要： There is provided a system having: an execution core operable to execute internal instructions; a translation buffer operable to store a plurality of internal instruction blocks of one or more internal instructions, said internal instruction blocks being a dynamic translation of respective external instruction blocks of one or more external instructions; a remapper responsive to an execution request for an external instruction that is within one of said external instruction blocks to identify a corresponding internal instruction block stored within said translation buffer such that one or more internal instructions from said corresponding internal instruction block can be supplied to said execution core.

3. 发明授权

EP3311281B1 ADDRESS TRANSLATION 有权
公开(公告)号：EP3311281B1
公开(公告)日：2019-05-22
申请号：EP16720505.3
申请日：2016-04-28
申请人： ARM Limited
发明人： PARKER, Jason , GRISENTHWAITE, Richard Roy , ROSE, Andrew Christopher
IPC分类号： G06F12/1036 , G06F12/14 , G06F12/1018 , G06F9/46 , G06F21/72 , G06F21/78

4. 发明授权

EP2912559B1 COMMUNICATION OF MESSAGE SIGNALLED INTERRUPTS 有权
标题翻译：消息信令中断的通信
公开(公告)号：EP2912559B1
公开(公告)日：2017-07-26
申请号：EP13759805.8
申请日：2013-08-29
申请人： ARM Limited
发明人： GRISENTHWAITE, Richard Roy , JEBSON, Anthony , ROSE, Andrew Christopher , EVANS, Matthew Lucien
IPC分类号： G06F13/24
CPC分类号： G06F13/26 , G06F13/24

5. 发明公开

EP1402360A2 UNHANDLED OPERATION HANDLING IN MULTIPLE INSTRUCTION SET SYSTEMS 有权
标题翻译：治疗UNTREATED OPERERATIONEN系统中具有多个命令集
公开(公告)号：EP1402360A2
公开(公告)日：2004-03-31
申请号：EP02701432.3
申请日：2002-02-26
申请人： ARM Limited
发明人： NEVILL, Edward Colles , ROSE, Andrew Christopher
IPC分类号： G06F9/455
CPC分类号： G06F9/3802 , G06F9/30149 , G06F9/30174 , G06F9/3816 , G06F9/3861 , G06F9/45504
摘要： Unhandled operation of a program instruction of a first instruction set, such as a Java bytecode, is detected. Instead of invoking a mechanism for directly dealing with that unhandled operation, one or more instructions from a second instruction set, such as ARM instructions, are instead used to emulate the instruction that was subject to the unhandled operation. If these instructions of the second instruction set are also subject to unhandled operation, then the mechanisms for dealing with unhandled operation within that second instruction set may be invoked to repair that operation. This approach is well suited to dealing with unhandled operation of variable length instructions being interpreted with a processor core having a native fixed length instruction set. In particular, prefetch aborts and unhandled floating point operations may be conveniently dealt with in this way.

6. 发明公开

EP1323036A1 STORING STACK OPERANDS IN REGISTERS 有权
标题翻译： SAVING STACK操作数寄存器
公开(公告)号：EP1323036A1
公开(公告)日：2003-07-02
申请号：EP01940825.1
申请日：2001-06-21
申请人： ARM Limited
发明人： NEVILL, Edward Colles , ROSE, Andrew Christopher
IPC分类号： G06F9/45 , G06F9/455 , G06F9/30
CPC分类号： G06F9/4843 , G06F9/30 , G06F9/30134 , G06F9/30149 , G06F9/30174 , G06F9/3802 , G06F9/3814 , G06F9/3853 , G06F9/3861
摘要： A data processing apparatus (102) includes a processor core (104) having a bank of registers (106). The bank of registers (106) include a set of registers that are used for the storage of stack operands. Instructions from a second instruction set specifying stack operands are translated by an instruction translator (108) into instructions of a first instruction set (or control signals corresponding to those instructions) specifying register operands. These translated instructions are then executed by the processor core (104). The instruction translator (108) has multiple mapping states for controlling which registers corresponding to which stack operands within the stack. Changes between mapping states are carried out in dependence of stack operands being added to or removed from the set of registers.

7. 发明公开

EP2912559A1 COMMUNICATION OF MESSAGE SIGNALLED INTERRUPTS 有权
标题翻译： KOMMUNIKATION VON NACHRICHTENSIGNALISIERTEN UNTERBRECHUNGEN
公开(公告)号：EP2912559A1
公开(公告)日：2015-09-02
申请号：EP13759805.8
申请日：2013-08-29
申请人： ARM Limited
发明人： GRISENTHWAITE, Richard Roy , JEBSON, Anthony , ROSE, Andrew Christopher , EVANS, Matthew Lucien
IPC分类号： G06F13/24
CPC分类号： G06F13/26 , G06F13/24
摘要： A global interrupt number space (38) is provided for use in message signalled interrupts. Interrupt destinations (10, 12, 14, 16) are provided with pending interrupt caches (24) with either backing storage provided by global pending status memory (34) shared by all the caches or separate individual pending status memories (56). The interrupt number space may be divided into regions with programmable mapping data being used to indicate which interrupt destinations are responsible for which regions. When interrupts are migrated from one interrupt destination to another, then such programmable mapping data is updated. Pending interrupts may be flushed back to the global pending status memory 34 during the reassignment process such that this pending interrupt data may be picked up by the newly responsible interrupt destination.
摘要翻译：提供全局中断号码空间38用于消息信号中断。中断目的地10,12,14,16具有等待中断高速缓存24，其中由所有高速缓存共享的全局挂起状态存储器34提供的后备存储器或独立的各个未决状态存储器56.中断号码空间可以被划分为具有可编程映射数据用于指示哪些中断目的地负责哪些区域。当中断从一个中断目的地迁移到另一个中断时，则更新这种可编程映射数据。在重新分配过程期间，待处理的中断可以被刷新回到全局挂起状态存储器34，使得该待决中断数据可以被新负责的中断目的地拾取。

8. 发明公开

EP3311283A1 DATA PROCESSING APPARATUS AND METHOD WITH OWNERSHIP TABLE 有权
标题翻译：数据处理装置和具有所有权表的方法
公开(公告)号：EP3311283A1
公开(公告)日：2018-04-25
申请号：EP16720504.6
申请日：2016-04-28
申请人： ARM Limited
发明人： PARKER, Jason , GRISENTHWAITE, Richard Roy , ROSE, Andrew Christopher
IPC分类号： G06F12/14 , G06F12/10 , G06F12/02
CPC分类号： G06F12/1036 , G06F9/45533 , G06F12/0284 , G06F12/10 , G06F12/1009 , G06F12/109 , G06F12/1441 , G06F12/1475 , G06F12/1483 , G06F2212/151 , G06F2212/2542
摘要： A data processing apparatus (20) comprises processing circuitry (24, 25, 28) to execute a plurality of processes. An ownership table (50) comprises one or more entries (52) each indicating, for a corresponding block of physical addresses, which of the processes is an owner process that has exclusive control of access to the corresponding block of physical addresses.

9. 发明公开

EP3311271A1 PROTECTED EXCEPTION HANDLING 有权
标题翻译：受保护的异常处理
公开(公告)号：EP3311271A1
公开(公告)日：2018-04-25
申请号：EP16720485.8
申请日：2016-04-26
申请人： ARM Limited
发明人： PARKER, Jason , GRISENTHWAITE, Richard Roy , ROSE, Andrew Christopher , EVANS, Matthew Lucien
IPC分类号： G06F9/46 , G06F12/14 , G06F12/02 , G06F9/50
CPC分类号： G06F12/1441 , G06F9/45558 , G06F9/461 , G06F9/462 , G06F9/485 , G06F9/5016 , G06F11/0793 , G06F12/023 , G06F12/1425 , G06F2212/1044
摘要： A data processing system for processing data comprising: ownership circuitry to enforce ownership rights of memory regions, a given more privileged state memory region having a given owning process specified from among a plurality of processes, said given owning process having exclusive rights to control access to said given memory region; and context switching circuitry responsive to receipt of an interrupt to trigger a context switch from a first active process to a second active process whereby one or more items of state for use in restarting said first process is saved to one or more context data memory regions owned by said first process and one or more items of state accessible to said second process and dependent upon processing by said first process is overwritten prior to commencing execution of said second process.

10. 发明授权

EP1692613B1 A DATA PROCESSING APPARATUS AND METHOD FOR MOVING DATA BETWEEN REGISTERS AND MEMORY 有权
标题翻译：一种数据处理装置和方法，用于在寄存器和存储器之间移动数据
公开(公告)号：EP1692613B1
公开(公告)日：2018-03-21
申请号：EP04743193.7
申请日：2004-07-01
申请人： ARM Limited
发明人： FORD, Simon Andrew , SYMES, Dominic Hugo , ROSE, Andrew Christopher , LUTZ, David Raymond , HINDS, Christopher Neal
IPC分类号： G06F9/312 , G06F9/30
CPC分类号： G06F9/30167 , G06F9/30025 , G06F9/30036 , G06F9/3004 , G06F9/30145
摘要： A data processing apparatus and method are provided for moving data between registers and memory. The data processing apparatus comprises a register data store having a plurality of registers operable to store data elements. A processor is operable to perform in parallel a data processing operation on multiple data elements accessed in at least one of the registers. Access logic is operable in response to a single access instruction to move a plurality of data elements between specified registers and a continuous block of memory in which data elements are stored as an array of structures having a structure format, the structure format having a plurality of components. The single access instruction identifies the number of components in the structure format, and the access logic is further operable to rearrange the plurality of data elements as they are moved such that each specified register stores data elements of one component whilst in memory the data elements are stored as the array of structures.

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