专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

EP0107416B1 Method of producing semiconductor device 失效
标题翻译：生产半导体器件的方法
公开(公告)号：EP0107416B1
公开(公告)日：1989-09-20
申请号：EP83305971.0
申请日：1983-09-30
申请人： FUJITSU LIMITED
发明人： Ito, Takashi , Sugii, Toshihiro , Fukano, Tetsu , Horie, Hiroshi
IPC分类号： H01L21/31 , H01L21/28
CPC分类号： H01L21/7688 , H01L21/033 , H01L21/31116 , H01L21/32137 , Y10S438/965

32. 发明公开

EP0331555A1 Gettering treatment process 失效
标题翻译： Getterprozess。
公开(公告)号：EP0331555A1
公开(公告)日：1989-09-06
申请号：EP89400470.4
申请日：1989-02-20
申请人： FUJITSU LIMITED
发明人： Sugino, Rinshi , Nara, Yasuo , Ito, Takashi
IPC分类号： H01L21/306 , H01L21/316
CPC分类号： H01L21/02046 , H01L21/02131 , H01L21/02238 , H01L21/02255 , H01L21/02321 , H01L21/02337 , H01L21/02348 , H01L21/31662
摘要： A gettering treatment process comprises the step of irradiating an ultraviolet light onto an insulating layer (a silicon oxide thin layer formed by thermally oxidizing silicon), in a chlorine-containing gas atmosphere. The ultraviolet light (16) excites and dissociates the chlorine-containing gas to generate chlorine radicals which uniformly penetrate the insulating layer, to trap metal impurities within the silicon oxide thin layer.
摘要翻译：吸气处理方法包括在含氯气体气氛中将紫外光照射到绝缘层（通过热氧化硅形成的氧化硅薄膜）上的步骤。紫外光（16）激发并解离含氯气体以产生均匀地穿过绝缘层的氯自由基，以将氧化硅薄层中的金属杂质捕获。

33. 发明公开

EP0246802A3 Process for cleaning surface of semiconductor substrate 失效
标题翻译：半导体衬底表面清洁工艺
公开(公告)号：EP0246802A3
公开(公告)日：1988-05-25
申请号：EP87304228
申请日：1987-05-13
申请人： FUJITSU LIMITED
发明人： Sugino, Rinshi , Ito, Takashi
IPC分类号： H01L21/306
CPC分类号： H01L21/02054 , H01L21/3065
摘要： The surface of a semiconductor substrate can be cleaned effectively by first etching the surface with an atmospherecontaining a free halogen or a halogen compound, irradiated with UV-rays, followed by wet solution cleaning.

34. 发明公开

EP0246802A2 Process for cleaning surface of semiconductor substrate 失效
标题翻译： Verfahren zum Reinigen derOberflächeeines Halbleitersubstrates。
公开(公告)号：EP0246802A2
公开(公告)日：1987-11-25
申请号：EP87304228.7
申请日：1987-05-13
申请人： FUJITSU LIMITED
发明人： Sugino, Rinshi , Ito, Takashi
IPC分类号： H01L21/306
CPC分类号： H01L21/02054 , H01L21/3065
摘要： The surface of a semiconductor substrate can be cleaned effectively by first etching the surface with an atmospherecontaining a free halogen or a halogen compound, irradiated with UV-rays, followed by wet solution cleaning.
摘要翻译：首先用含有游离卤素或卤素化合物的气氛，用紫外线照射，随后进行湿式溶液清洗，来对表面进行有效的清洗。

35. 发明授权

EP0064805B1 Method of producing a metallic thin film on a semiconductor body 失效
标题翻译：在半导体体上生产金属薄膜的方法
公开(公告)号：EP0064805B1
公开(公告)日：1987-08-19
申请号：EP82301513.6
申请日：1982-03-23
申请人： FUJITSU LIMITED
发明人： Ito, Takashi
IPC分类号： H01L21/285 , H01L21/60
CPC分类号： H01L21/7684 , C23C16/12 , H01L21/28512 , H01L21/32051

36. 发明公开

EP0107416A3 Method of producing semiconductor device 失效
标题翻译：生产半导体器件的方法
公开(公告)号：EP0107416A3
公开(公告)日：1986-11-20
申请号：EP83305971
申请日：1983-09-30
申请人： FUJITSU LIMITED
发明人： Ito, Takashi , Sugii, Toshihiro , Fukano, Tetsu , Horie, Hiroshi
IPC分类号： H01L21/31 , H01L21/82
CPC分类号： H01L21/7688 , H01L21/033 , H01L21/31116 , H01L21/32137 , Y10S438/965
摘要： A bipolar or MOS semiconductor device is produced by self-alignment by the steps of (a) forming an insulating film on a semiconductor substrate, (b) forming a first conductive film, (c) forming a first masking film having a window, (d) anisotropically etching the conductive film to form an opening, (e) transversely etching the conductive film to form a protruding portion of the masking film, (f) forming a second masking film on the insulating film through the window, (g) etching an uncovered portion of the insulating film under the protruding portion, and (h) forming a second conductive film connecting the first conductive film and the exposed portion of the semiconductor substrate.

37. 发明公开

EP0046011A3 Semiconductor memory device 失效
公开(公告)号：EP0046011A3
公开(公告)日：1983-08-24
申请号：EP81303162
申请日：1981-07-10
申请人： FUJITSU LIMITED
发明人： Taguchi, Masao , Ito, Takashi
IPC分类号： H01L27/10 , G11C11/24
CPC分类号： H01L27/10808 , G11C11/404
摘要： A semiconductor memory device comprises a number of dynamic memory cells, each consisting of a capacitor (C I ) and a field effect-type switching transistor (Q 2 ) arranged at points of intersection of a plurality of bit lines (BL) and word lines (WL). The source or drain electrode of the transistor (0 2 ) is connected tq a reference potential line (RL) and the other of the source or drain electrode is connected to one electrode of the capacitor (C I ). The bit line (BL) is commonly connected to the other electrode of the capacitors of the memory cells arranged along that bit line (BL). The word line (WL) is commonly connected to the gate electrode of the switching transistors (Q 2 ) of the memory cells arranged along that word line (WL). The area of the capacitor (C 1 ) is greater than the area of an electrode portion connecting the transistor (Q 2 ) to the capacitor (C I ). This enables the area of the capacitor (C 1 ) to be maximised whilst reducing the parasitic capacitance of the lines to a minimum.

38. 发明公开

EP0046011A2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：EP0046011A2
公开(公告)日：1982-02-17
申请号：EP81303162.2
申请日：1981-07-10
申请人： FUJITSU LIMITED
发明人： Taguchi, Masao , Ito, Takashi
IPC分类号： H01L27/10 , G11C11/24
CPC分类号： H01L27/10808 , G11C11/404
摘要： A semiconductor memory device comprises a number of dynamic memory cells, each consisting of a capacitor (C I ) and a field effect-type switching transistor (Q 2 ) arranged at points of intersection of a plurality of bit lines (BL) and word lines (WL). The source or drain electrode of the transistor (0 2 ) is connected tq a reference potential line (RL) and the other of the source or drain electrode is connected to one electrode of the capacitor (C I ). The bit line (BL) is commonly connected to the other electrode of the capacitors of the memory cells arranged along that bit line (BL). The word line (WL) is commonly connected to the gate electrode of the switching transistors (Q 2 ) of the memory cells arranged along that word line (WL). The area of the capacitor (C 1 ) is greater than the area of an electrode portion connecting the transistor (Q 2 ) to the capacitor (C I ). This enables the area of the capacitor (C 1 ) to be maximised whilst reducing the parasitic capacitance of the lines to a minimum.
摘要翻译：一种半导体存储器件包括多个动态存储单元，每个动态存储单元包括布置在多个位线（BL）和字线（WL）的交点处的电容器（CI）和场效应型开关晶体管（Q2））。晶体管（02）的源极或漏极连接到参考电位线（RL），源极或漏极中的另一个连接到电容器（C1）的一个电极。位线（BL）共同连接到沿着位线（BL）布置的存储器单元的电容器的另一电极。字线（WL）共同连接到沿着该字线（WL）布置的存储单元的开关晶体管（Q2）的栅电极。电容器（C1）的面积大于连接晶体管（Q2）和电容器（C1）的电极部分的面积。这使得电容器（C1）的面积最大化，同时将线路的寄生电容降至最小。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式