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21. 发明公开

EP3154077A1 VERFAHREN ZUM HERSTELLEN EINES ELEKTRONISCHEN BAUELEMENTS UND ELEKTRONISCHES BAUELEMENT 审中-公开
标题翻译：方法生产电子部件和电子元件的
公开(公告)号：EP3154077A1
公开(公告)日：2017-04-12
申请号：EP16191719.0
申请日：2016-09-30
申请人： Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
发明人： Dr. Braun, Tanja , Becker, Karl-Friedrich , Kahle, Ruben , Dr. Töpper, Michael
IPC分类号： H01L21/48 , H01L23/538
CPC分类号： H01L23/5387 , H01L21/4846 , H01L21/486 , H01L21/565 , H01L21/568 , H01L23/5384 , H01L23/5386 , H01L24/96 , H01L25/0655 , H01L2224/04105 , H01L2224/24137 , H01L2924/15311 , H01L2924/1815
摘要： Die Erfindung betrifft ein Verfahren zum Herstellen eines elektronischen Bauelements (24) mit den Schritten:
- Bereitstellen einer Halbleiteranordnung (15) umfassend eine Trägerstruktur (8), die mindestens einen in eine Vergussmasse (7) eingebundenen Halbleiterchip (3, 4, 16) aufweist, und eine Umverdrahtungslage (14), die biegbares Material (9) und mindestens eine Leiterbahn (12, 13) aufweist, wobei die Trägerstruktur (8) zumindest bereichsweise mit der Umverdrahtungslage (14) verbunden ist und der mindestens eine Halbleiterchip (3, 4, 16) mit der Umverdrahtungslage (14) elektrisch leitfähig verbunden ist, und
- Trennen der Trägerstruktur (8) entlang mindestens eines Trenngrabens (17, 17', 17", 17"', 17""), derart, dass die Trägerstruktur (8) in mindestens zwei vereinzelte Trägerelemente (20, 21, 22, 23) aufgeteilt wird, wobei zwei benachbarte der vereinzelten Trägerelemente (20, 21, 22, 23) über den jeweiligen Trenngraben (17, 17', 17", 17"', 17"") durch die Umverdrahtungslage (14) miteinander verbunden sind.
摘要翻译：一种用于制造电子元件的方法可包括以下步骤：提供半导体装置，其包含具有结合到封装化合物的至少一个半导体芯片载体结构，其包括柔性材料的再分布层和至少一个带状导体， worin至少局部载体结构被连接到再分布层，并且所述至少一个半导体芯片电传导地连接到再分布层，并以这样的方式寻求DASS管芯载体结构是沿所述至少一个沟槽中分离载体结构分为至少两个单一化的载体元件，该worin载体单一化的元件的两个相邻的通过再分布层的方式彼此连接在respectivement沟槽。

23. 发明公开

EP3136432A1 RESIN STRUCTURE HAVING ELECTRONIC COMPONENT EMBEDDED THEREIN, AND METHOD FOR MANUFACTURING SAID STRUCTURE 审中-公开
标题翻译：根据上述制造这种结构嵌入其中的电子元件和方法树脂结构体
公开(公告)号：EP3136432A1
公开(公告)日：2017-03-01
申请号：EP15783345.0
申请日：2015-03-26
申请人： Omron Corporation
发明人： KAWAI, Wakahiro
IPC分类号： H01L23/28 , B29C45/14 , H01L21/56 , H01L25/04 , H01L25/18 , H05K3/00 , H05K3/28 , H05K5/00
CPC分类号： H01L23/5389 , B29C45/14 , B29C45/14819 , B29K2705/10 , B29L2031/3481 , H01L21/4867 , H01L21/565 , H01L21/568 , H01L23/31 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/48 , H01L24/96 , H01L2224/04105 , H01L2224/05554 , H01L2224/24137 , H01L2224/24195 , H01L2224/451 , H01L2224/48101 , H01L2224/48137 , H01L2224/48195 , H01L2924/00014 , H01L2924/12041 , H01L2924/14 , H01L2924/1815 , H01L2924/19041 , H01L2924/19043 , H01L2924/19105 , H05K1/184 , H05K3/00 , H05K3/28 , H05K5/00 , H01L2224/05599 , H01L2224/85399
摘要： In a resin structure (1) including a resin molded body (5) and a plurality of electronic components (2) embedded in the resin molded body (5), (i) the resin molded body (5) has a plurality of exposed surfaces on which electrodes (3) of the plurality of electronic components (2) are exposed, (ii) the resin molded body (5) has a recess (7) formed therein, and (iii) the recess (7) has a bottom surface (13) which is at least one of the plurality of exposed surfaces.
摘要翻译：在树脂结构（1）包括一个树脂成型体（5）和（2）在所述树脂成型体（5）嵌入的电子部件的复数，（i）所述的树脂成型体（5）具有暴露表面的一个多元化在其上的电极（3）的电子元件（2）的所述多个露出，（ii）所述的树脂成型体（5）具有（7）形成在其中的凹部，和（iii）的凹部（7）具有一个下表面（13），所有这些是暴露的表面的多个的至少一个。

24. 发明公开

EP3128549A1 SEMICONDUCTOR DEVICE, LAYERED SEMICONDUCTOR DEVICE, SEALED-THEN-LAYERED SEMICONDUCTOR DEVICE, AND MANUFACTURING METHODS THEREFOR 审中-公开
标题翻译：半导体部件，分层的半导体部件，密封，然后分层半导体元件及其制造方法
公开(公告)号：EP3128549A1
公开(公告)日：2017-02-08
申请号：EP15773072.2
申请日：2015-03-12
申请人： Shin-Etsu Chemical Co., Ltd.
发明人： TAKEMURA, Katsuya , SOGA, Kyoko , ASAI, Satoshi , KONDO, Kazunori , SUGO, Michihiro , KATO, Hideto
IPC分类号： H01L23/12 , C25D5/02 , C25D7/00 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522 , H01L25/10 , H01L25/11 , H01L25/18 , H05K1/11 , H05K3/28 , H05K3/40
CPC分类号： H01L23/12 , B23K1/0016 , B29C70/78 , B29C70/882 , B29K2063/00 , B29K2083/00 , B29K2105/20 , B29K2995/0005 , B29L2031/3493 , C23C14/042 , C23C14/34 , C23C14/58 , C25D3/60 , C25D5/022 , C25D5/48 , C25D5/505 , C25D5/54 , C25D7/00 , C25D7/123 , H01L21/02282 , H01L21/4857 , H01L21/563 , H01L21/568 , H01L23/3107 , H01L23/49816 , H01L23/49827 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/82 , H01L25/03 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/04105 , H01L2224/12105 , H01L2224/16227 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73267 , H01L2224/82005 , H01L2224/92244 , H01L2225/06513 , H01L2225/06541 , H01L2225/1035 , H01L2225/1058 , H01L2924/3511 , H05K3/3436 , H05K2201/10515 , H05K2201/1053 , H01L2224/19 , H01L2224/83005
摘要： The present invention is a semiconductor apparatus including a semiconductor device, an on-semiconductor-device metal pad and a metal interconnect each electrically connected to the semiconductor device, a through electrode and a solder bump each electrically connected to the metal interconnect, a first insulating layer on which the semiconductor device is placed, a second insulating layer formed on the semiconductor device, a third insulating layer formed on the second insulating layer, wherein the metal interconnect is electrically connected to the semiconductor device via the on-semiconductor-device metal pad at an upper surface of the second insulating layer, penetrates the second insulating layer from its upper surface, and is electrically connected to the through electrode at an lower surface of the second insulating layer, and an under-semiconductor-device metal interconnect is disposed between the first insulating layer and the semiconductor device, and the under-semiconductor-device metal interconnect is electrically connected to the metal interconnect at the lower ' surface of the second insulating layer. This semiconductor apparatus can be easily placed on a circuit board and stacked, and can reduce its warpage even with dense metal interconnects.
摘要翻译：本发明是一种半导体装置，导通半导体器件的金属焊盘和金属互连的每个电连接到所述半导体器件中，通过电极和焊料凸块的每个电连接到所述金属互连，第一绝缘的半导体装置在其上的半导体器件被置于层，形成在半导体器件上形成第二绝缘层，形成在第二绝缘层上的第三绝缘层，worin金属互连电连接到所述半导体器件经由所述上半导体器件的金属垫在在所述第二绝缘层的上表面上，贯穿其上表面上的第二绝缘层，以及电连接到所述贯通电极在在所述第二绝缘层的下表面上，并在下半导体器件的金属互连件之间设置在第一绝缘层和所述半导体器件中，和下半导体的设备金属互连在所述第二绝缘层的下部“表面电连接至所述金属互连。该半导体装置可以被容易地放置在电路板上并堆叠，并能减少其翘曲即使致密的金属互连件。

25. 发明公开

EP3127405A1 VERFAHREN ZUR HERSTELLUNG EINER LEITERPLATTE MIT ZUMINDEST EINER OPTOELEKTRONISCHEN KOMPONENTE 审中-公开
标题翻译：一种用于生产电路板，至少一个光电组件
公开(公告)号：EP3127405A1
公开(公告)日：2017-02-08
申请号：EP15715131.7
申请日：2015-03-25
申请人： AT & S Austria Technologie & Systemtechnik Aktiengesellschaft
发明人： LANGER, Gregor
IPC分类号： H05K1/18 , H05K1/02 , G02B6/43
CPC分类号： H05K1/188 , G02B6/43 , H01L24/19 , H01L24/20 , H01L2224/04105 , H01L2224/06181 , H01L2224/2518 , H01L2224/48091 , H01L2224/48227 , H05K1/0206 , H05K1/0209 , H05K1/0274 , H05K2201/10106 , H05K2201/10121 , H05K2201/10522 , H01L2924/00014
摘要： The invention relates to a method for producing a circuit board having at least one optoelectronic component, which method is characterized by the following steps: a) applying a transparent curable adhesive layer (1) to a carrier layer (2), b) placing at least one optoelectronic component (3) onto the adhesive layer (1) by means of an optically relevant side (4) of the component, c) curing the adhesive layer (1) into a window element (1'), d) embedding the component (3) in a circuit-board composite, e) structuring the carrier layer (2) in order to at least partially expose the window element (1') and to contact the component (3).
摘要翻译：本发明涉及一种用于制造具有至少一个光电部件，该方法是通过以下步骤为特征的电路基板：a）将一个透明的可固化粘合剂层（1）到载体层（2）中，b）在将（4）组分，c）该粘合剂层的固化（1）插入的窗元件（1“）中，d）嵌入至少一个光电部件（3）到粘合剂层（1）由光学相关侧的方式在电路板的复合，E成分（3））构成所述载体层（2）（以至少部分地露出窗元件（1“）和接触部件3）。

27. 发明公开

EP3111734A1 VERFAHREN ZUM KONTAKTIEREN EINES IN EINE LEITERPLATTE EINGEBETTETEN BAUELEMENTS SOWIE LEITERPLATTE 有权
标题翻译：方法用于接触在一块电路板上和嵌入式器件的电路板
公开(公告)号：EP3111734A1
公开(公告)日：2017-01-04
申请号：EP15716392.4
申请日：2015-02-26
申请人： AT & S Austria Technologie & Systemtechnik Aktiengesellschaft
发明人： WEIDINGER, Gerald , ZLUC, Andreas
IPC分类号： H05K1/18 , H05K3/10 , H01L23/538
CPC分类号： H05K1/188 , H01L23/13 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L2224/04105 , H01L2224/24227 , H01L2224/32225 , H01L2224/73267 , H01L2224/92244 , H01L2924/15153 , H05K3/064 , H05K3/108 , H05K3/30 , H05K2201/10674
摘要： The invention relates to a method for making contact with a component (6) embedded in a printed circuit board (13), which method has the following steps: a) providing a core (1) which has at least one insulating layer (2) and at least one conductor layer (3, 4) applied to the insulating layer (2), b) embedding at least one component (6) in a depression (5) in the insulating layer (2), wherein the contact pins (8) of the component (6) are located substantially in the plane of an outer surface of the core (1) having the at least one conductor layer (4), c) applying a varnish (9) that can be photo-structured to the one outer surface of the core (1) on which the component (6) is arranged, filling the spaces between the contact pins (8) of the component (6), d) exposing end faces of the contact pins (8) and the regions of the conductor layer (4) covered by the varnish (9) that can be photo-structured, by illuminating and developing the varnish (9) that can be photo-structured, e) by applying a semi-additive process, depositing a layer (10) of conductor material on the exposed end faces of the contact pins (8) and the exposed regions of the conductor layer (4), and forming a conductor structure (12-12), at least on the one outer surface of the core (1) on which the component (6) is arranged, and on the connecting lines (11) between the contact pins (8) and the conductor structure (12-12), and f) removing the regions of the conductor layer (4+10) that do not belong to the conductor structure (12-12).
摘要翻译：本发明涉及的方法用于接触一个部件（6）嵌入在印刷电路板（13），该方法具有以下步骤：a）提供一个芯体（1），其具有至少一个绝缘层（2）和至少一个导体层（3，4）施加到所述绝缘层（2），b）中嵌入至少一个部件（6）中的凹陷（5）的绝缘层（2）中，worin接触销（8 ）组分（6）基本上位于所述芯的外表面的平面（1），其具有至少一个导体层（4），c）将清漆（9），可光致结构化的芯的一个外表面（1）在其上的组分（6）布置，填充接触销之间的空间（8）的部件（6）中，d）将所述接触销的端面（8）和（4）包括的清漆（9）确实可以是光结构化，通过照射和由applyin显影清漆（9）确实可以是光结构化，E），导体层的区域 GA半加成法，在接触销（8）和所述导体层（4），和形成导体结构的暴露区域的露出端面沉积导体材料层（10）（12-12）至少在芯的一个外表面（1）在其上的组分（6）设置，并在接触销（8）和该导体结构（12-12），和f之间的连接线（11））去除所述导体层（4 + 10）的区域中没有不属于该导体结构（12-12）。

28. 发明公开

EP3107120A1 POWER SEMICONDUCTOR MODULE 审中-公开
标题翻译：功率半导体模块
公开(公告)号：EP3107120A1
公开(公告)日：2016-12-21
申请号：EP16171741.8
申请日：2016-05-27
申请人： Delta Electronics Int'l (Singapore) Pte Ltd
发明人： Lai, Yiu-Wai , Chen, Da-Jung
IPC分类号： H01L25/11 , H01L25/18 , H01L23/538
CPC分类号： H02M7/003 , H01L23/36 , H01L23/3735 , H01L23/5384 , H01L23/5389 , H01L24/18 , H01L24/20 , H01L24/24 , H01L25/115 , H01L25/18 , H01L2224/04105 , H01L2224/18 , H01L2224/24137 , H01L2224/32225 , H01L2224/73267 , H01L2924/15153 , H05K1/0206 , H05K1/0207 , H05K7/209 , H05K2201/066 , H05K2201/10053 , H05K2201/10166 , H05K2201/10174 , H05K2201/10416
摘要： A power module (1, 10, 11, 12) includes a substrate (2), a first sub-module (3, 6, 8) and a second sub-module (4, 7, 9). The substrate (2) includes plural first conducting parts (20), plural second conducting parts (21) and a third conducting part (22). The first sub-module (3, 6, 8) is disposed on the substrate (2), and includes a first semiconductor switch (30), a first diode (31), a first electrode (320), a second electrode (321) and a third electrode (322). The first electrode (320) and the second electrode (321) are electrically connected with the corresponding first conducting parts (20). The third electrode (322) is electrically connected with the third conducting part (22). The second sub-module (4, 7, 9) is disposed on the substrate (2), and includes a second semiconductor switch (40), a second diode (41), a fourth electrode (420), a fifth electrode (421) and a sixth electrode (422). The fourth electrode (420) and the fifth electrode (421) are electrically connected with the corresponding second conducting parts (21). The sixth electrode (422) is electrically connected with the third conducting part (22).
摘要翻译：功率模块（1,10,11,12）包括基板（2），第一子模块（3,6,8）和第二子模块（4,7,9）。衬底（2）包括多个第一导电部分（20），多个第二导电部分（21）和第三导电部分（22）。第一子模块（3,6,8）设置在基板（2）上，并且包括第一半导体开关（30），第一二极管（31），第一电极（320），第二电极）和第三电极（322）。第一电极（320）和第二电极（321）与相应的第一导电部分（20）电连接。第三电极（322）与第三导电部分（22）电连接。第二子模块（4,7,9）设置在基板（2）上，并且包括第二半导体开关（40），第二二极管（41），第四电极（420），第五电极（421 ）和第六电极（422）。第四电极（420）和第五电极（421）与相应的第二导电部分（21）电连接。第六电极（422）与第三导电部分（22）电连接。

29. 发明公开

EP3070739A3 SEMICONDUCTOR DEVICE AND WAFER LEVEL PACKAGE INCLUDING SUCH SEMICONDUCTOR DEVICE 审中-公开
标题翻译：包括这种半导体器件的半导体器件和晶片级封装
公开(公告)号：EP3070739A3
公开(公告)日：2016-12-07
申请号：EP16153575.2
申请日：2016-02-01
申请人： MediaTek, Inc
发明人： SYU, Shih-Yi , HSIEH, Tung-Hsien , CHOU, Che-Ya
IPC分类号： H01L23/522 , H01L23/538 , H01L23/485 , H01L23/31 , H01L23/66
CPC分类号： H01L23/5386 , H01L23/291 , H01L23/3171 , H01L23/3192 , H01L23/49811 , H01L23/49838 , H01L23/5226 , H01L23/525 , H01L23/53228 , H01L23/5384 , H01L23/66 , H01L24/05 , H01L24/09 , H01L24/17 , H01L24/20 , H01L24/24 , H01L24/25 , H01L24/96 , H01L25/0655 , H01L2224/02331 , H01L2224/0401 , H01L2224/04105 , H01L2224/05008 , H01L2224/05013 , H01L2224/05015 , H01L2224/05022 , H01L2224/05124 , H01L2224/05147 , H01L2224/05553 , H01L2224/05555 , H01L2224/05569 , H01L2224/05572 , H01L2224/05647 , H01L2224/12105 , H01L2224/13147 , H01L2224/19 , H01L2224/24137 , H01L2224/244 , H01L2224/245 , H01L2224/25175 , H01L2224/73209 , H01L2924/01029 , H01L2924/14 , H01L2924/18162 , H01L2924/3025 , H01L2924/00012 , H01L2924/00014
摘要： An RDL structure on a passivation layer includes a first landing pad disposed directly above a first on-chip metal pad; a first via in a passivation layer to electrically connecting the first landing pad with the first on-chip metal pad; a second landing pad disposed directly above the second on-chip metal pad; a second via in the passivation layer to electrically connecting the second landing pad with the second on-chip metal pad; and at least five traces being disposed on the passivation layer and passing through a space between the first landing pad and the second landing pad.
摘要翻译：钝化层上的RDL结构包括直接设置在第一片上金属焊盘上方的第一焊盘; 在钝化层中的第一通孔，以将所述第一连接焊盘与所述第一片上金属焊盘电连接; 直接设置在所述第二片上金属焊盘之上的第二焊盘; 在所述钝化层中的第二通孔，以将所述第二着陆焊盘与所述第二片上金属焊盘电连接; 并且至少五条迹线设置在钝化层上并且穿过第一连接焊盘和第二连接焊盘之间的空间。

30. 发明公开

EP3057132A3 MICROELECTRONIC PACKAGE WITH SURFACE MOUNTED PASSIVE ELEMENT 审中-公开
标题翻译：与表面微电子封装安装的无源元件
公开(公告)号：EP3057132A3
公开(公告)日：2016-11-09
申请号：EP15197168.6
申请日：2015-12-01
申请人： MediaTek, Inc
发明人： YEH, Chao-Yang , UNG, Chee-Kong , LIN, Tzu-Hung , FANG, Jia-Wei
IPC分类号： H01L25/16 , H01L21/60
CPC分类号： H01L28/40 , H01L23/3157 , H01L23/49816 , H01L24/09 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/32 , H01L24/73 , H01L24/92 , H01L25/16 , H01L28/10 , H01L28/20 , H01L2224/02371 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/131 , H01L2224/16227 , H01L2224/16265 , H01L2224/32225 , H01L2224/73204 , H01L2224/92125 , H01L2924/15159 , H01L2924/15311 , H01L2924/18162 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19103 , H01L2924/19104 , H01L2924/014
摘要： A microelectronic package includes a packaging substrate (20) having a chip mounting surface (20a); a chip (10) mounted on the chip mounting surface of the packaging substrate with the chip's active surface facing down to the chip mounting surface; a plurality of input/output (I/O) pads (11) distributed on the active surface of the chip; and a discrete passive element (30) mounted on the active surface of the chip. The discrete passive element may be a decoupling capacitor, a resistor, or an inductor.

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