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21. 发明公开

EP2637207A1 Semiconductor wafer with high thermal conductivity 审中-公开
标题翻译：具有高导热性的半导体晶圆
公开(公告)号：EP2637207A1
公开(公告)日：2013-09-11
申请号：EP13166824.6
申请日：2007-01-26
申请人： MEMC Electronic Materials, Inc.
发明人： Seacrist, Michael R.
IPC分类号： H01L27/02 , H01L29/36 , H01L29/02 , H01L21/22 , H01L21/02 , H01L31/0352
CPC分类号： H01L21/30608 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/22 , H01L21/2253 , H01L27/14601 , H01L27/1464 , H01L29/02 , H01L29/36 , H01L31/03529
摘要： This invention generally relates to an epitaxial silicon semiconductor wafer with increased thermal conductivity to transfer heat away from a device layer, while also having resistance to common failure mechanisms, such as latch-up failures and radiation event failures. The semiconductor wafer comprises a lightly-doped device layer, a highly-doped protective layer, and a lightly-doped substrate. The invention is also directed to a process for forming such an epitaxial silicon wafer.
摘要翻译：本发明总体上涉及一种具有增加的导热性的外延硅半导体晶片，以将热量从器件层转移走，同时还具有对常见失效机理（例如闭锁失效和辐射事件失效）的抵抗力。半导体晶片包括轻掺杂器件层，高掺杂保护层和轻掺杂衬底。本发明还涉及形成这种外延硅晶片的工艺。

22. 发明公开

EP2595177A3 Lattice-mismatched semiconductor structures with reduced dislocation defect densities related methods for device fabrication 审中-公开
标题翻译：具有减少的位错缺陷密度的晶格不匹配的半导体结构与器件制造相关的方法
公开(公告)号：EP2595177A3
公开(公告)日：2013-07-17
申请号：EP13155286.1
申请日：2006-05-17
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Cheng, Zhiyuan , Currie, Matthew T. , Lochtefeld, Anthony J. , Fiorenza, James , Langdo, Thomas A. , Braithwaite, Glyn
IPC分类号： H01L21/20 , H01L21/02 , H01L29/66 , H01L29/78 , H01L21/762
CPC分类号： H01L21/02647 , H01L21/02381 , H01L21/0245 , H01L21/0251 , H01L21/02521 , H01L21/02532 , H01L21/0254 , H01L21/02639 , H01L21/7624 , H01L21/8258 , H01L29/66795 , H01L29/785
摘要： Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.
摘要翻译：具有有限区域区域的单片晶格失配半导体异质结构的制造，所述有限区域具有基本上耗尽穿透位错的上部，以及基于这种晶格失配的异质结构制造半导体器件。

23. 发明公开

EP2540662A3 Graphene structure and method of manufacturing the graphene structure, and graphene device and method of manufacturing the graphene device 有权转让
标题翻译：图结构以及制备该图形结构的过程，图形设备和方法用于制备图形设备
公开(公告)号：EP2540662A3
公开(公告)日：2013-06-12
申请号：EP12173032.9
申请日：2012-06-21
申请人： Samsung Electronics Co., Ltd. , Sungkyunkwan University Foundation For Corporate Collaboration
发明人： Choi, Byoung-lyong , Lee, Eun-kyung , Whang, Dong-mok
IPC分类号： B82B1/00 , B82B3/00 , H01L29/10 , H01L29/775 , H01L29/16 , H01L29/06 , H01L29/66 , H01L21/02 , H01L29/78 , H01L29/786
CPC分类号： H01L29/1606 , B82Y10/00 , B82Y30/00 , B82Y40/00 , H01L21/02164 , H01L21/02381 , H01L21/0245 , H01L21/02491 , H01L21/02527 , H01L21/0262 , H01L21/02639 , H01L21/02645 , H01L29/0673 , H01L29/66045 , H01L29/66439 , H01L29/66742 , H01L29/775 , H01L29/785 , H01L29/78684 , H01L29/78696
摘要： A graphene structure and a method of manufacturing the graphene structure, and a graphene device and a method of manufacturing the graphene device. The graphene structure includes a substrate; a growth layer disposed on the substrate and having exposed side surfaces; and a graphene layer disposed on the side surfaces of the growth layer. A growth layer 120 and a protective layer 130 are sequentially formed on a substrate 110. The growth layer 120 is a layer from which a graphene layer 140 grows, and may be formed of for example, metal or germanium (Ge). The growth layer 120 may have a thickness of, for example, about several nanometers. As will be described later, the thickness of the growth layer 120 determines a width W of the graphene layer 140. Then, the protective layer 130 is formed on an upper surface of the growth layer 120. A groove 150 is formed in the protective layer 130 and the growth layer 120. The groove 150 is formed in a predetermined shape by sequentially etching the protective layer 130 and the growth layer 120. The groove 150 exposes side surfaces of the protective layer 130 and the growth layer 120 and an upper surface of the substrate 110. The groove 150 may be formed by etching the protective layer 130 and the growth layer 120 by using an etching mask until the upper surface of the substrate 110 is exposed. FIG. 3A is a perspective view showing that the graphene layer 140 is grown from the side surfaces of the growth layer 120.

24. 发明授权

EP2434034B1 Procédé pour éliminer les résidus de catalyseur métallique à la surface de nano-fils 有权
标题翻译：一种用于去除金属催化剂的过程从纳米线表面的残基
公开(公告)号：EP2434034B1
公开(公告)日：2013-01-30
申请号：EP11306078.4
申请日：2011-08-29
申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
发明人： Perraud, Simon , Coronel, Philippe
IPC分类号： B82Y40/00 , C30B29/60 , C30B33/08 , H01L29/06 , H01L21/02
CPC分类号： H01L29/0676 , B82Y40/00 , H01L21/0245 , H01L21/02463 , H01L21/02521 , H01L21/02532 , H01L21/02546 , H01L21/02603 , H01L21/02645 , H01L21/02664

25. 发明公开

EP2267762A3 Semiconductor heterostructures having reduced dislocation pile-ups and related methods 审中-公开
标题翻译：半导体异质结构与位错和制备适当的方法的积累降低
公开(公告)号：EP2267762A3
公开(公告)日：2012-08-22
申请号：EP10183272.3
申请日：2003-08-22
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Leitz, Christopher , Vineis, Christopher , Westhoff, Richard , Yang, Vicky , Currie, Matthew
IPC分类号： H01L21/20 , H01L21/02 , C30B25/02 , C30B29/52 , H01L21/8238
CPC分类号： H01L21/0251 , C30B23/025 , C30B23/066 , C30B25/02 , C30B25/183 , C30B29/52 , H01L21/02381 , H01L21/0245 , H01L21/02505 , H01L21/02532 , H01L21/0262 , H01L21/823807
摘要： Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.

26. 发明授权

EP1509949B1 FORMATION OF LATTICE-TUNING SEMICONDUCTOR SUBSTRATES 有权
标题翻译：培训LATTICE半导体衬底投票
公开(公告)号：EP1509949B1
公开(公告)日：2012-08-22
申请号：EP03755984.6
申请日：2003-05-30
申请人： AdvanceSis Limited
发明人： CAPEWELL, Adam, Daniel , GRASBY, Timothy, John , PARKER, Evan Hubert , WHALL, Terence
IPC分类号： H01L21/20 , H01L21/02 , C30B23/02 , C30B25/02 , C30B29/52
CPC分类号： C30B23/02 , C30B25/02 , C30B29/52 , H01L21/02381 , H01L21/0245 , H01L21/02505 , H01L21/0251 , H01L21/02532 , H01L21/02617
摘要： In order to reduce dislocation pile-ups in a virtual substrate, a buffer layer 32 is provided, between an underlying Si substrate 34 and an uppermost constant composition SiGe layer 36 , which comprises alternating graded SiGe layers 38 and uniform SiGe layers 40 . During the deposition of each of the graded SiGe layers 38 the Ge fraction x is linearly increased from a value corresponding to the Ge composition ratio of the preceding layer to a value corresponding to the Ge composition ratio of the following layer. Furthermore the Ge fraction x is maintained constant during deposition of each uniform SiGe layer 40 , so that the Ge fraction x varies in step-wise fashion through the depth of the buffer layer. After the deposition of each pair of graded and uniform SiGe layers 38 and 40 , the wafer is annealed at an elevated temperature greater than the temperature at which the layers have been deposited. Each graded SiGe layer is permitted to relax by pile-ups of dislocations, but the uniform SiGe layers 40 prevent the pile-ups of dislocations from extending out of the graded SiGe layers 38 . Furthermore each of the subsequent annealing steps ensures that the previously applied graded and uniform SiGe layers 38 and 40 are fully relaxed in spite of the relative thinness of these layers. As a result the dislocations are produced substantially independently within successive pairs of layers 38 and 40 , and are relatively evenly distributed with only small surface undulations 40 being produced. Furthermore the density of threading dislocations is greatly reduced, thus enhancing the performance of the virtual substrate by decreasing the disruption of the atomic lattice which can lead to scattering of electrons in the active devices and degradation of the speed of movement of the electrons.

27. 发明公开

EP2423951A3 Antiphase domain boundary-free III-V compound semiconductor material on semiconductor substrate and method for manufacturing thereof 有权
标题翻译：在半导体衬底上的反相域无边界III-V族化合物半导体材料及其制造方法
公开(公告)号：EP2423951A3
公开(公告)日：2012-03-07
申请号：EP11176589.7
申请日：2011-08-04
申请人： IMEC , Katholieke Universiteit Leuven, K.U. Leuven R&D
发明人： Wang, Gang , Caymax, Matty , Leys, Maarten , Wang, Wei-E , Waldron, Niamh
IPC分类号： H01L21/20 , H01L21/02
CPC分类号： H01L21/02538 , H01L21/02381 , H01L21/0245 , H01L21/02461 , H01L21/02463 , H01L21/02502 , H01L21/02543 , H01L21/02546 , H01L21/0262 , H01L21/02639
摘要： Method for manufacturing a III-V compound semiconductor material comprising: providing a substrate made of a first semiconductor material having a {001} orientation, an insulating layer overlying and in contact with the substrate and a recessed region in the insulating layer which exposes the substrate; forming a buffer layer of a group IV semiconductor material overlying and in contact with the exposed substrate in the recessed region; applying a thermal treatment at a temperature higher or equal to a roughening temperature of the group IV semiconductor for roughening the surface of the buffer layer, such that the buffer layer takes a rounded shape having a double stepped surface; and filling at least partially the recessed region with a III-V compound semiconductor material which is overlying and in contact with the double stepped surface of the buffer layer.
摘要翻译：用于制造III-V族化合物半导体材料的方法，包括：提供由具有{001}取向的第一半导体材料制成的衬底，覆盖并接触衬底的绝缘层以及暴露衬底的绝缘层中的凹陷区域 ; 在所述凹陷区域中形成覆盖并与所述暴露的衬底接触的IV族半导体材料的缓冲层; 在高于或等于IV族半导体的粗糙化温度的温度下进行热处理，以使所述缓冲层的表面粗糙化，使得所述缓冲层为具有双阶梯表面的圆形; 以及用III-V族化合物半导体材料至少部分地填充凹陷区域，所述III-V族化合物半导体材料覆盖并接触缓冲层的双阶梯表面。

28. 发明公开

EP2423951A2 Antiphase domain boundary-free III-V compound semiconductor material on semiconductor substrate and method for manufacturing thereof 有权
标题翻译：上的半导体基板及其制造方法限制免费的反相域III-V族化合物半导体材料或其
公开(公告)号：EP2423951A2
公开(公告)日：2012-02-29
申请号：EP11176589.7
申请日：2011-08-04
申请人： IMEC , Katholieke Universiteit Leuven, K.U. Leuven R&D
发明人： Wang, Gang , Caymax, Matty , Leys, Maarten , Wang, Wei-E , Waldron, Niamh
IPC分类号： H01L21/20 , H01L21/02
CPC分类号： H01L21/02538 , H01L21/02381 , H01L21/0245 , H01L21/02461 , H01L21/02463 , H01L21/02502 , H01L21/02543 , H01L21/02546 , H01L21/0262 , H01L21/02639
摘要： Method for manufacturing a III-V compound semiconductor material comprising: providing a substrate made of a first semiconductor material having a {001} orientation, an insulating layer overlying and in contact with the substrate and a recessed region in the insulating layer which exposes the substrate; forming a buffer layer of a group IV semiconductor material overlying and in contact with the exposed substrate in the recessed region; applying a thermal treatment at a temperature higher or equal to a roughening temperature of the group IV semiconductor for roughening the surface of the buffer layer, such that the buffer layer takes a rounded shape having a double stepped surface; and filling at least partially the recessed region with a III-V compound semiconductor material which is overlying and in contact with the double stepped surface of the buffer layer.
摘要翻译：用于制造III-V族化合物半导体材料的方法，包括：提供具有一个{001}取向由第一半导体材料的基板，在绝缘层上覆且与绝缘层中的底物和凹陷区域接触暴露所述基板 ; 形成与在凹进区域的曝光的衬底接触的IV族半导体材料上覆的和的缓冲层; 在高于或等于所述IV族半导体的粗糙化温度为粗糙化缓冲层的表面的温度下施加热处理，检查并在缓冲层需要具有双台阶表面的圆形形状; 和填充至少部分地凹陷区域与III-V族化合物半导体材料的所有被覆盖并与所述缓冲层的双台阶面接触。

29. 发明公开

EP2302681A1 Improved semiconductor sensor structures with reduced dislocation defect densities and related methods for the same 有权
标题翻译： VERBESSERTE HALBLEITERSENSORSTRUKTUREN MIT VERRINGERTEN VERSETZUNGSDEFEKTDICHTEN
公开(公告)号：EP2302681A1
公开(公告)日：2011-03-30
申请号：EP10003084.0
申请日：2010-03-23
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Cheng, Zhi-Yuan , Fiorenza, James G. , Sheen, Calvin , Lochtefeld, Anthony J.
IPC分类号： H01L27/146 , H01L21/20 , H01L21/02
CPC分类号： H01L27/14643 , H01L21/02381 , H01L21/0245 , H01L21/0251 , H01L21/02532 , H01L21/02642 , H01L21/02647 , H01L27/14603 , H01L27/14632 , H01L27/14687 , H01L27/14689 , H01L31/035281 , H01L31/18
摘要： Non-silicon based semiconductor devices are integrated into silicon fabrication processes by using aspect-ratio-trapping materials. Non-silicon light-sensing devices in a least a portion of a crystalline material can output electrons generated by light absorption therein. Exemplary light-sensing devices can have relatively large micron dimensions. As an exemplary application, complementary-metal-oxide-semiconductor photodetectors are formed on a silicon substrate by incorporating an aspect-ratio-trapping technique.
摘要翻译：非硅基半导体器件通过使用纵横比捕获材料集成到硅制造工艺中。结晶材料的至少一部分中的非硅光感测装置可以输出由其中的光吸收产生的电子。示例性的光感测装置可以具有相对较大的微米尺寸。作为示例性应用，通过结合纵横比捕获技术在硅衬底上形成互补金属氧化物半导体光电探测器。

30. 发明公开

EP1708254A4 PROCESS FOR PRODUCING MONOCRYSTAL THIN FILM AND MONOCRYSTAL THIN FILM DEVICE 审中-公开
标题翻译：工艺单结晶薄膜和薄膜器件单晶
公开(公告)号：EP1708254A4
公开(公告)日：2010-11-24
申请号：EP04807552
申请日：2004-12-22
申请人： JAPAN SCIENCE & TECH AGENCY
发明人： NODA SUGURU
IPC分类号： H01L21/20 , C23C16/01 , C30B25/02 , C30B29/06 , C30B33/00 , H01L21/205 , H01L31/0392 , H01L31/04 , H01L31/18
CPC分类号： H01L31/1804 , C30B25/02 , C30B29/06 , C30B33/00 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02634 , H01L21/02664 , H01L31/03921 , Y02E10/547 , Y02P70/521

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