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21. 发明公开

EP0718768A1 Single-chip microcomputer 失效
标题翻译：单片机
公开(公告)号：EP0718768A1
公开(公告)日：1996-06-26
申请号：EP96102994.9
申请日：1994-08-10
申请人： HITACHI, LTD. , HITACHI MICROCOMPUTER SYSTEM LTD.
发明人： Kawasaki, Shumpei , Akao, Yasushi , Noguchi, Kouki , Hasegawa, Atsushi , Ohsuga, Hiroshi , Kurakazu, Keiichi , Matsubara, Kiyoshi , Hayakawa, Akio , Ito, Yoshitaka
IPC分类号： G06F12/08 , G06F15/78
CPC分类号： G06F9/3001 , G06F12/0893 , G06F13/36 , G06F13/405 , G06F15/7817 , H04W28/08 , H04W52/0216 , H04W88/02 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D70/142 , Y02D70/26
摘要： A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.

22. 发明公开

EP0646873A3 Single-chip microcomputer 失效
标题翻译：单片机
公开(公告)号：EP0646873A3
公开(公告)日：1995-09-20
申请号：EP94112520.5
申请日：1994-08-10
申请人： HITACHI, LTD. , HITACHI MICROCOMPUTER SYSTEM LTD.
发明人： Kawasaki, Shumpei , Akao, Yasushi , Noguchi, Kouki , Hasegawa, Atsushi , Ohsuga, Hiroshi , Kurakazu, Keiichi , Matsubara, Kiyoshi , Hayakawa, Akio , Ito, Yoshitaka
IPC分类号： G06F13/40 , G06F15/78 , G06F12/08 , G06F13/42
CPC分类号： G06F9/3001 , G06F12/0893 , G06F13/36 , G06F13/405 , G06F15/7817 , H04W28/08 , H04W52/0216 , H04W88/02 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D70/142 , Y02D70/26
摘要： A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.
摘要翻译：一种单片微型计算机，包括：具有中央处理单元和与其连接的高速缓冲存储器的第一总线; 具有动态存储器访问控制电路和与其连接的外部总线接口的第二总线; 中断控制器，用于选择性地连接第一总线和第二总线; 第三总线，其具有与其连接的外围模块并且具有比第一总线和第二总线的总线周期更低的总线周期; 以及用于实现第二总线和第三总线之间的数据传输和同步的总线状态控制器。单片机具有三条分开的内部总线，以降低信号传输路径上的负载容量，从而可以高速完成信号传输。而且，不需要操作速度的外围模块被隔离，从而可以降低功耗。

23. 发明授权

EP0305106B1 Bus error processing system 失效
公开(公告)号：EP0305106B1
公开(公告)日：1995-03-15
申请号：EP88307609.3
申请日：1988-08-17
申请人： HITACHI, LTD.
发明人： Maruyama, Takashi , Kaneko, Susumu , Kurakazu, Keiichi , Kida, Hiroyuki
IPC分类号： G06F11/00 , G06F13/28
CPC分类号： G06F11/0745 , G06F11/0793
摘要： A bus error ascribable to a bus master module (2) other than a central processing unit (CPU) (1) is set as a specified factor for an exception process. When the exception process is requested, the CPU (1) executes a corresponding service program for the exception process without executing a process for altering and setting mask bits, which would be executed for a normal interrupt request. Thus, the exception process request specific to the bus error is not undesirably refused by interrupt requests etc., being accepted before the bus error. Furthermore there is a reduction in the time which is expended before the start of the run of a service program corresponding to the bus error, with the result that the reliability of the process for the bus error attributed to the predetermined bus master module (2) other than the CPU (1) is enhanced.

24. 发明授权

EP0241909B1 Information processing apparatus 失效
标题翻译：数据处理装置。
公开(公告)号：EP0241909B1
公开(公告)日：1994-02-23
申请号：EP87105507.5
申请日：1987-04-14
申请人： HITACHI, LTD.
发明人： Watanabe, Tan , Kurakazu, Keiichi , Kashiwagi, Yugo , Toyama, Keisuke , Nojiri, Tohru
IPC分类号： G06F9/46 , G06F9/30
CPC分类号： G06F9/30138 , G06F9/30105 , G06F9/30127 , G06F9/30134 , G06F9/342 , G06F9/4484 , G06F9/461 , G06F9/462
摘要： In a computer system equipped with a large number of registers (R, Q) which have an access time much shorter than that of a main memory, a register designating address part (12) in which the assignment (13) of an area register (21) having a register address (i) of a register area as its value and the assignment (14) of a register displacement value (d) expressing a relative register address within the register area are combined is provided in each instruction so that, even when physical registers are increased, save and restore of registers attendant upon task switches, etc. may be lessened to attain a raised speed of program run processing. Besides, an address part (103) for designating the main memory is provided in the same instruction.

25. 发明公开

EP0902361A2 Single-chip CPU and microcomputer 失效
标题翻译：单片机
公开(公告)号：EP0902361A2
公开(公告)日：1999-03-17
申请号：EP98120015.7
申请日：1992-06-22
申请人： Hitachi, Ltd. , HITACHI ULSI ENGINEERING CORPORATION , HITACHI MICROCOMPUTER SYSTEM LTD.
发明人： Kawasaki, Shumpei , Sakakibara, Eiji , Fukada, Kaoru , Yamazaki, Takanaga , Akao, Yasushi , Baba, Shiro , Kihara, Toshimasa , Kurakazu, Keiichi , Tsukamoto, Takashi , Masumura, Shigeki , Tawara, Yasuhiro , Kashiwagi, Yugo , Fujita, Shuya , Ishida, Katsuhiko , Sawa, Noriko , Asano, Yoichi , Chaki, Hideaki , Sugawara, Tadahiko , Kainaga, Masahiro , Noguchi, Kouki B-11, Hitachitennouueshataku , Watabe, Mitsuru
IPC分类号： G06F9/38 , G06F15/78
CPC分类号： G06F7/535 , G06F9/30 , G06F9/3001 , G06F9/30112 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30163 , G06F9/30167 , G06F9/30181 , G06F9/30189 , G06F9/322 , G06F9/324 , G06F9/3557 , G06F9/3802 , G06F9/3814 , G06F9/3836 , G06F9/3857 , G06F9/3859 , G06F9/3867 , G06F2207/5352
摘要： A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting an instruction format of a fixed length of 2 n bits which is smaller than the length of the maximum data word fed to instruction execution means. The control of the coded division is executed by noting the code bits.

26. 发明授权

EP0312194B1 Data processor having two modes of operation 失效
标题翻译：数据处理器具有两种操作模式。
公开(公告)号：EP0312194B1
公开(公告)日：1995-05-10
申请号：EP88307303.3
申请日：1988-08-08
申请人： HITACHI, LTD.
发明人： Kaneko, Susumu , Kurakazu, Keiichi
IPC分类号： G06F9/46 , G06F12/14
CPC分类号： G06F21/74 , G06F9/45533 , G06F12/1458

27. 发明公开

EP0525375A3 Microcomputer and divider circuit 失效
标题翻译：微型计算机和分路器电路
公开(公告)号：EP0525375A3
公开(公告)日：1993-04-21
申请号：EP92110517.7
申请日：1992-06-22
申请人： HITACHI, LTD. , HITACHI ULSI ENGINEERING CORPORATION , HITACHI MICROCOMPUTER SYSTEM LTD.
发明人： Kawasaki, Shumpei , Sakakibara, Eiji , Fukada, Kaoru , Yamazaki, Takanaga , Akao, Yasushi , Baba, Shiro , Kihara, Toshimasa , Kurakazu, Keiichi , Tsukamoto, Takashi , Masumura, Shigeki , Tawara, Yasuhiro , Kashiwagi, Yugo , Fujita, Shuya , Ishida, Katsuhiko , Sawa, Noriko , Asano, Yoichi , Chaki, Hideaki , Sugawara, Tadahiko , Kainaga, Masahiro , Noguchi, Kouki , Watabe, Mitsuru
IPC分类号： G06F9/38
CPC分类号： G06F7/535 , G06F9/30 , G06F9/3001 , G06F9/30112 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30163 , G06F9/30167 , G06F9/30181 , G06F9/30189 , G06F9/322 , G06F9/324 , G06F9/3557 , G06F9/3802 , G06F9/3814 , G06F9/3836 , G06F9/3857 , G06F9/3859 , G06F9/3867 , G06F2207/5352
摘要： RISC-type microprocessor has a fixed struction lenght of 2 n bits, whilst the data use size is 2 m bits,where m is greater than or equal to n.

28. 发明公开

EP0241909A3 Information processing apparatus 失效
标题翻译：信息处理设备
公开(公告)号：EP0241909A3
公开(公告)日：1990-03-28
申请号：EP87105507.5
申请日：1987-04-14
申请人： HITACHI, LTD.
发明人： Watanabe, Tan , Kurakazu, Keiichi , Kashiwagi, Yugo , Toyama, Keisuke , Nojiri, Tohru
IPC分类号： G06F9/46 , G06F9/30
CPC分类号： G06F9/30138 , G06F9/30105 , G06F9/30127 , G06F9/30134 , G06F9/342 , G06F9/4484 , G06F9/461 , G06F9/462
摘要： In a computer system equipped with a large number of registers (R, Q) which have an access time much shorter than that of a main memory, a register designating address part (12) in which the assignment (13) of an area register (21) having a register address (i) of a register area as its value and the assignment (14) of a register displacement value (d) expressing a relative register address within the register area are combined is provided in each instruction so that, even when physical registers are increased, save and restore of registers attendant upon task switches, etc. may be lessened to attain a raised speed of program run processing. Besides, an address part (103) for designating the main memory is provided in the same instruction.
摘要翻译：在配备有大量寄存器（R，Q）的计算机系统中，其访问时间比主存储器的访问时间短得多，寄存器指定地址部分（12），其中寄存器指定地址部分（12）在每个指令中提供具有作为其值的寄存器区域的寄存器地址（i）和表示寄存器区域内的相对寄存器地址的寄存器位移值（d）的分配（14）的指令（21）当物理寄存器增加时，伴随着任务切换等的寄存器的保存和恢复可能会减少，以达到程序运行处理的提高的速度。此外，用于指定主存储器的地址部分（103）被提供在相同的指令中。

29. 发明公开

EP0241909A2 Information processing apparatus 失效
标题翻译： Datenverarbeitungsvorrichtung。
公开(公告)号：EP0241909A2
公开(公告)日：1987-10-21
申请号：EP87105507.5
申请日：1987-04-14
申请人： HITACHI, LTD.
发明人： Watanabe, Tan , Kurakazu, Keiichi , Kashiwagi, Yugo , Toyama, Keisuke , Nojiri, Tohru
IPC分类号： G06F9/46 , G06F9/30
CPC分类号： G06F9/30138 , G06F9/30105 , G06F9/30127 , G06F9/30134 , G06F9/342 , G06F9/4484 , G06F9/461 , G06F9/462
摘要： In a computer system equipped with a large number of registers (R, Q) which have an access time much shorter than that of a main memory, a register designating address part (12) in which the assignment (13) of an area register (21) having a register address (i) of a register area as its value and the assignment (14) of a register displacement value (d) expressing a relative register address within the register area are combined is provided in each instruction so that, even when physical registers are increased, save and restore of registers attendant upon task switches, etc. may be lessened to attain a raised speed of program run processing.
Besides, an address part (103) for designating the main memory is provided in the same instruction.
摘要翻译：在具有大量比主存储器的访问时间短的访问时间的大量寄存器（R，Q）的计算机系统中，指定地址部分（12）的寄存器指定地址部分（12），其中区域寄存器具有作为其值的寄存器区域的寄存器地址（i）和表示寄存器区域内的相对寄存器地址的寄存器位移值（d）的分配（14）被组合在每个指令中，使得甚至当物理寄存器增加时，可以减少对任务切换等等的登记的保存和恢复，以达到程序运行处理的提高速度。此外，在相同的指令中提供了用于指定主存储器的地址部分（103）。

30. 发明公开

EP0220684A2 Data processing system 失效
公开(公告)号：EP0220684A2
公开(公告)日：1987-05-06
申请号：EP86114724.7
申请日：1986-10-23
申请人： HITACHI, LTD.
发明人： Kurakazu, Keiichi , Baba, Shiro
IPC分类号： G06F9/34 , G06F9/30
CPC分类号： G06F9/30192
摘要： An instruction having two operands including a field (Sz2) specifying the bit length of a source operand and a field (Sz1) specifying the bit length of data to be operated by the execution unit. Based on size information stored in these fields (Sz1, Sz2), the operand bit length is modified, which unnecessitates the modification of the bit length of an operand by use of a macro instruction Consequently, the program execution speed can be improved.

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