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11. 发明公开

EP0032195A1 Schottky barrier diode and method of making it 失效
标题翻译：肖特基Sperrschichtdiode和Verfahren zu deren Herstellung。
公开(公告)号：EP0032195A1
公开(公告)日：1981-07-22
申请号：EP80107627.4
申请日：1980-12-04
申请人： International Business Machines Corporation
发明人： Feth, George Clarence , Wiedmann, Siegfried Kurt
IPC分类号： H01L29/48 , H01L21/316 , H01L21/28
CPC分类号： H01L29/66848 , H01L21/74 , H01L29/47 , H01L29/872 , Y10S148/131 , Y10S148/139 , Y10S148/141
摘要： The anode (40) and cathode contact (32) of the diode are contiguously located on a semiconductor surface and separated by an insulating coating (36) on cathode contact (32). Preferably the anode (40) consists of two regions (40) separated by coated cathode contact (32) and laterally surrounded by recessed oxide area (16).
The method of making includes the steps of forming cathode contact (32) of a layer of conductive material and applying insulative coating (36) onto it where after this step at least one area of the semiconductor surface adjoining coated cathode contact (32) is exposed, of blanket depositing a metal layer and causing the reaction of the metal with the semiconductor material to produce anode (40) that is self-aligned with respect to cathode contact (32).
The diode may be incorporated into merged transistor logic devices in large scale integration applications.
摘要翻译：二极管的阳极（40）和阴极（32）连接地位于半导体表面上并由阴极接触件（32）上的绝缘涂层（36）分开。优选地，阳极（40）由被涂覆的阴极接触（32）分开并被凹陷的氧化物区域（16）侧向包围的两个区域（40）组成。 ...制造方法包括以下步骤：形成导电材料层的阴极接触（32）并在其上施加绝缘涂层（36），其中在该步骤之后，半导体表面的至少一个区域邻接涂覆的阴极接触（32）暴露，覆盖沉积金属层并使金属与半导体材料的反应产生相对于阴极接触（32）自对准的阳极（40）。在大规模集成应用中，二极管可并入到合并的晶体管逻辑器件中。

12. 发明公开

EP0005185A1 Verfahren zum gleichzeitigen Herstellen von Schottky-Sperrschichtdioden und ohmschen Kontakten nach dotierten Halbleiterzonen 失效
标题翻译：用于同时生产肖特基势垒二极管的欧姆接触的方法，以及掺杂半导体区。
公开(公告)号：EP0005185A1
公开(公告)日：1979-11-14
申请号：EP79101076.2
申请日：1979-04-09
申请人： International Business Machines Corporation
发明人： Friedman, Jules David , Saraf, Lumdas Hiraman
IPC分类号： H01L21/60 , H01L23/48 , H01L21/285 , H01L29/48
CPC分类号： H01L21/28537 , H01L21/28518 , H01L21/76886 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： Verfahren zum selektiven Herstellen von Kontakten auf Halbleiterzonen.
Eine Gruppe von Kontaktbohrungen wird während der Metallisierung einer anderen Gruppe von freiliegenden Kontaktbohrungen durch eine Sperrschicht (24) geschützt, wodurch der saubere Zustand und die Zuverlässigkeit der Kontakte verbessert werden. Die Sperrschicht wird anschließend entfernt und in beiden Gruppen von Kontaktbohrungen wird eine zweite Metallisierungsschicht niedergeschlagen. In der bevorzugten Ausführungsform wird eine übliche Diffusionsmaske für die Festlegung aller Kontaktbereiche benutzt, und zur Abschirmung wird in jeder der Kontaktbohrungen thermisch eine Oxidschicht (24) aufgewachsen. Eine sperrende Photolackmaske wird anschließend aufgebracht und mit einem Muster versehen, das das Oxid in denjenigen Kontaktbohrungen freilegt, in denen die erste Gruppe von Kontakten gebildet werden soll. Die abschirmende Oxidschicht wird dann entfernt und eine erste Metallisierungsschicht, die vorzugsweise aus Platinsilicid besteht, wird dann gebildet. Die abschirmende Oxidschicht (24) wird anschließend von den geschützten Kontaktbereichen entfernt, und eine zweite Metallisierungsschicht, die beispielsweise aus Chrom, Aluminium oder anderen Metallen oder deren Legierungen bestehen kann, wird daraufhin in allen Kontaktbohrungen niedergeschlagen, so daß insgesamt in der zweiten Gruppe von Kontaktbohrungen eine Metallisierungsschicht und in der ersten Gruppe von Kontaktbohrungen zwei Metallisierungsschichten übereinander gebildet sind.
摘要翻译：一种用于有选择地产生接触，以半导体区的过程。 A组的接触孔通过的阻挡层（24），由此清洁的状态和触点的可靠性可以提高金属化时产生保护的另一基团暴露的接触孔。然后在阻挡层被除去，在接触孔两组，一第二金属化层被沉积。在优选实施例中，对于所有Kondtaktbereiche的定义的常规扩散掩模用于屏蔽和在每个接触孔的热氧化物层（24）的生长。然后将阻断光刻胶掩模被沉积并设置有暴露所述氧化物在这些接触孔，其中，第一组是联系人的将要形成的图案。然后屏蔽氧化物层被除去，然后，形成第一金属化层，其优选由铂硅化物构成。屏蔽氧化物层（24）然后，从接触的保护区，和一个第二金属化层，它可以由例如铬，铝或其它金属或合金，然后它们被沉积在所有的接触孔的除去，从而在第二组接触孔在总金属化层和所述第一组Kontakbohrungen两个金属化层的形成在一个在另一个的上面。

13. 发明公开

EP0005163A1 Verfahren zum Herstellen eines PtSi-Schottky-Sperrschichtkontakts 失效
标题翻译： Verfahren zum Herstellen eines PtSi-Schottky-Sperrschichtkontakts。
公开(公告)号：EP0005163A1
公开(公告)日：1979-11-14
申请号：EP79100947.5
申请日：1979-03-29
申请人： International Business Machines Corporation
发明人： Gniewek, John James , Reith, Timothy Martin , Sullivan, Michael James , White, James Francis
IPC分类号： H01L21/263 , H01L29/48 , C23C15/00
CPC分类号： H01L21/32131 , H01L21/28537
摘要： Die Anmeldung behandelt ein Verfahren zum Herstellen eines PtSi-Schottky-Sperrschichtkontakts. Nach Herstellung eines Kontaktes aus Platinsilicid (5) in einer Öffnung (3) einer auf der Oberfläche eines Siliciumsubstrats (1) angebrachten Isolierschicht (2) für die Bildung einer Schottky-Sperrschichtdiode in einem Silicium-Halbleitersubstrat wird das noch verbleibende, nicht umgesetzte Platin (4) durch Zerstäubungsätzen in einer Edelgasatmosphäre in Verbindung mit Sauerstoff oder Stickstoff abgeätzt.
摘要翻译： Pt在PtSi上的溅射蚀刻速率的差异通过在稀有气体环境中溅射蚀刻Pt而增加。 > = 1 vol。％O2或N2，pref。 Ar contg 10卷％O2。该方法被并入Si衬底中形成肖特基势垒电极，特别是通过（a）在Si衬底中形成有源电路元件，（b）用绝缘层涂覆表面，该绝缘层具有暴露Si的至少一个开口（ c）在绝缘体和开口中沉积铂层，（d）烧结，在开口中形成PtSi，和（e）如上所述溅射蚀刻未组合的Pt。蚀刻速率差的增加导致Pt稀化比使用纯Ar更低。污染少，没有Cl和S污染。

14. 发明公开

EP0579286A3 Method of fabricating a semiconductor device with Schottky barrier 失效
标题翻译：用肖特基阻挡层制造半导体器件的方法
公开(公告)号：EP0579286A3
公开(公告)日：1994-09-07
申请号：EP93115576.6
申请日：1989-10-31
申请人： SANKEN ELECTRIC CO., LTD.
发明人： Ohtsuka,Koji , Goto, Hirokazu
IPC分类号： H01L29/91 , H01L29/40 , H01L29/06 , H01L29/48 , H01L21/329
CPC分类号： H01L29/66143 , H01L29/475 , H01L29/872 , Y10S148/139 , Y10S148/14 , Y10S438/934
摘要： A semiconductor device such as a Schottky-barrier rectifier diode is disclosed which has a barrier electrode formed on a semiconductor substrate of gallium arsenide or the like. Formed around the barrier electrode is an annular resistive layer, typically of titanium oxide, creating a Schottky barrier at its interface with the semiconductor substrate. The resistive layer has a sheet resistance of more than 10 kilohms per square. In order to prevent preliminary breakdowns from taking place at the peripheral part of the resistive layer before final breakdown of the device, the sheet resistance of the resistive layer is made higher as it extends away from the barrier electrode. For the ease of manufacture, the resistive layer can be divided into two or more annular regions of distinctly different sheet resistances.
摘要翻译：公开了一种诸如肖特基势垒整流二极管的半导体器件，其具有形成在砷化镓等的半导体衬底上的势垒电极。形成在阻挡电极周围的环状电阻层通常为氧化钛，在其与半导体衬底的界面处产生肖特基势垒。电阻层具有大于10千欧每平方的薄层电阻。为了防止在器件的最终击穿之前在电阻层的周边部分发生初步破坏，电阻层的薄层电阻随着远离阻挡电极而越高。为了易于制造，电阻层可以分成两个或更多个明显不同的薄层电阻的环形区域。

15. 发明公开

EP0406373A4 TAPE AUTOMATED BONDED LEAD PACKAGE AND REUSABLE TRANSPORT TAPE FOR USE THEREWITH 失效
标题翻译：胶带自动捆绑引线包和可重复使用的运输带
公开(公告)号：EP0406373A4
公开(公告)日：1992-04-29
申请号：EP90900714
申请日：1989-12-07
申请人： TRIBOTECH
发明人： CAIN, EARL, S.
IPC分类号： H01L21/60 , H01L21/68 , H01L23/495 , H01L23/498 , H01L23/48 , H01L29/48 , H01L29/52 , H01L29/60
CPC分类号： H01L21/6835 , H01L23/49572 , H01L23/4985 , H01L24/50 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/14
摘要： A lead pack which includes a rectangular frame (18, 28) of polymer insulating material and a plurality of leads (34) imbedded in said frame and extending inwardly and outwardly therefrom for attachment to an associated integrated circuit and for attachment of the leaded integrated circuit to an associated printed wiring board or like circuit. The insulating frame serves as a dam or sealing means in an encapsulating process. An additional frame (29) stabilizes and positions. The outwardly extending ends of the leads (34). A reusable transport and test tape (12) which includes a plurality of leads (62) adapted to receive and connect to the leads (34) of the lead pack and the position the lead pack for reception of an integrated circuit for bonding of lead pack leads to the contact pads of the integrated circuit and to move the lead pack and integrated circuit into succeeding processing stations where the circuit is packaged and tested, and then excised.

16. 发明公开

EP0383193A2 Microwave integrated circuit 失效
标题翻译：微波集成电路
公开(公告)号：EP0383193A2
公开(公告)日：1990-08-22
申请号：EP90102466.1
申请日：1990-02-08
申请人： SUMITOMO ELECTRIC INDUSTRIES, LTD.
发明人： Shiga, Nobuo, c/o Yokohama Works
IPC分类号： H01P3/08 , H01L29/48 , H01L23/52
CPC分类号： H01P3/08
摘要： In this invention, a distributed constant line (12) of a microwave IC is formed of a Schottky metal, and a semiconductor conductive layer (15,16) contacting the distributed constant line (12) at least at one position and an ohmic contact electrode (13,14) contacting the semiconductor conductive layer (15,16) are arranged. According to this invention, characteristics of ICs can be optimized against a variation in elements combined with a circuit comprising the distributed constant line after the manufacture of ICs.
摘要翻译：在本发明中，微波IC的分布常数线路（12）由肖特基金属形成，并且半导体导电层（15,16）至少在一个位置与分布常数线路（12）接触，欧姆接触电极（13,14）与半导体导电层（15,16）接触。根据本发明，IC的特性可以针对在制造IC之后与包括分布常数线路的电路组合的元件的变化而被优化。

17. 发明公开

EP0372428A1 Semiconductor device having intermediate layer for pinching off conductive path during reverse bias application 失效
标题翻译：一种半导体装置，包括反向偏压期间的中间层，以电流路径的收缩。
公开(公告)号：EP0372428A1
公开(公告)日：1990-06-13
申请号：EP89122233.3
申请日：1989-12-01
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Sugita, Naomasa c/o Intellectual Prop. Div.
IPC分类号： H01L29/91 , H01L29/48
CPC分类号： H01L29/872
摘要： A semiconductor device comprising a semiconductor substrate (30) having two major surfaces, cathode electorde film (32) formed on the first major surface of the substrate (30), and anode electrode film (34) made of a Schottky-barrier metal such as titanium (Ti, Mo, V), formed on the second major surface of the substrate (30). The substrate (30) is formed of an N⁺-type layer (36) formed on the cathode electrode film (32), an N⁻-type layer (38) formed on the N⁺-type layer (36), an N⁻⁻-type layer (40) formed on the N⁻-type layer (38) and having an impurity concentration lower than that of the N⁻-type layer (38), and an N⁻-type layer (42) interposed between the N⁻⁻-type layer (40) and the anode electrode film (34). The device further comprises a plurality of P⁺-type areas (46) formed in the second major surface of the substrate (30), contacting the anode electrode film (34) and extending through the N⁻-type layer (42) and the N⁻⁻-type layer (40) into the N⁻-type layer (38). When a forward bias is applied to the device, a current flows from the anode electrode film (34), passes through the N⁻-, N⁻⁻-, N⁻- and the N⁺-type layers (42, 40, 38, 36), and flows out of the cathode electrode film (32). When a reverse bias is applied to the device, the depletion layer formed around the junction between each P⁺-type area (46) and the N⁻⁻-type layer (40) extends, joining with the similar depletion layers, thereby pinching off the path of the current. As a result, the flow of a reverse leakage current is suppressed.
摘要翻译：具有两个主表面，阴极electorde电影（32）一种半导体装置，包括：半导体衬底（30）形成在由一肖特基势垒金属的底物（30）和阳极电极的电影（34）的第一主表面：如钛（钛，钼，V），形成在所述基片（30）的第二主表面。（32）将N形成在阴极电极电影型层（36）< - - > - 型层（38）形成在n <+> - 基板（30）上形成n <+>的类型层（36）将N < - > < - > - 型层（40）形成在n < - > - 型层（38），并在杂质浓度比n的降低具有< - > - 型层（38 ），以及N < - > - < - > < - > - 型层（40）和所述阳极电极的电影（34）的N个之间（型层42）。该装置还包括P <+>的多元化 - 在接触阳极电极电影（34）在基板（30）的第二主表面上形成型区域（46）和通过所述N个扩展< - > - 型层（ 42）和N < - > < - > - 型层（40）向N < - > - 型层（38）。当正向偏压施加到该装置中，电流从阳极电极电影（34）流动，通过N个< - > - ，N < - > < - > - ，N < - > - 和N <+ >型层（42，40，38，36），并流出阴极电极电影（32）的。当反向偏压被施加到该装置，耗尽层周围形成每个P <+>之间的结 - 型区域（46）和N < - > < - > - 型层（40）延伸，与同类接合耗尽层，由此夹断的电流的路径。其结果是，反向漏电流的流动被抑制。

18. 发明授权

EP0031366B1 VERTICAL FIELD EFFECT TRANSISTOR 失效
标题翻译：垂直场效应晶体管
公开(公告)号：EP0031366B1
公开(公告)日：1985-10-02
申请号：EP80901438.4
申请日：1980-06-16
申请人： Western Electric Company, Incorporated
发明人： CHO, Alfred Yi
IPC分类号： H01L29/48 , H01L29/161 , H01L29/80 , H01L29/06 , H01L29/04
CPC分类号： H01L29/7828 , H01L29/8122
摘要： A vertical field effect transistor (10) includes a relatively wide bandgap, lowly doped active layer (18) epitaxially grown on, and substantially lattice matched to, an underlying semiconductor body portion (13). A mesa (20) of lower bandgap material is epitaxially grown on and substantially lattice matched to the active layer. A source electrode (22) is formed on a bottom major surface (34) of the semiconductor body portion, a drain electrode (24) is formed on the top of the mesa, and a pair of gate electrode stripes (26) are formed on the active layer adjacent both sides of the mesa. When voltage (VG), negative with respect to the drain, is applied to the gate electrodes, the depletion regions (28) there under extend laterally in the active layer until they intersect, thereby pinching off the flow of current in the channel extending from the drain and source electrodes. Also described is an embodiment in which spaced-apart, high impedance zones (30) underlie the active layer and the mesas, and the spaces between zones underlie the gate stripes.

19. 发明公开

EP0034166A4 SEMICONDUCTOR EMBEDDED LAYER TECHNOLOGY. 失效
标题翻译：嵌入式技术用于半导体层。
公开(公告)号：EP0034166A4
公开(公告)日：1984-04-27
申请号：EP80901688
申请日：1981-02-24
申请人： MASSACHUSETTS INST TECHNOLOGY
发明人： BOZLER CARL O , ALLEY GARY D , LINDLEY WILLIAM T , MURPHY R ALLEN
IPC分类号： H01L29/73 , H01L21/20 , H01L21/331 , H01L21/335 , H01L21/74 , H01L23/482 , H01L23/52 , H01L23/535 , H01L29/10 , H01L29/772 , H01L29/80 , H01L29/92 , H01L29/48 , H01L23/48 , H01L27/02 , H01L29/06
CPC分类号： H01L29/66424 , H01L21/02395 , H01L21/02532 , H01L21/02546 , H01L21/02639 , H01L21/743 , H01L23/4824 , H01L23/52 , H01L23/535 , H01L28/40 , H01L29/7722 , H01L2924/0002 , H01L2924/3011 , Y10S148/164 , H01L2924/00
摘要： A permeable base transistor (30) including a metal base layer (34) embedded in a semiconductor crystal (32) to separate collector (38) and emitter (40) regions and form a Schottky barrier with each. The metal base layer has at least one opening (37) through which the crystal semiconductor (32) joins the collector (38) and emitter (40) regions. Ohmic contacts (42, 44) are made to the emitter (40) and collector (38) regions. The width of all openings (37) in the base layer (34) is of the order of the zero bias depletion width corresponding to the carrier concentration in the opening. The thickness of the metal layer (34) is in the order of 10% if this zero bias depletion width. As a result, a potential barrier in each opening limits current flow over the lower portion of the bias range. With increasing forward base bias the potential in the openings, which is lower than along the metal of the base layer (34), is lowered sufficiently to permit substantial increase in the barrier limited current flow from the collector (38) to emitter (40). A method of fabricating this transistor as well as methods for forming integrated circuit structures are also disclosed. Metal and other layers may be selectively embedded in semiconductor crystal. Embedded metal layers may serve as interconnections between devices. Devices may be in a stacked configuration.

20. 发明公开

EP0031366A4 VERTICAL FIELD EFFECT TRANSISTOR. 失效
标题翻译：纵型场效应晶体管。
公开(公告)号：EP0031366A4
公开(公告)日：1983-04-06
申请号：EP80901438
申请日：1981-01-26
申请人： WESTERN ELECTRIC CO
发明人： CHO ALFRED YI
IPC分类号： H01L29/06 , H01L29/12 , H01L29/205 , H01L29/78 , H01L29/80 , H01L29/812 , H01L29/48 , H01L29/04 , H01L29/161
CPC分类号： H01L29/7828 , H01L29/8122

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