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11. 发明公开

EP0060108A3 ADDRESS BUFFER 失效
标题翻译：地址缓冲区
公开(公告)号：EP0060108A3
公开(公告)日：1985-09-18
申请号：EP82301141
申请日：1982-03-05
申请人： FUJITSU LIMITED
发明人： TAKEMAE, YOSHIHIRO , NOZAKI, SHIGEKI , KABASHIMA, KATSUHIKO , ENOMOTO, SEIJI , MEZAWA, TSUTOMU
IPC分类号： G11C11/403 , G11C11/406 , G11C11/408 , G11C11/24
CPC分类号： G11C11/4082 , G11C11/406

12. 发明公开

EP4326024A2 FIN FIELD-EFFECT TRANSISTOR (FINFET) BASED SEMICONDUCTOR MEMORY ARRAY HAVING MEMORY CELLS WITH A REDUCED SURFACE AREA 审中-实审
公开(公告)号：EP4326024A2
公开(公告)日：2024-02-21
申请号：EP23191282.5
申请日：2023-08-14
申请人： ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)
发明人： Giterman, Robert , Burg, Andreas , Yigit, Halil Andac
IPC分类号： H10B12/00 , G11C11/403 , H01L27/02
摘要： A fin field-effect transistor (FinFET) based semiconductor memory array having a plurality of memory cells, each memory cell including a write transistor having a write wordline gate over a first fin connected to a write wordline gate contact, a write bitline contact in connection with the first fin, and a storage node contact in connection with the first fin, and a read transistor having a storage node gate over a second fin, the storage node gate connected to a storage node gate contact, the storage node gate contact connected to the storage node contact, a read wordline contact in connection with the second fin, and a read bitline contact in connection with the second fin, wherein the write wordline gate and the storage node gate are arranged in series to each other along an extension axis that coincides with an longitudinal axis of the write wordline gate and a longitudinal axis of the storage node gate.

13. 发明授权

EP2534679B1 SEMICONDUCTOR DEVICE AND DRIVING METHOD OF THE SAME 有权转让
公开(公告)号：EP2534679B1
公开(公告)日：2021-06-16
申请号：EP11742135.4
申请日：2011-01-25
发明人： INOUE, Hiroki , KATO, Kiyoshi , MATSUZAKI, Takanori , NAGATSUKA, Shuhei
IPC分类号： G11C11/401 , H01L27/12 , G11C11/24 , G11C11/403 , H01L29/792 , H01L29/788 , H01L27/115 , H01L27/108 , H01L27/105 , H01L27/10 , G11C11/405 , H01L21/8242

14. 发明公开

EP2466587A2 Semiconductor storage device 审中-公开
标题翻译： Halbleiterspeicherelement
公开(公告)号：EP2466587A2
公开(公告)日：2012-06-20
申请号：EP11194028.4
申请日：2011-12-16
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Nagatsuka, Shuhei , Takahashi, Yasuyuki
IPC分类号： G11C16/02 , G11C11/403 , G11C11/404
摘要： A semiconductor storage device with a novel structure, which can retain stored data even when power is not supplied (i.e., is non-volatile) and has no limitation on the number of write cycles. The semiconductor storage device includes a memory cell array in which a plurality of memory cells are arranged in matrix, a decoder configured to select a memory cell to operate among the plurality of memory cells in accordance with a control signal, and a control circuit configured to select whether to output the control signal to the decoder. In each of the plurality of memory cells, data is held by turning off a selection transistor whose channel region is formed with an oxide semiconductor.
摘要翻译：一种具有新颖结构的半导体存储装置，即使在未提供电力（即非易失性）的情况下也能够保持存储的数据，并且对写入周期的数量没有限制。所述半导体存储装置具有存储单元阵列，其中多个存储单元以矩阵形式排列;解码器，被配置为根据控制信号选择存储单元在所述多个存储单元之间进行操作;以及控制电路，选择是否将控制信号输出到解码器。在多个存储单元的每一个中，通过关闭其沟道区域形成氧化物半导体的选择晶体管来保持数据。

15. 发明公开

EP2287849A3 Semiconductor memory having dual port cell supporting hidden refresh 审中-公开
标题翻译：支持隐藏刷新的半双工单元半导体存储器
公开(公告)号：EP2287849A3
公开(公告)日：2011-03-09
申请号：EP10178106.0
申请日：2001-08-29
申请人： Micron Technology, Inc.
发明人： Keeth, Brent , Dennison, Chuck
IPC分类号： G11C11/406 , G11C11/405 , G11C8/16 , G11C11/403
CPC分类号： G11C11/403 , G11C11/406 , Y10S257/907
摘要： The present invention is directed to an integrated circuit device having a memory cell for storing a data and refresh circuitry for refreshing that data in the memory cell. In one illustrative embodiment, the device comprises a memory cell having a storage element, a read/write access device, and a refresh access device. A read/write digit line is coupled to the read/write access 0 device, and a refresh digit line is coupled to the refresh access device. A sense amplifier is coupled to the read/write digit line, and input/output circuitry is coupled to the read/write digit line. A refresh sense amplifier is coupled to the refresh digit line. The memory cell is constructed in such a way as to provide a large charge storage capacity in a relatively small, compact area.
摘要翻译：本发明涉及具有用于存储数据的存储器单元和用于刷新存储器单元中的数据的刷新电路的集成电路器件。在一个说明性实施例中，该设备包括具有存储元件，读取/写入访问设备和刷新访问设备的存储器单元。读/写数字线连接到读/写访问设备，并且刷新数位线连接到刷新访问设备。读出放大器耦合到读/写数字线，输入/输出电路耦合到读/写数字线。刷新感测放大器耦合到刷新数字线。存储器单元被构造为在相对小的紧凑区域中提供大的电荷存储容量。

16. 发明公开

EP2013881A1 DYNAMIC RANDOM ACCESS MEMORY DEVICE AND METHOD FOR SELF- REFRESHING MEMORY CELLS WITH TEMPERATURE COMPENSATED SELF- REFRESH 审中-公开
标题翻译：动态随机存取存储器设备和方法补偿与自刷新温度自刷新存储单元
公开(公告)号：EP2013881A1
公开(公告)日：2009-01-14
申请号：EP07719461.1
申请日：2007-03-30
申请人： Mosaid Technologies Incorporated
发明人： PYEON, Hong Beom
IPC分类号： G11C11/406 , G11C11/403
CPC分类号： G11C11/406 , G11C7/04 , G11C11/40611 , G11C11/40615 , G11C11/40626 , G11C2211/4061
摘要： A dynamic random access memory (DRAM) device has an array of DRAM cells of rows by columns. Each DRAM cell of the array is coupled with a wordline of a corresponding row and a bitline of a corresponding column. An entry into and an exit from the self-refresh mode are detected by a mode detector and a self-refresh mode signal is provided. An oscillation circuit generates in response to the self-refresh mode signal generates a basic time period. A first frequency divider/time period multiplier changes the basic time period in accordance with a process variation factor relating to the DRAM device. A second frequency divider/time period multiplier further changes the changed time period in accordance with a temperature change factor relating to the DRAM device. In the self-refresh mode, data stored in the DRAM cells is refreshed. In accordance with the two factors, the DRAM devices perform and achieve reliable self- refresh for variable DRAM cell retention time.

17. 发明公开

EP1328942A4 METHOD AND SYSTEM FOR HIDING REFRESHES IN A DYNAMIC RANDOM ACCESS MEMORY 有权
标题翻译：隐藏的方法和系统刷新动态随机存取存储器
公开(公告)号：EP1328942A4
公开(公告)日：2008-01-02
申请号：EP01962382
申请日：2001-08-14
申请人： MICRON TECHNOLOGY INC
发明人： KEETH BRENT , SHIRLEY BRIAN M , RYAN KEVIN J , DENNISON CHARLES H
IPC分类号： G11C11/403 , G11C7/10 , G11C11/406 , G11C7/00
CPC分类号： G11C11/40618 , G11C7/1042 , G11C11/406
摘要： A method and system for refreshing a dynamic random access memory ('DRAM')(40) includes a pair of memory arrays for each of a plurality of banks. The DRAM (40) includes the usual addressing and data path circuitry, as well as a refresh controller (70) that refreshes the arrays in a manner that hides refreshes sufficiently that the DRAM (40) can be used in place of an SRAM as a cache memory (236). Since only one of the arrays in each bank is refreshed at a time, the refresh controller (70) is able to allow data to be written to the array that is not being refreshed. The refresh controller (70) then causes the write data to be temporarily stored so that it can be written to the array of the refresh of the array has been completed. If neither array is being refreshed, the data are written to both arrays. Data are read from the arrays by first checking to determine if any of the arrays is being refreshed. If so, data are read from the array that is not being refreshed.

18. 发明公开

EP1858025A1 Semiconductor memory operated by internal and external refresh 有权
标题翻译： Halbleiterspeicher mit internem和externem刷新
公开(公告)号：EP1858025A1
公开(公告)日：2007-11-21
申请号：EP07108189.7
申请日：2007-05-14
申请人： FUJITSU LIMITED
发明人： Kawakubo, Tomohiro
IPC分类号： G11C11/406 , G11C11/402 , G11C11/403
CPC分类号： G11C11/406 , G11C11/40611 , G11C11/40615 , G11C11/40622 , G11C2211/4061
摘要： A core control circuit outputs operation control signals to a memory core in order to perform refresh operations in response to an internal refresh request (SREF) from a refresh request generating circuit and an external refresh request (AREF). The core control circuit sets the number of memory cells each subjected to the refresh operation in response to the external refresh request larger than the number of memory cells each subjected to the refresh operations in response to the internal refresh request. By relatively increasing the number of memory cells each subjected to the refresh operation in response to one external refresh request, the number of external refresh requests required to refresh all memory cells can be reduced. Accordingly, the frequency with which the external refresh request is supplied to the semiconductor memory can be lowered, which can improve access efficiency.
摘要翻译：核心控制电路将操作控制信号输出到存储器核心，以便响应来自刷新请求产生电路和外部刷新请求（AREF）的内部刷新请求（SREF）执行刷新操作。核心控制电路响应于大于响应于内部刷新请求的刷新操作的每个存储单元的数量的外部刷新请求，设置每个经历刷新操作的存储器单元的数量。通过相对增加响应于一个外部刷新请求而进行刷新操作的存储器单元的数量，可以减少刷新所有存储器单元所需的外部刷新请求数。因此，可以降低向半导体存储器提供外部刷新请求的频率，这可以提高访问效率。

19. 发明公开

EP1406267A4 SEMICONDUCTOR MEMORY 审中-公开
标题翻译： HALBLEITERSPEICHER
公开(公告)号：EP1406267A4
公开(公告)日：2007-10-31
申请号：EP02728132
申请日：2002-05-23
申请人： NEC ELECTRONICS CORP
发明人： TAKAHASHI HIROYUKI , INABA HIDEO , NAKAGAWA ATSUSHI
IPC分类号： G11C11/403 , G11C7/10 , G11C11/401 , G11C11/406 , G11C11/409 , G11C11/4096 , G11C11/40
CPC分类号： G11C11/40615 , G11C7/1012 , G11C7/1051 , G11C11/406 , G11C11/4096
摘要： An asynchronous semiconductor memory is composed of so-called pseudo-SRAMs. The restriction on the skew of an address is relaxed, and the read rate is improved. A data latch circuit (110) holds data read out of memory cells in a memory cell array (106) specified by a row address included in an address ADDU in a read mode. A multiplexer (111) sends to the outside sequentially the data held in the data latch circuit (110) asynchronously according to column addresses A0, A1 when the column addresses A0, A1 included in the address change.
摘要翻译：异步半导体存储器由所谓的伪SRAM组成。对地址歪斜的限制被放宽，并且读取率得到改善。数据锁存电路（110）在读取模式下保持从由包含在地址ADDU中的行地址指定的存储单元阵列（106）中的存储单元读出的数据。当包含在地址中的列地址A0，A1改变时，多路复用器（111）根据列地址A0，A1异步地将保存在数据锁存电路（110）中的数据异步地发送到外部。

20. 发明公开

EP1770711A1 SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：半导体存储设备
公开(公告)号：EP1770711A1
公开(公告)日：2007-04-04
申请号：EP04747675.9
申请日：2004-07-16
申请人： Fujitsu Ltd.
发明人： TOMITA, Hiroyoshi, Fujitsu Limited , YAMAGUCHI, Shusaku, Fujitsu Limited 1-1
IPC分类号： G11C11/403
CPC分类号： G11C11/406 , G11C7/1045 , G11C11/40603 , G11C11/40615 , G11C11/4076
摘要： A multipurpose terminal receives an address signal and a data signal. An address valid terminal receives an address valid signal indicating that a signal supplied to the multipurpose terminal is the address signal. An arbiter determines which of an external access request and an internal refresh request is given priority. The arbiter disables reception of the internal fresh request in response to a fact that both a chip enable signal and the address valid signal reach a valid level (an external access request). The arbiter enables the reception of the internal refresh request in response to completion of a read operation or a write operation. As a result, in a semiconductor memory device including the multipurpose terminal which receives the address signal and the data signal, contention between the read operation and the write operation, and a refresh operation which responds to the internal refresh request is prevented, which prevents a malfunction.
摘要翻译：多用途终端接收地址信号和数据信号。地址有效终端接收指示提供给多用途终端的信号是地址信号的地址有效信号。仲裁器确定外部访问请求和内部刷新请求中的哪一个被赋予优先级。响应于芯片使能信号和地址有效信号两者达到有效电平（外部访问请求）的事实，仲裁器禁止接收内部新鲜请求。仲裁器响应于完成读取操作或写入操作而启用内部刷新请求的接收。结果，在包括接收地址信号和数据信号的多用途端子的半导体存储装置中，防止了读取操作和写入操作之间的争用以及响应于内部刷新请求的刷新操作，这防止了故障。

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