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1. 发明公开

EP2287849A2 Semiconductor memory having dual port cell supporting hidden refresh 审中-公开
标题翻译：半导体存储器与适合于透明复习两端口细胞
公开(公告)号：EP2287849A2
公开(公告)日：2011-02-23
申请号：EP10178106.0
申请日：2001-08-29
申请人： Micron Technology, Inc.
发明人： Keeth, Brent , Dennison, Chuck
IPC分类号： G11C11/406 , G11C11/405 , G11C8/16 , G11C11/403
CPC分类号： G11C11/403 , G11C11/406 , Y10S257/907
摘要： The present invention is directed to an integrated circuit device having a memory cell for storing a data and refresh circuitry for refreshing that data in the memory cell. In one illustrative embodiment, the device comprises a memory cell having a storage element, a read/write access device, and a refresh access device. A read/write digit line is coupled to the read/write access 0 device, and a refresh digit line is coupled to the refresh access device. A sense amplifier is coupled to the read/write digit line, and input/output circuitry is coupled to the read/write digit line. A refresh sense amplifier is coupled to the refresh digit line. The memory cell is constructed in such a way as to provide a large charge storage capacity in a relatively small, compact area.

2. 发明授权

EP1056095B1 Adjustable output driver circuit 失效
标题翻译：可调输出驱动器电路
公开(公告)号：EP1056095B1
公开(公告)日：2002-11-06
申请号：EP00115868.2
申请日：1997-12-18
申请人： Micron Technology, Inc.
发明人： Keeth, Brent
IPC分类号： G11C7/10 , H03K17/16
CPC分类号： H03K17/164 , G11C7/1051

3. 发明公开

EP2058820A1 Semiconductor memory having segmented row repair 审中-公开
标题翻译： Haliliterspeicher mit segmentierter Zeilenreparation
公开(公告)号：EP2058820A1
公开(公告)日：2009-05-13
申请号：EP09001943.1
申请日：2001-06-07
申请人： Micron Technology, Inc.
发明人： Keeth, Brent
IPC分类号： G11C29/00
CPC分类号： G11C29/80
摘要： A memory device comprising: a memory array comprising primary memory cells; at least one primary row wordline for accessing a row of said primary memory cells, said at least one primary row wordline being divided into a plurality of segments, each of which accesses a respective portion of said row of said primary memory cells; at least one row of redundant memory cells; at least one redundant row wordline for accessing said redundant memory cells, said at least one redundant row wordline being divided into a plurality of segments, each of which accesses a portion of said redundant memory cells; and a programmable logic circuit which can be selectively programmed to replace at least one of said primary row wordline segments associated with a defective memory cell with a redundant row wordline segment during memory access operation.
摘要翻译：一种存储器件，包括：包括主存储器单元的存储器阵列; 用于访问所述主存储器单元的行的至少一个主行字线，所述至少一个主行字线被划分成多个段，每个段访问所述主存储单元的所述行的相应部分; 至少一行冗余存储单元; 用于访问所述冗余存储器单元的至少一个冗余行字线，所述至少一个冗余行字线被划分成多个段，每个段访问所述冗余存储单元的一部分; 以及可编程逻辑电路，其可以被选择性地编程以在存储器访问操作期间用冗余行字线段替换与缺陷存储器单元相关联的所述主行字线段中的至少一个。

4. 发明公开

EP2267722A8 Method and system for hiding refreshes in a dynamic random access memory 审中-公开
标题翻译：方法和装置用于在DRAM存储器隐藏刷新周期
公开(公告)号：EP2267722A8
公开(公告)日：2011-05-18
申请号：EP10183192.3
申请日：2001-08-14
申请人： Micron Technology, Inc.
发明人： Keeth, Brent , Shirley, Brian M. , Ryan, Kevin J. , Dennison, Charles H.
IPC分类号： G11C7/00
CPC分类号： G11C11/40618 , G11C7/1042 , G11C11/406
摘要： A method and system for refreshing a dynamic random access memory ("DRAM") (40) includes a pair of memory arrays for each of a plurality of banks. The DRAM (40) includes the usual addressing and data path circuitry, as well as a refresh controller (70) that refreshes the arrays in a manner that hides refreshes sufficiently that the DRAM (40) can be used in place of an SRAM as a cache memory (236). Since only one of the arrays in each bank is refreshed at a time, the refresh controller (70) is able to allow data to be written to the array that is not being refreshed. The refresh controller (70) then causes the write data to be temporarily stored so that it can be written to the array of the refresh of the array has been completed. If neither array is being refreshed, the data are written to both arrays. Data are read from the arrays by first checking to determine if any of the arrays is being refreshed. If so, data are read from the array that is not being refreshed.

5. 发明公开

EP1927988A1 Predictive timing calibration for memory devices 有权
标题翻译： Prognostische ZeitkalibrierungfürSpeichergeräte
公开(公告)号：EP1927988A1
公开(公告)日：2008-06-04
申请号：EP07023120.4
申请日：2001-05-07
申请人： Micron Technology, Inc.
发明人： Johnson, Brian , Keeth, Brent
IPC分类号： G11C7/10 , G06F13/16
CPC分类号： G11C11/4076 , G11C7/1072 , G11C2207/2254
摘要： The pressed invention provides a unique way of using a 2 N bit synchronization pattern to obtain a faster and more reliable calibration of multiple data paths in a memory system. If the 2 N bit synchronization pattern is generated with a known clock phase relationship, then the data-to-clock phase alignment can be determined using simple decode logic to predict the next m-bits from a just-detected m-bits. If the succeeding m-bit pattern does not match the predicted pattern, then the current data-to-clock alignment fails for a particular delay value adjustment in the data path undergoing alignment, and the delay in that data path is adjusted to a new value. The invention also ensures that data alignment will occur to a desired edge of the clock signal, e.g., a positive going edge, by forcing a failure of all predicted m-bit patterns which are associated with an undesired edge, e.g., a negative going edge, of the clock signal.
摘要翻译：按压的发明提供了使用2 N位同步模式以获得存储器系统中的多个数据路径的更快更可靠的校准的独特方式。如果以已知的时钟相位关系产生2 N比特同步模式，则可以使用简单的解码逻辑来确定数据到时钟相位对准，以便从刚刚检测到的m位来预测下一个m比特。如果后续的m位模式与预测模式不匹配，则对于经历对准的数据路径中的特定延迟值调整，当前数据对时钟对准失败，并且该数据路径中的延迟被调整到新值。本发明还确保通过强制与不期望的边缘相关联的所有预测的m位模式的故障，例如正向边沿，例如正向边沿，期望数据对准将发生到时钟信号的期望边缘的时钟信号。

6. 发明公开

EP2287849A3 Semiconductor memory having dual port cell supporting hidden refresh 审中-公开
标题翻译：支持隐藏刷新的半双工单元半导体存储器
公开(公告)号：EP2287849A3
公开(公告)日：2011-03-09
申请号：EP10178106.0
申请日：2001-08-29
申请人： Micron Technology, Inc.
发明人： Keeth, Brent , Dennison, Chuck
IPC分类号： G11C11/406 , G11C11/405 , G11C8/16 , G11C11/403
CPC分类号： G11C11/403 , G11C11/406 , Y10S257/907
摘要： The present invention is directed to an integrated circuit device having a memory cell for storing a data and refresh circuitry for refreshing that data in the memory cell. In one illustrative embodiment, the device comprises a memory cell having a storage element, a read/write access device, and a refresh access device. A read/write digit line is coupled to the read/write access 0 device, and a refresh digit line is coupled to the refresh access device. A sense amplifier is coupled to the read/write digit line, and input/output circuitry is coupled to the read/write digit line. A refresh sense amplifier is coupled to the refresh digit line. The memory cell is constructed in such a way as to provide a large charge storage capacity in a relatively small, compact area.
摘要翻译：本发明涉及具有用于存储数据的存储器单元和用于刷新存储器单元中的数据的刷新电路的集成电路器件。在一个说明性实施例中，该设备包括具有存储元件，读取/写入访问设备和刷新访问设备的存储器单元。读/写数字线连接到读/写访问设备，并且刷新数位线连接到刷新访问设备。读出放大器耦合到读/写数字线，输入/输出电路耦合到读/写数字线。刷新感测放大器耦合到刷新数字线。存储器单元被构造为在相对小的紧凑区域中提供大的电荷存储容量。

7. 发明公开

EP2267722A1 Method and system for hiding refreshes in a dynamic random access memory 审中-公开
标题翻译：电子DRAM-Speicher的Verfahren und Vorrichtung zum Verstecken von Refresh-Zyklen
公开(公告)号：EP2267722A1
公开(公告)日：2010-12-29
申请号：EP10183192.3
申请日：2001-08-14
申请人： Micron Technology, Inc.
发明人： Keeth, Brent , Shirley, Brian M. , Ryan, Kevin J. , Dennison, Charles H.
IPC分类号： G11C7/00
CPC分类号： G11C11/40618 , G11C7/1042 , G11C11/406
摘要： A method and system for refreshing a dynamic random access memory ("DRAM") (40) includes a pair of memory arrays for each of a plurality of banks. The DRAM (40) includes the usual addressing and data path circuitry, as well as a refresh controller (70) that refreshes the arrays in a manner that hides refreshes sufficiently that the DRAM (40) can be used in place of an SRAM as a cache memory (236). Since only one of the arrays in each bank is refreshed at a time, the refresh controller (70) is able to allow data to be written to the array that is not being refreshed. The refresh controller (70) then causes the write data to be temporarily stored so that it can be written to the array of the refresh of the array has been completed. If neither array is being refreshed, the data are written to both arrays. Data are read from the arrays by first checking to determine if any of the arrays is being refreshed. If so, data are read from the array that is not being refreshed.
摘要翻译：用于刷新动态随机存取存储器（“DRAM”）（40）的方法和系统包括用于多个存储体中的每一个的一对存储器阵列。 DRAM（40）包括通常的寻址和数据路径电路，以及刷新控制器（70），刷新控制器（70）以更隐蔽的方式刷新阵列，使得可以使用DRAM（40）代替SRAM作为缓存存储器（236）。由于刷新控制器（70）每次只刷新一个阵列中的一个阵列，因此能够将数据写入未刷新的阵列。然后，刷新控制器（70）使得写入数据被暂时存储，使得其可以写入阵列的刷新的阵列已经完成。如果两个数组都不被刷新，数据将被写入两个数组。通过首先检查来确定数组是否被刷新，从数组中读取数据。如果是这样，数据从数组中读取，没有被刷新。

8. 发明授权

EP1927988B1 Predictive timing calibration for memory devices 有权
标题翻译：用于存储设备的预后时间校准
公开(公告)号：EP1927988B1
公开(公告)日：2009-07-22
申请号：EP07023120.4
申请日：2001-05-07
申请人： Micron Technology, Inc.
发明人： Johnson, Brian , Keeth, Brent
IPC分类号： G11C7/10 , G06F13/16
CPC分类号： G11C11/4076 , G11C7/1072 , G11C2207/2254

9. 发明公开

EP2077558A1 Predictive timing calibration for memory devices 有权
标题翻译：存储设备的预测性定时校准
公开(公告)号：EP2077558A1
公开(公告)日：2009-07-08
申请号：EP09005437.0
申请日：2001-05-07
申请人： Micron Technology, Inc.
发明人： Keeth, Brent , Johnson, Brian
IPC分类号： G11C7/10 , G06F13/16
CPC分类号： G11C11/4076 , G11C7/1072 , G11C2207/2254
摘要： The present invention provides a unique way of using a 2 N bit synchronization pattern to obtain a faster and more reliable calibration of multiple data paths in a memory system. If the 2 N bit synchronization pattern is generated with a known clock phase relationship, then the data-to-clock phase alignment can be determined using simple decode logic to predict the next m-bits from a just-detected m-bits. If the succeeding m-bit pattern does not match the predicted pattern, then the current data-to-clock alignment fails for a particular delay value adjustment in the data path undergoing alignment, and the delay in that data path is adjusted to a new value. The invention also ensures that data alignment will occur to a desired edge of the clock signal, e.g., a positive going edge, by forcing a failure of all predicted m-bit patterns which are associated with an undesired edge, e.g., a negative going edge, of the clock signal.
摘要翻译：本发明提供了一种使用2N比特同步模式以获得存储器系统中多个数据路径的更快和更可靠的校准的独特方式。如果以已知的时钟相位关系生成2N比特同步模式，则可以使用简单的解码逻辑来预测来自刚刚检测到的m比特的下一个m比特，从而确定数据到时钟的相位对准。如果后续的m位模式与预测的模式不匹配，则当前的数据 - 时钟对准失败，用于正在进行对准的数据路径中的特定延迟值调整，并且该数据路径中的延迟被调整为新的值。本发明还确保通过迫使与不期望的边缘相关联的所有预测的m位图案的故障（例如，负向边缘）发生数据对齐到时钟信号的期望边缘（例如，正向边缘），时钟信号。

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