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11. 发明公开

EP2758867A2 DIGITAL PROCESSOR HAVING INSTRUCTION SET WITH COMPLEX EXPONENTIAL NON-LINEAR FUNCTION 审中-公开
标题翻译：与具有复杂的非更线性指数功能的命令系列数字处理器
公开(公告)号：EP2758867A2
公开(公告)日：2014-07-30
申请号：EP12844423.9
申请日：2012-10-26
申请人： LSI Corporation
发明人： AZADET, Kameran , MOLINA, Albert , OTHMER, Joseph, H. , VENKATARAGHAVAN, Parakalan , YU, Meng-Jin , WILLIAMS, Joseph
IPC分类号： G06F9/06 , G06F9/30 , G06F9/44
CPC分类号： G06F9/3001 , G06F5/01 , G06F9/30036 , G06F17/15 , H03F1/0288 , H03F1/3241 , H03F1/3258 , H03F3/189 , H03F3/24 , H03F2200/336 , H03F2201/3209 , H03F2201/3212 , H03F2201/3224 , H03F2201/3233 , H03H17/06 , H03M3/30 , H04B1/0003 , H04B1/0475 , H04B1/62 , H04B2001/0408 , H04L1/0054 , H04L25/02 , H04L25/03 , H04L25/03178 , H04L25/03216 , H04L25/4917 , H04L27/2334
摘要： A digital processor is provided having an instruction set with a complex exponential function. The digital processor evaluates a complex exponential function for an input value, x, by obtaining a complex exponential software instruction having the input value, x, as an input; and in response to the complex exponential software instruction: invoking at least one complex exponential functional unit that implements complex exponential software instructions to apply the complex exponential function to the input value, x; and generating an output corresponding to the complex exponential of the input value, x. A complex exponential function for an input value, x, can be evaluated by wrapping the input value to maintain a given range; computing a coarse approximation angle using a look-up table; scaling the coarse approximation angle to obtain an angle from 0 to θ; and computing a fine corrective value using a polynomial approximation.

12. 发明公开

EP3210299A1 RADIO FREQUENCY AMPLIFIER 审中-公开
标题翻译：无线电频率放大器
公开(公告)号：EP3210299A1
公开(公告)日：2017-08-30
申请号：EP15790637.1
申请日：2015-10-20
申请人： Cambridge Consultants Limited
发明人： DONOGHUE, Bryan James , PHILLIPS, Desmond , ROBERT, Tan , HERVE, Peter-Contesse
IPC分类号： H03F3/217 , H03M3/02
CPC分类号： H03F3/2175 , H03F2200/331 , H03M3/30 , H03M3/47 , H03M3/50
摘要： Successive blocks of an input signal are fed to M respective delta-sigma modulator channels 11, in which the output FIFOs 17 are filled at a rate that is about 1/M of the rate at which the contents of these FIFOs 17 are read through the multiplexer 20. This use of multiple parallel channels allows a lower clock rate to be used, so that delta-sigma modulators for switching UHF amplifiers become practical. Transients that may be evident upon a changeover between channels are reduced by overlaps (figure 5). The channels may be reset between the processing of data blocks, so that instability, to which high-order delta-sigma modulators are susceptible, does not have time to arise. The modulator may be used in class-S RF amplifiers or in analogue-to-digital converters.
摘要翻译：输入信号的连续块被馈送到M个相应的德耳塔西格玛调制器通道11，其中输出FIFO 17以大约为通过滤波器读取这些FIFO 17的内容的速率的1 / M的速率填充多路复用器20.这种多个并行通道的使用允许使用较低的时钟速率，使得用于切换UHF放大器的Δ-Σ调制器变得实用。通道间切换时可能出现的瞬态会因重叠而减少（图5）。信道可以在数据块的处理之间重置，使得高阶Δ-Σ调制器易受影响的不稳定性没有时间出现。该调制器可用于S类RF放大器或模数转换器。

13. 发明公开

EP3075077A4 METHODS AND DEVICES FOR ERROR CORRECTION OF A SIGNAL USING DELTA SIGMA MODULATION 审中-公开
标题翻译： VERFAHREN UND VORRICHTUNGEN ZUR FEHLERKORREKTUR EINES信号在SIGMA-DELTA调制
公开(公告)号：EP3075077A4
公开(公告)日：2017-08-09
申请号：EP13898054
申请日：2013-11-28
申请人： SMART ENERGY INSTR INC
发明人： DIONNE DONALD JEFFREY , HOWSE BRIAN LEONARD WILLIAM , MCCANN JENNIFER MARIE
IPC分类号： H03L7/085 , H03L1/00 , H03M3/02
CPC分类号： H03L7/0994 , G06F1/02 , G06F17/10 , H03L1/00 , H03L7/081 , H03L7/095 , H03M3/30

14. 发明公开

EP3182597A1 CIRCUITRY AND METHOD FOR CONVERTING ANALOG SIGNAL TO DIGITAL VALUE REPRESENTATION 审中-公开
标题翻译：将模拟信号转换为数字值表示的电路和方法
公开(公告)号：EP3182597A1
公开(公告)日：2017-06-21
申请号：EP15200350.5
申请日：2015-12-16
申请人： IMEC VZW
发明人： CRANINCKX, Jan , DE BOCK, Maarten , BORREMANS, Jonathan
IPC分类号： H03M3/00
CPC分类号： H03M3/458 , H03M1/00 , H03M1/12 , H03M1/365 , H03M3/30 , H03M3/322 , H03M3/39 , H03M3/496
摘要： The present invention relates to a circuitry and a method for converting an analog signal to a digital value representation, said circuitry (10) comprising: an incremental sigma-delta analog-to-digital converter, ADC, (20); a first input line (12) for providing a primary analog signal representing a sensor measurement to the incremental sigma-delta ADC (20), a second input line (14) for providing a secondary analog signal to the incremental sigma-delta ADC (20), said circuitry (10) being configured such that the incremental sigma-delta ADC (20) receives the primary analog signal during a first period ( T ADC1 ) and receives the secondary analog signal during a second period ( T ADC2 ), and said circuitry (10) further comprising a filter (30), said filter (30) being configured to weigh the digital values in a sequence of digital values output by the incremental sigma-delta ADC (20) and to output a single digital value representing the sensor measurement.
摘要翻译：本发明涉及用于将模拟信号转换为数字值表示的电路和方法，所述电路（10）包括：增量Σ-Δ模数转换器ADC（20）; 第一输入线（12），用于向递增Σ-ΔADC（20）提供表示传感器测量的初级模拟信号;第二输入线（14），用于向递增Σ-ΔADC（20）提供第二模拟信号），所述电路（10）被配置为使得所述递增Σ-ΔADC（20）在第一时间段（TADC1）期间接收所述主要模拟信号并且在第二时间段（TADC2）期间接收所述次要模拟信号，并且所述电路 10）还包括滤波器（30），所述滤波器（30）被配置为对由递增sigma-delta ADC（20）输出的数字值序列中的数字值进行加权并输出代表传感器测量值的单个数字值。

15. 发明公开

EP3101811A1 GENERATING COMPARATOR THRESHOLDS USING A ROTATING RING OF RESISTORS 审中-公开
标题翻译： ERZEUGUNG VON KOMPARATORSCHWELLEN MIT EINEM ROTIERENDEN RING VONWIDERSTÄNDEN
公开(公告)号：EP3101811A1
公开(公告)日：2016-12-07
申请号：EP16170418.4
申请日：2016-05-19
申请人： Analog Devices Global
发明人： YANG, Wenhua W. , SCHREIER, Richard E.
IPC分类号： H03M1/06 , H03M3/00 , H03M1/36
CPC分类号： H03M1/066 , H03M1/365 , H03M3/30 , H03M3/50
摘要： Data converters convert signals in analog form to digital form or from digital form to analog form. Due to mismatches between devices that are intended to be identical (unary elements), some data converters outputs may have undesirable characteristics, such as non-linearities. Shuffling the inputs to the unary elements based on a pseudo-random sequence is a technique that can average out the mismatches over time. However, shuffling generally requires a complex switch matrix, and can potentially impact the speed of the converter. To address mismatches, a high speed technique for rotating comparator thresholds is implemented to effectively rotate an array of unary digital-to-analog converter elements. The technique is particularly advantageous for addressing mismatches in unary digital-to-analog converters used for reconstructing a quantized analog signal within delta-sigma analog-to-digital converter.
摘要翻译：数据转换器将模拟形式的信号转换为数字形式或从数字形式转换为模拟形式。由于设计为相同（一元）的设备之间的不匹配，一些数据转换器输出可能具有不希望的特性，如非线性。基于伪随机序列对一元元素的输入进行混洗是可以随时间推移不平衡的技术。然而，混洗通常需要复杂的开关矩阵，并且可能会影响转换器的速度。为了解决不匹配，实现了用于旋转比较器阈值的高速技术来有效地旋转一元数模转换器元件阵列。该技术对于解决用于在Δ-Σ模数转换器内重建量化模拟信号的一元数模转换器中的不匹配特别有利。

16. 发明公开

EP2962382A4 CAPACITIVE MICRO-MACHINED SENSOR FORCE-FEEDBACK MODE INTERFACE SYSTEM 审中-公开
标题翻译：力反馈模式界面系统电容式微处理的传感器
公开(公告)号：EP2962382A4
公开(公告)日：2016-11-16
申请号：EP14756376
申请日：2014-02-27
申请人： SI WARE SYSTEMS
发明人： ISMAIL AYMAN , ELSHENNAWY AHMED , MOKHTAR AHMED , ELSAYED AYMAN
IPC分类号： H03M1/48 , G01R33/038 , G06F1/16 , G06F3/0346 , G06F3/038 , H03H11/04 , H03H11/12 , H03H19/00 , H03K5/13 , H03M3/00
CPC分类号： H03M3/368 , B81B2207/03 , G01R33/038 , G06F1/10 , G06F1/1694 , G06F3/0346 , G06F3/0383 , H03H11/0422 , H03H11/1291 , H03H19/004 , H03K5/133 , H03M1/00 , H03M1/12 , H03M1/48 , H03M1/804 , H03M3/30 , H03M3/43

17. 发明授权

EP2949045B1 VERFAHREN UND VORRICHTUNG ZUM ERZEUGEN EINES DIGITALEN SIGNALS 有权转让
标题翻译：方法和设备，用于生成数字信号
公开(公告)号：EP2949045B1
公开(公告)日：2016-08-24
申请号：EP14701215.7
申请日：2014-01-24
申请人： Lenze Automation GmbH
发明人： DÜSTERBERG, Dirk , STICHWEH, Heiko
IPC分类号： H03M3/00 , H02M5/00
CPC分类号： H03M3/458 , H02M5/00 , H03M1/00 , H03M1/12 , H03M3/30 , H03M3/504

18. 发明公开

EP2974032A1 4N+1 LEVEL CAPACITIVE DAC USING N CAPACITORS 有权
标题翻译：使用N个电容的4N + 1电平电容DAC
公开(公告)号：EP2974032A1
公开(公告)日：2016-01-20
申请号：EP14720287.3
申请日：2014-03-10
申请人： Microchip Technology Incorporated
发明人： QUIQUEMPOIX, Vincent
IPC分类号： H03M1/06 , H03M3/04
CPC分类号： H03M1/802 , H03M1/0665 , H03M3/30 , H03M3/424 , H03M3/464
摘要： A digital-to analog converter (DAC) of the charge transfer type for use in a sigma delta modulator, includes a capacitor switch unit operable to generate a 4n+l output levels, comprising: a plurality of second switching units for coupling first terminals of a plurality of reference capacitor pairs with either a positive or a negative reference signal; wherein the second terminals of the plurality of reference capacitor pairs are coupled in parallel, respectively; wherein for even transfers a single switching combination is provided to achieve linearity and wherein for odd transfers an average of different switching combinations is provided to achieve linearity; wherein an even transfer is when an input of the DAC is even and an odd transfer is when an input to the DAC is odd.
摘要翻译：用于Σ-Δ调制器中的电荷传输类型的数模转换器（DAC）包括可操作用于生成4n + 1输出电平的电容器开关单元，该电容器开关单元包括：多个第二开关单元，用于将具有正参考信号或负参考信号的多个参考电容器对; 其中所述多个参考电容器对的第二端子分别并联耦合; 其中为了偶数传输，提供单个开关组合以实现线性，并且其中对于奇数传输，提供平均不同开关组合以实现线性; 其中偶数传输是当DAC的输入是偶数时并且奇数传输是当DAC的输入是奇数时。

19. 发明公开

EP2949045A2 VERFAHREN UND VORRICHTUNG ZUM ERZEUGEN EINES DIGITALEN SIGNALS 有权转让
标题翻译：方法和设备，用于生成数字信号
公开(公告)号：EP2949045A2
公开(公告)日：2015-12-02
申请号：EP14701215.7
申请日：2014-01-24
申请人： Lenze Automation GmbH
发明人： DÜSTERBERG, Dirk , STICHWEH, Heiko
IPC分类号： H03M3/00 , H02M5/00
CPC分类号： H03M3/458 , H02M5/00 , H03M1/00 , H03M1/12 , H03M3/30 , H03M3/504
摘要： The invention relates to a method for producing a digital signal (DS) from an analog signal (UA) produced by means of a frequency converter on the basis of a pulse-width modulation having a variable period duration, wherein values of the digital signal (DS) correspond to a mean of the analog signal (UA) over an associated period duration of the pulse-width modulation, comprising the following steps: producing a bit stream (BS) as a function of the analog signal (UA) by means of a sigma-delta modulator (1), wherein the bit stream is produced with a constant modulator cycle time, producing temporally successive digital sampled values (S_1 to S_r) during an associated period duration by filtering the bit stream (BS) by means of a number of digital filters (2_1 to 2_r), wherein time intervals between the temporally successive digital sampled values are multiples of the modulator cycle time, the digital filters (2_1 to 2_r) are started at time offsets from each other in the time intervals of the multiples of the modulator cycle time, and each digital filter (2_1 to 2_r) outputs an associated digital sampled value (S_1 to S_r), and calculating a mean of the digital sampled values (S_1 to S_r) produced during the associated period duration, wherein the mean forms the value of the digital signal (DS) for the associated period duration.

20. 发明公开

EP2888683A1 DESIGN AUTOMATION FOR CONFIGURABLE MIXED-SIGNAL SYSTEMS 无效
标题翻译：设计自动化配置型混合信号系统
公开(公告)号：EP2888683A1
公开(公告)日：2015-07-01
申请号：EP13759342.2
申请日：2013-08-16
申请人： Missing Link Electronics Inc.
发明人： SCHUBERT, Nils Endric , BROCK, Johannes , GRUMBEIN, Christian
IPC分类号： G06F17/50 , H03M7/30 , H03M3/00
CPC分类号： H03M3/458 , G06F17/5022 , G06F17/5054 , G06F17/5063 , H03M3/30 , H03M3/392 , H03M3/46 , H03M7/3015
摘要： Configuration information is generated for a configurable mixed-signal system. Analog requirements for operating the configurable mixed-signal system are gathered. A simulation model of a delta-sigma modulator is received. A simulation based on the simulation model of the delta-sigma modulator is performed to obtain parameter settings for the delta-sigma modulator. The obtained parameter settings are used to build at least a portion of a description of the configurable mixed-signal system. The description of the configurable mixed signal system is synchronized to receive configuration information.

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