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11. 发明公开

EP2758867A2 DIGITAL PROCESSOR HAVING INSTRUCTION SET WITH COMPLEX EXPONENTIAL NON-LINEAR FUNCTION 审中-公开
标题翻译：与具有复杂的非更线性指数功能的命令系列数字处理器
公开(公告)号：EP2758867A2
公开(公告)日：2014-07-30
申请号：EP12844423.9
申请日：2012-10-26
申请人： LSI Corporation
发明人： AZADET, Kameran , MOLINA, Albert , OTHMER, Joseph, H. , VENKATARAGHAVAN, Parakalan , YU, Meng-Jin , WILLIAMS, Joseph
IPC分类号： G06F9/06 , G06F9/30 , G06F9/44
CPC分类号： G06F9/3001 , G06F5/01 , G06F9/30036 , G06F17/15 , H03F1/0288 , H03F1/3241 , H03F1/3258 , H03F3/189 , H03F3/24 , H03F2200/336 , H03F2201/3209 , H03F2201/3212 , H03F2201/3224 , H03F2201/3233 , H03H17/06 , H03M3/30 , H04B1/0003 , H04B1/0475 , H04B1/62 , H04B2001/0408 , H04L1/0054 , H04L25/02 , H04L25/03 , H04L25/03178 , H04L25/03216 , H04L25/4917 , H04L27/2334
摘要： A digital processor is provided having an instruction set with a complex exponential function. The digital processor evaluates a complex exponential function for an input value, x, by obtaining a complex exponential software instruction having the input value, x, as an input; and in response to the complex exponential software instruction: invoking at least one complex exponential functional unit that implements complex exponential software instructions to apply the complex exponential function to the input value, x; and generating an output corresponding to the complex exponential of the input value, x. A complex exponential function for an input value, x, can be evaluated by wrapping the input value to maintain a given range; computing a coarse approximation angle using a look-up table; scaling the coarse approximation angle to obtain an angle from 0 to θ; and computing a fine corrective value using a polynomial approximation.

12. 发明授权

EP3235136B1 OSCILLATOR CALIBRATION 有权
公开(公告)号：EP3235136B1
公开(公告)日：2018-12-05
申请号：EP15813517.8
申请日：2015-12-14
申请人： Nordic Semiconductor ASA
发明人： WEBERG, Stein Erik , SUNDSBØ, Ingil
IPC分类号： H03L7/197
CPC分类号： H03L7/197 , H03L7/085 , H03L7/0992 , H03L7/1976 , H03M3/30 , H04B1/40
摘要： A phase locked loop comprises: a controllable oscillator 102; a variable divider arrangement 108 / 110 which takes a signal from the controllable oscillator 102 and divides it by a variable amount to provide a lower frequency signal; a sigma-delta modulator 112 arranged to provide a control input to the variable divider arrangement 108 / 110; and a phase detector triggered 104 by the lower frequency signal, and a reference clock. The loop is arranged to operate in a normal mode in which the controllable oscillator 102 is controlled by a voltage from the phase detector 104, and in a calibration mode in which the controllable oscillator 102 is controlled digitally by a signal from a calibration module 114 which receives an input from said variable divider arrangement 108 / 110. Calibration may involve pre-setting the oscillator with a coarse tuning signal so that voltage control of the output frequency only needs to be used for fine tuning within a small subset of the overall frequency range. This in turn reduces the sensitivity of the controllable oscillator, reducing problems of noise.

13. 发明公开

EP3280055A1 DELTA-SIGMA MODULATOR WITH DELTA-SIGMA TRUNCATOR AND ASSOCIATED METHOD FOR REDUCING LEAKAGE ERRORS OF DELTA-SIGMA MODULATOR 审中-公开
标题翻译：具有DELTA-SIGMA调制器的DELTA-SIGMA调制器以及用于减少DELTA-SIGMA调制器的泄漏错误的相关方法
公开(公告)号：EP3280055A1
公开(公告)日：2018-02-07
申请号：EP17182826.2
申请日：2017-07-24
申请人： MediaTek Inc.
发明人： WENG, Chan-Hsiang , LO, Tien-Yu
IPC分类号： H03M3/04 , H03M1/06
CPC分类号： H03M3/426 , H03M1/00 , H03M1/066 , H03M1/12 , H03M3/30 , H03M3/428 , H03M3/436 , H03M3/454
摘要： A delta-sigma modulator includes a receiving circuit, a loop filter module, a quantizer, a delta-sigma truncator, a digital filter module, and an output circuit. The receiving circuit is arranged for receiving a feedback signal and an input signal to generate a summation signal. The loop filter module is arranged for filtering the summation signal to generate a filtered summation signal. The quantizer is arranged for generating a first digital signal according to the filtered summation signal. The delta-sigma truncator is arranged for truncating the first digital signal to generate a second digital signal. The digital filter module is arranged for filtering the first digital signal and the second digital signal to generate a filtered first digital signal and a filtered second digital signal, respectively. The output circuit is arranged for generating an output signal according to the filtered first digital signal and the filtered second digital signal.
摘要翻译： Δ-Σ调制器包括接收电路，环路滤波器模块，量化器，Δ-Σ截断器，数字滤波器模块和输出电路。接收电路被设置用于接收反馈信号和输入信号以生成求和信号。环路滤波器模块用于对求和信号进行滤波以产生滤波后的和信号。量化器用于根据滤波后的和信号生成第一数字信号。 Δ-Σ截断器被设置用于截断第一数字信号以产生第二数字信号。数字滤波器模块用于对第一数字信号和第二数字信号进行滤波，以分别生成滤波后的第一数字信号和滤波后的第二数字信号。输出电路用于根据滤波后的第一数字信号和滤波后的第二数字信号生成输出信号。

14. 发明公开

EP3238342A4 SYSTEM AND METHOD FOR DATA CONVERSION OF SIGNALS USING NOISE SHAPING 审中-公开
公开(公告)号：EP3238342A4
公开(公告)日：2018-01-24
申请号：EP15877665
申请日：2015-12-04
申请人： HUAWEI TECH CO LTD
发明人： HU LAN , KILAMBI SAI MOHAN
IPC分类号： H03M3/00 , H03M7/30 , H04L25/03
CPC分类号： H03M3/30 , H03M3/416 , H03M3/42 , H03M3/50 , H03M7/3022
摘要： Apparatus and methods are taught for dividing a signal to be processed by a Noise Shaping (Hereafter NS) loop into smaller sections, and applying NS to at least a subset of these smaller sections. The processed signals are then recombined. As noise shaping is performed on smaller sections, the operating speed of each noise shaping loop, and accordingly for the system in general, is faster than if the output signal had been generated by single higher bit NS loop. Embodiments further include a configuration block for configuring the apparatus. For example, the number of sections, the section calculation method, and the NS for each section can each be configurable, and for some embodiments, programmable.

15. 发明公开

EP3270256A1 NOISE REDUCTION CIRCUIT AND ASSOCIATED DELTA-SIGMA MODULATOR 有权
标题翻译：降噪电路和相关的DELTA-SIGMA调制器
公开(公告)号：EP3270256A1
公开(公告)日：2018-01-17
申请号：EP17178615.5
申请日：2017-06-29
申请人： MediaTek Inc.
发明人： TSAI, Hung-Chieh
IPC分类号： G05F3/02 , G05F3/26 , G05F1/46 , H03F1/30 , H03M3/00
CPC分类号： H03M3/322 , G05F3/262 , H03F1/26 , H03F3/193 , H03F2200/498 , H03M1/00 , H03M1/12 , H03M3/30 , H03M3/368 , H03M3/422 , H03M3/50
摘要： A circuit (100) includes a transistor (M0), a signal generating circuit (120) and a noise sensing circuit (110). The signal generating circuit (120) is arranged to provide an input signal. The noise sensing circuit (110) is coupled to the transistor (M0) and the signal generating circuit (120), and the noise sensing circuit (110) is arranged for receiving the input signal provided by the signal generating circuit (120) to generate an output signal to the transistor (M0), wherein a signal component of the output signal generated by the noise sensing circuit (110) cancels out a signal component of the input signal provided by the signal generating circuit (120), and the output signal and the input signal have opposite polarities.
摘要翻译：电路（100）包括晶体管（M0），信号生成电路（120）和噪声感测电路（110）。信号生成电路（120）被配置为提供输入信号。噪声感测电路110耦接晶体管M0与信号产生电路120，噪声感测电路110用以接收信号产生电路120所提供的输入信号以产生（M0）的输出信号，其中由噪声感测电路（110）产生的输出信号的信号分量抵消由信号生成电路（120）提供的输入信号的信号分量，并且输出信号和输入信号具有相反的极性。

16. 发明公开

EP3238342A1 SYSTEM AND METHOD FOR DATA CONVERSION OF SIGNALS USING NOISE SHAPING 审中-公开
标题翻译：用噪声整形信号数据转换的系统和方法
公开(公告)号：EP3238342A1
公开(公告)日：2017-11-01
申请号：EP15877665.8
申请日：2015-12-04
申请人： Huawei Technologies Co. Ltd.
发明人： HU, Lan , KILAMBI, Sai Mohan
IPC分类号： H03M3/00 , H04L25/03
CPC分类号： H03M3/30 , H03M3/416 , H03M3/42 , H03M3/50 , H03M7/3022
摘要： Apparatus and methods are taught for dividing a signal to be processed by a Noise Shaping (Hereafter NS) loop into smaller sections, and applying NS to at least a subset of these smaller sections. The processed signals are then recombined. As noise shaping is performed on smaller sections, the operating speed of each noise shaping loop, and accordingly for the system in general, is faster than if the output signal had been generated by single higher bit NS loop. Embodiments further include a configuration block for configuring the apparatus. For example, the number of sections, the section calculation method, and the NS for each section can each be configurable, and for some embodiments, programmable.
摘要翻译：教导了用于将由噪声整形（此后称NS）环路处理的信号划分为更小部分并将NS应用于这些更小部分的至少一个子集的装置和方法。处理后的信号然后重新组合。由于噪声整形是在较小的部分上执行的，因此每个噪声整形环路的运行速度以及相应的系统总体上的运行速度比如果输出信号已经由单个较高位NS环路产生的情况更快。实施例还包括用于配置设备的配置块。例如，每个部分的部分的数量，部分计算方法和NS可以各自是可配置的，并且对于一些实施例可以是可编程的。

17. 发明授权

EP2809007B1 Electric signal conversion 有权转让
标题翻译：电信号的转换
公开(公告)号：EP2809007B1
公开(公告)日：2017-03-22
申请号：EP14168345.8
申请日：2014-05-14
申请人： Analog Devices Global
发明人： Caldwell, Trevor Clifford , Schreier, Richard E. , Alldred, David , Yang, Wenhua W.
IPC分类号： H03M1/06 , H03M1/36 , H03M1/74 , H03M3/00
CPC分类号： H03M1/0673 , H03M1/361 , H03M1/74 , H03M3/30 , H03M3/338 , H03M3/464

18. 发明公开

EP2962392A1 2-PHASE SWITCHED CAPACITOR FLASH ADC 有权转让
标题翻译： FLASH-ADC MIT EINEM 2-PHASEN-GESCHALTETEN KONDENSATOR
公开(公告)号：EP2962392A1
公开(公告)日：2016-01-06
申请号：EP14708423.0
申请日：2014-02-20
申请人： Microchip Technology Incorporated
发明人： QUIQUEMPOIX, Vincent
IPC分类号： H03K5/15
CPC分类号： H03M3/34 , H03K5/15 , H03M1/00 , H03M1/12 , H03M1/804 , H03M3/30 , H03M3/322 , H03M3/356 , H03M3/422
摘要： An input stage for a switched capacitor analog-to-digital converter has a differential voltage input receiving an input voltage, a differential reference voltage input receiving a chopped reference voltage, a common voltage connection, and a differential output. A pair of input capacitors is coupled between the differential voltage input and the differential output and a pair of reference capacitors is coupled between the differential reference voltage input. A switching unit is controlled by a first and second phase operable during the first phase to connect a first terminal of the input capacitors with the common voltage connection and couple the first terminal of the reference capacitors with the inverted differential voltage reference; and during a second phase to connect the first terminal of the input capacitors with the differential input voltage and couple the first terminal of the reference capacitors with the non-inverted differential voltage reference.
摘要翻译：用于开关电容器模拟 - 数字转换器的输入级具有接收输入电压的差分电压输入端，接收斩波参考电压的差分参考电压输入，公共电压连接和差分输出。一对输入电容器耦合在差分电压输入和差分输出之间，一对参考电容耦合在差分参考电压输入端之间。开关单元由在第一阶段期间可操作的第一和第二相位来控制，以将输入电容器的第一端与公共电压连接相连，并将参考电容器的第一端与反相的差分电压基准耦合; 并且在第二阶段期间，将输入电容器的第一端子与差分输入电压连接，并将参考电容器的第一端子与非反相差分电压基准耦合。

19. 发明公开

EP2758867A4 DIGITAL PROCESSOR HAVING INSTRUCTION SET WITH COMPLEX EXPONENTIAL NON-LINEAR FUNCTION 审中-公开
标题翻译：与具有复杂的非更线性指数功能的命令系列数字处理器
公开(公告)号：EP2758867A4
公开(公告)日：2015-07-08
申请号：EP12844423
申请日：2012-10-26
申请人： LSI CORP
发明人： AZADET KAMERAN , MOLINA ALBERT , OTHMER JOSEPH H , VENKATARAGHAVAN PARAKALAN , YU MENG-JIN , WILLIAMS JOSEPH
IPC分类号： G06F17/15 , G06F1/03 , G06F9/30
CPC分类号： G06F9/3001 , G06F5/01 , G06F9/30036 , G06F17/15 , H03F1/0288 , H03F1/3241 , H03F1/3258 , H03F3/189 , H03F3/24 , H03F2200/336 , H03F2201/3209 , H03F2201/3212 , H03F2201/3224 , H03F2201/3233 , H03H17/06 , H03M3/30 , H04B1/0003 , H04B1/0475 , H04B1/62 , H04B2001/0408 , H04L1/0054 , H04L25/02 , H04L25/03 , H04L25/03178 , H04L25/03216 , H04L25/4917 , H04L27/2334

20. 发明公开

EP2797236A2 Zeitkontinuierlicher Delta-Sigma-Modulator 有权转让
标题翻译：连续时间Σ-Δ调制器
公开(公告)号：EP2797236A2
公开(公告)日：2014-10-29
申请号：EP14001368.1
申请日：2014-04-15
申请人： Micronas GmbH
发明人： Muthers, David
IPC分类号： H03M3/00
CPC分类号： H03M3/30 , H03M3/322 , H03M3/458
摘要： Zeitkontinuierlicher Delta-Sigma-Modulator,
- mit einem Integrator (Int) und einem mit einer Taktfrequenz (f clk ) getakteten Komparator (Comp), die in einer Rückkopplungsschleife verbunden sind,
- mit einer Spannungsquelle (Cal), die mit dem Komparator (Comp) zum Anlegen einer Schwellspannung (V th ) an den Komparator (Comp) verbunden ist,
- bei dem eine Integrationszeitkonstante des Integrators (Int) einen ersten Widerstand (R 1 ) und eine erste Kapazität (C 1 ) aufweist,
- bei dem die Spannungsquelle (Cal) einen zweiten Widerstand (R 2 ) und eine zweite Kapazität (C 2 ) zur Einstellung der Schwellspannung (V th ) aufweist,
- bei dem der erste Widerstand (R 1 ) und der zweite Widerstand (R 2 ) Bestandteil einer Widerstandspaarungsstruktur sind, und
- bei dem die erste Kapazität (C 1 ) und die zweite Kapazität (C 2 ) Bestandteil einer Kapazitätspaarungsstruktur sind.
摘要翻译：连续时间三角积分调制器， - 一个积分器（INT）和一个（F CLK）计时的比较（对照）与时钟频率，其被连接在反馈回路中， - 一个电压源（CAL），其中（到比较器Comp ）（用于施加阈值电压V th）（以比较器Comp）连接， - 其中，所述积分器（INT）的第一电阻器（R 1）的积分时间常数和第一电容（C 1）， - 其中，所述电压源（CAL）的第二电阻器（R 2）和用于调节所述阈值电压（V th）的第二电容（C 2），其 - 其中，所述第一电阻器（R 1）和第二电阻（R 2）成分的电阻匹配结构的是，其中所述第一电容（C 1）和所述第二电容器的容量配对结构的（C 2）成分 - 和。

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