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11. 发明公开

EP0905892A2 RS-Flip-Flop mit Enable-Eingängen 失效
公开(公告)号：EP0905892A2
公开(公告)日：1999-03-31
申请号：EP98114223.5
申请日：1998-07-29
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： Johnson, Bret , Schneider, Ralf
IPC分类号： H03K3/037
CPC分类号： H03K3/356113 , H03K3/037 , H03K3/356165
摘要： Die Erfindung betrifft ein RS-Flip-Flop mit einem mit einem Eingangsanschluß (IN) verbundenen Inverter (14), einem einen Enable-Set-Anschluß (ENS) aufweisenden NOR-Gatter (15) und einem einen Enable-Reset-Anschluß (ENR) aufweisenden NAND-Gatter (17) und jeweils einem mit dem Inverter (14) verbundenen ersten und zweiten Transistor (12 bzw. 13). Der Ausgang des NOR- bzw. NAND-Gatters (15 bzw. 17) ist über die Gate-Strecke des ersten bzw. zweiten Transistors (12 bzw. 11) an die Gateelektrode von jeweils einem von zwei in Reihe liegenden und ein Halteglied bildenden dritten und vierten Transistoren (16, 18) angeschlossen, deren gemeinsamer Verbindungspunkt mit dem Ausgang des Inverters (14) und dem Ausgangsanschluß (Q) des Flip-Flops zusammengeschaltet ist.
摘要翻译： RS触发器具有耦合到输入端子（IN）的反相器（14），具有使能置位端子（ENS）的NOR门（15）和具有使能复位端子的NAND门（17） ENR），每个具有将其耦合到逆变器的晶体管（12,13）。栅极的输出经由后者晶体管的栅极通路耦合到具有耦合到反相器的输出并且提供触发器输出端（Q）的公共端的另外的晶体管（16,18）。

12. 发明公开

EP0570597A1 FLASH MEMORY IMPROVED IN ERASING CHARACTERISTIC, AND CIRCUIT THEREFOR 失效
标题翻译： FLASH-SPEICHER MIT VERBESSERTENLÖSCHEIGENSCHAFTENUND SCHALTUNGDAFÜR。
公开(公告)号：EP0570597A1
公开(公告)日：1993-11-24
申请号：EP92924898.7
申请日：1992-12-09
申请人： FUJITSU LIMITED
发明人： AKAOGI, Takao Fujitsu Limited 1015, Kamikodanaka , KAWASHIMA, Hiromi Fujitsu Limited , TAKEGUCHI, Tetsuji Fujitsu Limited , HAGIWARA, Ryoji Fujitsu Limited , KASA, Yasushi Fujitsu Limited 1015, Kamikodanaka , ITANO, Kiyoshi Fujitsu Limited 1015, Kamikodanaka , OGAWA, Yasushige Fujitsu VLSI Limited , KAWAMURA, Shouichi Fujitsu Limited
IPC分类号： G11C16/06 , H03K19/21
CPC分类号： G11C29/82 , G05F3/205 , G11C5/145 , G11C16/0416 , G11C16/08 , G11C16/16 , G11C16/30 , H03K3/356147 , H03K3/356165 , H03K19/018521 , H03K19/215
摘要： A flash memory improved in its erasing operation by shortening its erasing time, wherein, when data is written prior to erasing, by selecting a plurality of lines of at least either of word lines and bit lines simultaneously, data is written into a plurality of transistors in concurrence.
摘要翻译：闪存通过缩短擦除时间来改善其擦除操作，其中当通过同时选择字线和位线中的至少一个的数行时，在擦除之前写入数据时，将数据写入多个晶体管同意。

13. 发明公开

EP1940028A1 Asynchronous interconnection system for 3D inter-chip communication 有权转让
标题翻译：不同步的Verbindungssystemfür3D-Inter-Chip-Kommunikation
公开(公告)号：EP1940028A1
公开(公告)日：2008-07-02
申请号：EP06027047.7
申请日：2006-12-29
申请人： STMicroelectronics S.r.l.
发明人： Fazzi, Alberto , Guerrieri, Roberto , Magagni, Luca , Ciccarelli, Luca , Canegallo, Roberto
IPC分类号： H03K19/0185 , H03K19/00
CPC分类号： H03K19/018521 , H03K3/356165
摘要： The present invention relates to a asynchronous interconnection system (10) comprising a transmitter circuit (11) and a receiver circuit (12) inserted between inserted between respective first and second voltage references (Vcctx, GNDtx - Vccrx, GNDrx) and having respective transmitter and receiver nodes (TX, RX) coupled in a capacitive manner.
Advantageously according to the invention, the receiver circuit (12) comprises:
- a recovery stage (13) inserted between the first and second voltage references (Vccrx, GNDrx) of the receiver circuit (12) and connected to the receiver node (RX); and
- a state control stage (14), in turn inserted between the first and second voltage references (Vccrx, GNDrx) of the receiver circuit (12) connected to the recovery stage (13) correspondence with a first feedback node (X) providing a first control signal (Recovery Enable) and having a second feedback node (Z*) connected in a feedback manner to the recovery stage (13).
The recovery stage (13) comprises a first feedback loop (Loop 1) connected to the first feedback node (X) and acting in such a way to recover a received voltage signal and a feedback loop (Loop2) connected to the second feedback node (Z*) of the state control stage (14) and acting in such a way to deactivate the recovery feedback on the receiver node (RX) and guarantee that the receiver node (RX) is let in a high impedance state.
摘要翻译：本发明涉及一种异步互连系统（10），包括发射机电路（11）和插入在相应的第一和第二电压基准（Vcctx，GNDtx-Vccrx，GNDrx）之间的接收机电路（12），并且具有各自的发射机和接收器节点（TX，RX）以电容方式耦合。有利地，根据本发明，接收器电路（12）包括： - 插入在接收器电路（12）的第一和第二电压基准（Vccrx，GNDrx）之间并连接到接收器节点（RX）的恢复级（13） ; 以及 - 状态控制级（14），其又插入在与恢复级（13）连接的接收器电路（12）的第一和第二电压基准（Vccrx，GNDrx）之间，与第一反馈节点（X）对应，提供第一控制信号（恢复使能）并且具有以反馈方式连接到恢复级（13）的第二反馈节点（Z *）。恢复阶段（13）包括连接到第一反馈节点（X）的第一反馈回路（回路1），并以这样一种方式起作用以恢复接收的电压信号和连接到第二反馈节点的反馈回路（Loop2）状态控制级（14）的Z *），并以这样一种方式使接收器节点（RX）上的恢复反馈失效，并保证接收器节点（RX）处于高阻抗状态。

14. 发明公开

EP1560332A3 Flip-flops, shift registers, and active-matrix display devices 审中-公开
标题翻译：触发器，移位寄存器和显示装置中，有源矩阵
公开(公告)号：EP1560332A3
公开(公告)日：2006-08-30
申请号：EP05250430.5
申请日：2005-01-27
申请人： SHARP KABUSHIKI KAISHA
发明人： Washio, Hajime , Murakami, Yuhichiroh , Brownlow, MIchael James
IPC分类号： H03K3/356
CPC分类号： H03K3/356165 , G09G3/3677 , G09G3/3688 , G11C19/00 , H03K3/012 , H03K3/356113 , H03K3/356147
摘要： A latch section includes a latch circuit. The latch circuit includes inverters and latches an input signal from a gating section. Between one of the inverters of the latch circuit and the output terminal OUT is disposed an analog switch whose ON/OFF characteristics are switched according to High/Low of a reset signal. Between the output terminal and an input for receiving a low potential as a power supply of a flip-flop is disposed a switching element whose ON/OFF characteristics are switched according to High/Low of the reset signal.

15. 发明公开

EP1560332A2 Flip-flops, shift registers, and active-matrix display devices 审中-公开
标题翻译：触发器，Schieberegister和Anzeigevorrichtungen mit aktiver矩阵
公开(公告)号：EP1560332A2
公开(公告)日：2005-08-03
申请号：EP05250430.5
申请日：2005-01-27
申请人： Sharp Kabushiki Kaisha
发明人： Washio, Hajime , Murakami, Yuhichiroh , Brownlow, MIchael James
IPC分类号： H03K3/356
CPC分类号： H03K3/356165 , G09G3/3677 , G09G3/3688 , G11C19/00 , H03K3/012 , H03K3/356113 , H03K3/356147
摘要： A latch section includes a latch circuit. The latch circuit includes inverters and latches an input signal from a gating section. Between one of the inverters of the latch circuit and the output terminal OUT is disposed an analog switch whose ON/OFF characteristics are switched according to High/Low of a reset signal. Between the output terminal and an input for receiving a low potential as a power supply of a flip-flop is disposed a switching element whose ON/OFF characteristics are switched according to High/Low of the reset signal.
摘要翻译：锁存部分包括锁存电路。锁存电路包括反相器并锁存来自门控部分的输入信号。在锁存电路的一个反相器和输出端子OUT之间配置有根据复位信号的高/低切换开/关特性的模拟开关。在输出端子和用于接收作为触发器的电源的低电位的输入端之间设置有根据复位信号的高/低切换开/关特性的开关元件。

16. 发明公开

EP1168365A3 Negative-voltage bias circuit 失效
标题翻译：电路，用于产生一负偏压
公开(公告)号：EP1168365A3
公开(公告)日：2004-09-29
申请号：EP01117838.1
申请日：1992-12-09
申请人： FUJITSU LIMITED
发明人： Akaogi, Takao , Kawashima, Hiromi , Takeguchi, Tetsuji , Hagiwara, Ryoji , Kasa, Yasushi , Itano, Kiyoshi , Kawamura, Shouichi , Ogawa, Yasushige c/o Fujitsu VLSI Ltd.,
IPC分类号： G11C16/06 , H03K19/21 , G11C5/14 , G11C16/30
CPC分类号： G11C29/82 , G05F3/205 , G11C5/145 , G11C16/0416 , G11C16/08 , G11C16/16 , G11C16/30 , H03K3/356147 , H03K3/356165 , H03K19/018521 , H03K19/215
摘要： A negative-voltage bias circuit is provided which comprises: a capacitor (550) having first and second terminals (550B, 550A) ; a first p-channel MIS field-effect transistor (551) whose drain is connected to a negative-voltage output terminal (554) and whose gate and source are connected to the first terminal (550B) of the capacitor (550); and a second p-channel MIS field-effect transistor (552) whose drain is connected to the source of the first p-channel MIS field effect transistor (551), whose gate is connected to the negative-voltage output terminal (554), and whose source is provided with a negative voltage (V BB ). The first p-channel MIS field-effect transistor (551) is a depletion-type p-channel MIS field-effect transistor. In operation of the circuit, application to the second terminal (550A) of a series of clock pulses (CLK) causes a potential of the negative-voltage output terminal (554) to tend towards the negative voltage (V BB ).

17. 发明授权

EP0905892B1 RS-Flip-Flop mit Enable-Eingängen 失效
标题翻译： RS触发器与使能输入
公开(公告)号：EP0905892B1
公开(公告)日：2002-10-02
申请号：EP98114223.5
申请日：1998-07-29
申请人： Infineon Technologies AG
发明人： Johnson, Bret , Schneider, Ralf
IPC分类号： H03K3/037
CPC分类号： H03K3/356113 , H03K3/037 , H03K3/356165

18. 发明授权

EP0961290B1 Flash memory with improved erasability and its circuitry 有权
标题翻译：闪存具有更好的可擦及其电路
公开(公告)号：EP0961290B1
公开(公告)日：2001-11-14
申请号：EP99115180.4
申请日：1992-12-09
申请人： FUJITSU LIMITED
发明人： Akaogi, Takao , Kawashima, Hiromi , Takeguchi, Tetsuji , Hagiwara, Ryoji , Kasa, Yasushi , Itano, Kiyoshi , Kawamura, Shouichi , Ogawa, Yasushige
IPC分类号： G11C16/06 , H03K19/21 , G11C5/14
CPC分类号： G11C29/82 , G05F3/205 , G11C5/145 , G11C16/0416 , G11C16/08 , G11C16/16 , G11C16/30 , H03K3/356147 , H03K3/356165 , H03K19/018521 , H03K19/215
摘要： A negative-voltage bias circuit is provided which comprises: a capacitor (550) having first and second terminals (550B, 550A) ; a first p-channel MIS field-effect transistor (551) whose drain is connected to a negative-voltage output terminal (554) and whose gate and source are connected to the first terminal (550B) of the capacitor (550); and a second p-channel MIS field-effect transistor (552) whose drain is connected to the source of the first p-channel MIS field effect transistor (551), whose gate is connected to the negative-voltage output terminal (554), and whose source is provided with a negative voltage (VBB). The first p-channel MIS field-effect transistor (551) is a depletion-type p-channel MIS field-effect transistor. In operation of the circuit, application to the second terminal (550A) of a series of clock pulses (CLK) causes a potential of the negative-voltage output terminal (554) to tend towards the negative voltage (VBB).

19. 发明公开

EP0926825A3 Static latch circuit and static logic circuit 审中-公开
标题翻译：静态锁存电路和静态逻辑电路
公开(公告)号：EP0926825A3
公开(公告)日：1999-08-04
申请号：EP98124596.2
申请日：1998-12-23
申请人： NEC CORPORATION
发明人： Kanno, Hiroshi
IPC分类号： H03K3/356 , H03K19/017
CPC分类号： H03K3/356165 , H03K19/0016
摘要： A static latch circuit and a static logic circuit can be easily designed without gate width and gate length optimization while using transistors with the smallest usable gate width to reduce power consumption. The resulting static latch circuit and static logic circuit can be used in applications where all gate lengths must be the same. The drive capacity of parts associated with the static holding function of the latch circuit and logic circuit is reduced by using a step-down circuit and step-up circuit to reduce the effective supply voltage during operation.
摘要翻译：在使用具有最小可用栅极宽度的晶体管来降低功耗的同时，可以容易地设计静态锁存电路和静态逻辑电路，而无需栅极宽度和栅极长度优化。得到的静态锁存电路和静态逻辑电路可用于所有门极长度必须相同的应用中。通过使用降压电路和升压电路来降低与锁存电路和逻辑电路的静态保持功能相关联的部件的驱动能力，以降低操作期间的有效供电电压。

20. 发明授权

EP0407591B1 DIFFERENTIAL AMPLIFIER CIRCUIT 失效
标题翻译：电路对差分放大器电路
公开(公告)号：EP0407591B1
公开(公告)日：1996-08-21
申请号：EP89911109.0
申请日：1989-10-06
申请人： Oki Electric Industry Co., Ltd.
发明人： MIYAMOTO, Sanpei Oki Electric Industry Co., Ltd. , UEHARA, Hidenori Oki Electric Industry Co., Ltd.
IPC分类号： H03K5/02 , H03K3/356 , G11C7/06
CPC分类号： H03K3/356165 , H03K3/356113 , H03K3/356147
摘要： A differential amplifier circuit that compares a potential difference between a first input (Ain) and a second input (Vr) to produce complementary output signals (A^¨B7, A). Potential drops of the output signals (A, A) are detected by fixing means that is constituted by n-channel FET's (33, 34) of which the drains are connected to nodes (N3, N4) of a flip-flop circuit (20) and of which the sources are connected to a second potential (Vss), and inverters (31, 32) of which the outputs are connected to the gates of the n-channel FET's (33, 34). Nodes (N3, N4) connected to nodes (N1, N2) that produce output signals (A, A^¨B7) are fixed to the second potential (Vss), in order to increase the speed of operation and to decrease the number of timing control signals (Ø).

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