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11. 发明公开

EP3104411A1 SEMICONDUCTOR MODULE 无效
标题翻译： HALBLEITERMODUL
公开(公告)号：EP3104411A1
公开(公告)日：2016-12-14
申请号：EP15819776.4
申请日：2015-04-28
申请人： Shindengen Electric Manufacturing Co., Ltd.
发明人： IKEDA, Kosuke
IPC分类号： H01L25/07 , H01L23/28 , H01L23/29 , H01L25/18
CPC分类号： H01L23/49537 , H01L23/3142 , H01L23/3675 , H01L23/49562 , H01L23/49568 , H01L25/071 , H01L25/074
摘要： Semiconductor module (100) has a first member (10), a second member (20), a conductor column (31) extending in the vertical direction between the first member (10) and the second member (20) and a sealing resin (80) covering a first conductor layer (12) and a first power device (13) of the first member (10), a second conductor layer (22) and a second power device (23) of the second member (20) and the conductor column (31). Positions of the first power device (13) and the second power device (23) on the horizontal plane are shifted, the second conductor layer (22) is not provided in the vertical direction from a first connection part (46) connected to the first power device (13), and the first conductor layer (12) is not provided in the vertical direction from a second connection part (56), connected to the second power device (23), of the second power device (23).
摘要翻译：半导体模块（100）具有第一构件（10），第二构件（20），在第一构件（10）和第二构件（20）之间沿垂直方向延伸的导体柱（31）和密封树脂覆盖第一构件（10）的第一导体层（12）和第一功率器件（13），第二构件（20）的第二导体层（22）和第二功率器件（23）导体柱（31）。第一动力装置（13）和第二动力装置（23）在水平面上的位置偏移，第二导体层（22）不从与第一动力装置（13）和第二动力装置（23）连接的第一连接部功率器件（13），并且第一导体层（12）不从与第二电力设备（23）连接的第二连接部分（56）的垂直方向设置。

12. 发明公开

EP2976380A4 DIENE/DIENOPHILE COUPLES AND THERMOSETTING RESIN COMPOSITIONS HAVING REWORKABILITY 审中-公开
标题翻译：二烯/ DIENOPHILPAARE和热固性树脂组合物再加工
公开(公告)号：EP2976380A4
公开(公告)日：2016-11-02
申请号：EP14767385
申请日：2014-03-21
申请人： HENKEL IP & HOLDING GMBH
发明人： CHAMPAGNE TIMOTHY M , SRIDHAR LAXMISHA M , ISRAEL JONATHAN B , KLEMARCZYK PHILIP T , ZHANG XIANMAN , JORDAN BENNY E
IPC分类号： C08J3/24 , C07C33/12 , C07C69/54 , C07C69/753 , C07D303/16 , C07D303/28 , C08F283/10 , C08F290/00 , C08G59/40 , C08K5/00 , C08K5/092 , C08L63/00 , C08L79/00 , C08L79/08 , C08L101/02 , C09J163/00 , C09J163/04 , H01L21/56 , H01L23/29 , H01L23/31 , H01L23/498
CPC分类号： C09J163/00 , C07C33/12 , C07C69/54 , C07C69/753 , C07C2603/68 , C07D303/16 , C07D303/28 , C08F283/10 , C08G59/226 , C08G59/24 , C08G59/4021 , C08G59/5073 , C08G59/56 , C08K5/092 , C08L63/00 , C08L79/085 , C09J163/04 , H01L21/563 , H01L23/293 , H01L23/3142 , H01L23/49838 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/15311 , H01L2924/00 , C08L53/02
摘要： Thermosetting resin compositions are provided that are useful for mounting onto a circuit board semiconductor devices, such as chip size or chip scale packages (“CSPs”), ball grid arrays (“BGAs”), land grid arrays (“LGAs”) and the like (collectively, “subcomponents”), or semiconductor chips. Reaction products of the compositions are controllably reworkable when subjected to appropriate conditions.

13. 发明公开

EP2924729A8 Electronic package and method of connecting a first die to a second die to form an electronic package 审中-公开
标题翻译：电子封装和连接在第二管芯上的第一管芯用于模制的电子封装的方法
公开(公告)号：EP2924729A8
公开(公告)日：2016-02-24
申请号：EP15155426.8
申请日：2015-02-17
申请人： Intel Corporation
发明人： Chase, Harold Ryan , Manusharow, Mathew J. , Roy, Mihir K.
IPC分类号： H01L23/538 , H01L25/065
CPC分类号： H01L25/0652 , H01L21/56 , H01L21/768 , H01L23/13 , H01L23/3142 , H01L23/3157 , H01L23/5226 , H01L23/5386 , H01L23/5389 , H01L24/19 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/04105 , H01L2224/16145 , H01L2224/16225 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/81005 , H01L2224/81203 , H01L2224/83005 , H01L2224/83855 , H01L2224/92125 , H01L2225/06541 , H01L2225/06548 , H01L2225/06555 , H01L2225/06572 , H01L2924/12042 , H01L2924/1433 , H01L2924/14335 , H01L2924/15153 , H01L2924/15192 , H01L2924/18162 , H05K1/183 , H05K1/186 , H01L2924/00
摘要： Some embodiments relate to an electronic package. The electronic package includes a substraten (11) that includes a plurality of buildup layers (12A,12B,12C). A first die (13) is embedded in one of the buildup layers on one side of the substrate. A second die(16) is bonded to the substrate within a cavity (17) on an opposing side of the substrate. The first die and the second die may be electrically connected to conductors within the plurality of buildup layers. Other embodiments relate to method of connecting a first die to a second die to form an electronic package. The method includes attaching a first die to a core and fabricating a substrate onto the core. The method further includes creating a cavity in another of the buildup layers on an opposing side of the substrate and attaching a second die to the substrate within the cavity.
摘要翻译：一些实施例涉及对电子封装。所述电子封装包括衬底（11）做了包括堆积层（12A，12B，12C）的复数。第一即（13）被嵌入在基板的一侧上的堆积层中的一个。第二，在（16）在相对的基板的侧面结合到上的空腔（17）内的基材。所述第一和第二所述的可电连接到导体堆积层的多元性内。其它实施例涉及的第一连接到第二所述的，以形成电子封装的方法。该方法包括：附接第一到一个芯和在芯上制造的衬底。该方法包括在相对的基板侧和将第二对所述腔内的基板形成空腔在另一个堆积层的进一步上。

14. 发明公开

EP2783229A1 MAGNETIC FIELD SENSOR DEVICE HAVING NON- CONDUCTIVE DIE PADDLE AND PRODUCTION METHOD 有权转让
标题翻译：随着对生产不会造成芯片板和工艺磁性传感器装置
公开(公告)号：EP2783229A1
公开(公告)日：2014-10-01
申请号：EP12809921.5
申请日：2012-12-11
申请人： Allegro Microsystems, LLC
发明人： MILANO, Shaun, D. , DOOGUE, Michael, C. , TAYLOR, William, P.
IPC分类号： G01R33/00 , H01L23/495
CPC分类号： H01L43/04 , G01R33/0029 , G01R33/0052 , G01R33/0076 , G01R33/07 , G01R33/09 , H01L23/3107 , H01L23/3142 , H01L23/49503 , H01L23/49506 , H01L23/49541 , H01L23/49575 , H01L24/17 , H01L43/02 , H01L43/06 , H01L43/065 , H01L43/08 , H01L43/12 , H01L43/14 , H01L2224/16 , H01L2224/16245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/4826 , H01L2224/49171 , H01L2224/73204 , H01L2224/73265 , H01L2924/15311 , H01L2924/15747 , H01L2924/181 , H01L2924/30107 , H01L2924/3025 , H01L2924/00014 , H01L2924/00
摘要： Methods and apparatus to provide an integrated circuit package having a conductive leadframe, a non-conductive die paddle mechanically coupled to the leadframe, and a die disposed on the die paddle and electrically connected to the leadframe. With this arrangement, eddy currents are reduced near the magnetic field transducer to reduce interference with magnetic fields.

15. 发明公开

EP2461357A3 Metal-resin composite, method for producing the same, busbar, module case, and resinous connector part 有权
标题翻译：金属树脂复合体，它们的制造方法中，汇流排模块外壳和树脂连接器
公开(公告)号：EP2461357A3
公开(公告)日：2012-11-28
申请号：EP11191289.5
申请日：2011-11-30
申请人： Hitachi, Ltd.
发明人： Kajiwara, Ryoichi , Motowaki, Shigehisa , Asaumi, Yusuke
IPC分类号： H01L21/56 , H01L23/29
CPC分类号： C23C16/56 , C22F1/10 , C22F1/165 , H01L21/56 , H01L23/049 , H01L23/24 , H01L23/296 , H01L23/3142 , H01L23/3735 , H01L2224/45124 , H01L2224/48091 , H01L2224/48472 , H01L2224/73265 , H01L2924/13055 , H01L2924/181 , H01L2924/19107 , H01L2924/30107 , Y10T428/12458 , Y10T428/12472 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： Provided are a metal-resin composite having excellent adhesive strength, a method for producing the same, a busbar, a module case, and a resinous connector part. The metal-resin composite comprises a metallic member 1 including a metal with a high melting point of 500°C or more, a resin member 2 being integrated with the metallic member 1; and an alloy layer 3 including a metal with a low melting point lower than 500°C. The alloy layer 3 is arranged between the metallic member 1 and the resin member 2, and has average surface roughness thereof in the range from 5nm or more to less than 1 µm at the interface between the alloy layer 3 and the resin member 2. Herein, a period of the unevenness formed on the interface of the alloy layer 3 is in the range from 5nm or more to less than 1 µm.

16. 发明授权

EP1188182B1 A METHOD OF ASSEMBLING A SEMICONDUCTOR DEVICE PACKAGE 有权
标题翻译：方法论罩，便于半导体布置编制
公开(公告)号：EP1188182B1
公开(公告)日：2012-08-22
申请号：EP99924092.2
申请日：1999-05-31
申请人： Infineon Technologies AG
发明人： LEE, Charles , STRACK, Helmut
IPC分类号： H01L21/48 , H01L21/50 , H01L23/48 , H01L23/28
CPC分类号： H01L23/3142 , H01L24/29 , H01L24/48 , H01L24/73 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2224/8592 , H01L2924/00014 , H01L2924/01006 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/15747 , H01L2924/181 , H01L2924/351 , H01L2924/3512 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599
摘要： A method of assembling a semiconductor device package includes first attaching a semiconductor device to a die-pad area of a leadframe. Electrical connections are then between electrical contact areas on the semiconductor device and electrical connection areas on the leadframe to form a device/leadframe assembly. An adhesion enhancing coating is then deposited on the exposed surface of the device frame/leadframe assembly before encapsulating the coated device leadframe assembly in an electrically insulating material.

17. 发明公开

EP2400534A1 Packaged semiconductor device having improved locking properties 审中-公开
标题翻译： Verpacktes Halbleiterbauelement mit动词dessertenen Verschlusseigenschaften
公开(公告)号：EP2400534A1
公开(公告)日：2011-12-28
申请号：EP10166815.0
申请日：2010-06-22
申请人： NXP B.V.
发明人： Van den Boomen, Rene , Van Kempen, Jan
IPC分类号： H01L21/56 , H01L23/31 , H01L21/48 , H01L23/00
CPC分类号： H01L21/56 , H01L21/4832 , H01L21/568 , H01L23/3107 , H01L23/3121 , H01L23/3142 , H01L23/49548 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L2224/274 , H01L2224/32057 , H01L2224/32245 , H01L2224/48247 , H01L2224/48257 , H01L2224/48471 , H01L2224/48479 , H01L2224/73265 , H01L2224/83191 , H01L2224/83385 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/0105 , H01L2924/01055 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15747 , H01L2924/181 , H01L2924/18301 , H05K3/3436 , H01L2924/00012 , H01L2924/00 , H01L2224/48227 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/4554
摘要： The invention relates to a method of manufacturing a semiconductor device (1), the method comprising: i) providing a substrate (10); ii) providing a photoresist layer (15) on the substrate (10), the photoresist layer (15) comprising an opening (16) having pre-shaped sidewalls (18); iii) filling the opening (16) with an electrically conductive material (20) for defining a contact pad (22) having further sidewalls (23, 26) corresponding with the pre-shaped sidewalls (18). The sidewalls (18) are pre-shaped such that the further sidewalls (23, 26) contained within the opening (16) are formed with a protrusion; iv) removing the photoresist layer (15); v) providing the semiconductor chip (100) and mounting said semiconductor chip (100) on the substrate (10) such that one terminal is electrically connected to the contact pad (22), and vi) providing a protective compound (30) covering the substrate (10) and the semiconductor chip (100) and at least the protrusion of at least one of the further sidewalls (23, 26) of the contact pad (22). The invention further relates to a semiconductor device (1) manufactured with such method. The semiconductor device (1) comprises: a) a contact pad (22) pre-shaped sidewalls (26); b) a semiconductor chip (100) having a terminal that is electrically connected to the contact pad (22), and c) a protective compound (30) covering the semiconductor chip (100) and at least part of the sidewalls (26). In a first embodiment the sidewall is rough and in a second embodiment the sidewall is tapered. The invention further relates to a PCB (200) comprising such semiconductor device (1). The invention facilitates better locking of the contact pad (22) into the compound (30).
摘要翻译：本发明涉及一种制造半导体器件（1）的方法，所述方法包括：i）提供衬底（10）; ii）在所述基底（10）上提供光致抗蚀剂层（15），所述光致抗蚀剂层（15）包括具有预成形侧壁（18）的开口（16）; iii）用导电材料（20）填充开口（16），用于限定具有与预成型侧壁（18）相对应的另外侧壁（23,26）的接触垫（22）。侧壁（18）被预成形，使得容纳在开口（16）内的另外的侧壁（23,26）形成有突起; iv）去除光致抗蚀剂层（15）; v）提供半导体芯片（100）并将所述半导体芯片（100）安装在所述基板（10）上，使得一个端子电连接到所述接触焊盘（22），以及vi）提供覆盖所述半导体芯片的保护化合物（30）衬底（10）和半导体芯片（100），并且至少接触焊盘（22）的至少一个另外的侧壁（23,26）的突起。本发明还涉及用这种方法制造的半导体器件（1）。半导体器件（1）包括：a）接触垫（22）预成形的侧壁（26）; b）具有电连接到接触焊盘（22）的端子的半导体芯片（100），以及c）覆盖半导体芯片（100）和至少一部分侧壁（26）的保护化合物（30）。在第一实施例中，侧壁是粗糙的，并且在第二实施例中，侧壁是锥形的。本发明还涉及包括这种半导体器件（1）的PCB（200）。本发明便于将接触垫（22）更好地锁定到化合物（30）中。

18. 发明公开

EP2235747A1 IN-SITU CAVITY INTEGRATED CIRCUIT PACKAGE 有权
标题翻译：具有在线谐振器集成SCHALTUNGSKAPSELUNG
公开(公告)号：EP2235747A1
公开(公告)日：2010-10-06
申请号：EP08869038.3
申请日：2008-11-10
申请人： Skyworks Solutions, Inc.
发明人： LIANG, Steve, X.
IPC分类号： H01L21/60 , H01L23/48
CPC分类号： H01L24/14 , B81B7/0077 , B81C2203/0109 , B81C2203/0118 , B81C2203/019 , H01L23/293 , H01L23/3121 , H01L23/3142 , H01L23/315 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/0401 , H01L2224/05144 , H01L2224/10135 , H01L2224/1134 , H01L2224/11462 , H01L2224/13082 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/16225 , H01L2224/16227 , H01L2224/81139 , H01L2224/8114 , H01L2224/81191 , H01L2224/81207 , H01L2224/814 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81464 , H01L2224/8183 , H01L2924/00013 , H01L2924/01029 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/1461 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H03H9/0523 , H03H9/059 , H01L2924/00014 , H01L2924/01014 , H01L2224/13099 , H01L2224/05099 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599 , H01L2924/00
摘要： A flip chip semiconductor packaging device and method that incorporates in situ formation of cavities underneath selected portions of a die during a flip chip die bonding process. A method of flip chip semiconductor component packaging includes providing a die having a first surface, forming a barrier on first surface of the die, the barrier at least partially surrounding a designated location on the first surface of the die, bonding the die to a substrate in a flip chip configuration, and flowing molding compound over the die and over at least a portion of the substrate. Bonding the die to the substrate includes causing contact between the barrier and the substrate such that flow of the molding compound is blocked by the barrier to provide a cavity between the die and the substrate, the cavity being proximate the designated location on the first surface of the die.

19. 发明公开

EP2100323A2 PLASTIC ELECTRONIC COMPONENT PACKAGE 审中-公开
标题翻译：塑料电子元件包装
公开(公告)号：EP2100323A2
公开(公告)日：2009-09-16
申请号：EP07853355.1
申请日：2007-12-12
申请人： Quantum Leap Packaging, Inc.
发明人： ZIMMERMAN, Michael A. , SMITH, Keith , SHVERDIN, Jacob
IPC分类号： H01L21/00
CPC分类号： H01L27/14618 , H01L23/10 , H01L23/3142 , H01L23/49861 , H01L24/48 , H01L27/14683 , H01L33/486 , H01L2224/48091 , H01L2224/48227 , H01L2224/4899 , H01L2924/00014 , H01L2924/01012 , H01L2924/0102 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/12041 , H01L2924/15747 , H01L2924/16195 , H01L2924/181 , H01L2924/3025 , Y10T428/12569 , Y10T428/12618 , Y10T428/31678 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A plastic package for an image sensor or other electronic component which comprises a plastic body, preferably of LCP material, molded around a leadframe and defining a cavity in which the image sensor is to be disposed. A lid assembly is provided having a transparent glass lid retained in a plastic lid frame which is weldable or otherwise bondable to the plastic body of the package to enclose the image sensor mounted in the cavity. The leadframe is usually composed of copper or a copper alloy, or a ferrous alloy having a copper coating. An interfacial layer is formed on the surfaces of the leadframe at least in those portions which are in contact with the plastic body which serves to provide substantially improved adhesion between the leadframe and the plastic material to achieve a hermetic bond between the metal and plastic materials. The interfacial layer is composed of a cuprous oxide base layer formed on a surface of the leadframe, and a cupric oxide layer formed on the cuprous oxide layer. The cupric oxide outer layer has an acicular structure which provides an interlocking mechanism for adhesion to the plastic material molded thereto in forming the package.
摘要翻译：一种用于图像传感器的塑料封装包括塑料主体，该塑料主体被模制在引线框周围并且限定图像传感器将被布置在其中的空腔。提供了一种盖组件，其具有保持在塑料盖框架中的透明玻璃盖，其可焊接或以其他方式可接合至包装的塑料本体以封闭安装在腔中的图像传感器。界面层形成在引线框的表面上，该引线框由在引线框表面上形成的氧化亚铜基底层和在氧化亚铜层上形成的氧化铜层组成。该卷曲氧化物外层具有针状结构，该结构在形成包装时提供用于粘附到模制于其上的塑料材料的互锁机构。

20. 发明公开

EP1914798A2 Semiconductor Mounting Substrate and Method for Manufacturing the Same 审中-公开
标题翻译： Halbleitermontagesubstrat和Verfahren zu seiner Herstellung
公开(公告)号：EP1914798A2
公开(公告)日：2008-04-23
申请号：EP07118576.3
申请日：2007-10-16
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD
发明人： Kimura, Junichi , Niimi, Hideki , Fuwa, Yuji , Sakaue, Tsuyoshi
IPC分类号： H01L21/56
CPC分类号： H01L21/563 , H01L23/3135 , H01L23/3142 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2924/00011 , H01L2924/00014 , H01L2924/19105 , H05K1/023 , H05K3/305 , H05K2201/10522 , H05K2201/10636 , H05K2201/10674 , H05K2201/10977 , Y02P70/611 , Y02P70/613 , H01L2924/00 , H01L2224/0401
摘要： A semiconductor mounting substrate according to the present invention comprises: a substrate; a semiconductor device, mounted on this substrate; solder bumps, which connect the semiconductor device and the substrate; a first resin, filled in a space between the semiconductor device and the substrate; and electronic components, mounted on a face side of the semiconductor device where the semiconductor device is mounted, wherein bond strength reinforcing resin section is provided at least between a side face in the vicinity of a corner part of the semiconductor device and a substrate surface of the substrate in a position corresponding to the corner part.
摘要翻译：根据本发明的半导体安装基板包括：基板; 安装在该基板上的半导体器件; 焊料凸块，其连接半导体器件和衬底; 填充在半导体器件和衬底之间的空间中的第一树脂; 以及安装在半导体装置的半导体装置的正面侧的电子部件，其中，接合强度增强树脂部至少设置在半导体装置的角部附近的侧面和所述基板处于与所述角部对应的位置。

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