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12. 发明公开

EP2482311A3 Semiconductor device, method of manufacturing semiconductor device, and electronic device 审中-公开
标题翻译：一种半导体装置，一种用于制造半导体器件的方法，和电子装置
公开(公告)号：EP2482311A3
公开(公告)日：2016-06-08
申请号：EP12150102.7
申请日：2012-01-03
申请人： Fujitsu Limited
发明人： Akamatsu, Toshiya
IPC分类号： H01L23/498 , H01L21/98 , H01L25/065 , H01L23/14 , H01L23/48 , H01L21/60
CPC分类号： H01L25/0657 , H01L21/76898 , H01L23/481 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/48 , H01L24/73 , H01L24/81 , H01L25/0652 , H01L25/50 , H01L29/0657 , H01L2224/02372 , H01L2224/0401 , H01L2224/05548 , H01L2224/05567 , H01L2224/05571 , H01L2224/05573 , H01L2224/05624 , H01L2224/11002 , H01L2224/1147 , H01L2224/13006 , H01L2224/13024 , H01L2224/13025 , H01L2224/13027 , H01L2224/1308 , H01L2224/13082 , H01L2224/131 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/14181 , H01L2224/16141 , H01L2224/16147 , H01L2224/16148 , H01L2224/16238 , H01L2224/1624 , H01L2224/1703 , H01L2224/17051 , H01L2224/17181 , H01L2224/45144 , H01L2224/48095 , H01L2224/48227 , H01L2224/48599 , H01L2224/73204 , H01L2224/73207 , H01L2224/73265 , H01L2224/81136 , H01L2224/8114 , H01L2224/81192 , H01L2224/81193 , H01L2224/81815 , H01L2224/81986 , H01L2224/83102 , H01L2224/9201 , H01L2224/94 , H01L2224/96 , H01L2225/0651 , H01L2225/06513 , H01L2225/06541 , H01L2225/06555 , H01L2225/06572 , H01L2225/06575 , H01L2924/00013 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/15159 , H01L2924/15321 , H01L2924/15787 , H01L2924/1579 , H01L2924/351 , H05K1/18 , H05K1/181 , H05K2201/09063 , H05K2201/1053 , H05K2201/10545 , H05K2201/10674 , H01L2224/13099 , H01L2224/11 , H01L2224/05099 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599 , H01L2224/81 , H01L2924/00012 , H01L2224/48624 , H01L2924/00 , H01L2224/05552 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device includes a semiconductor element (2) and an electronic element (3). The semiconductor element has a first protruding electrode (2a), and the electronic element has a second protruding electrode (3a). A substrate (4) is disposed between the semiconductor element (2) and the electronic element (3). The substrate has a through-hole (4a) in which the first and second protruding electrodes (2a, 3a) are fitted. The first and second protruding electrodes are connected together inside the through-hole (4a) of the substrate.

13. 发明公开

EP3026704A1 LIGHT-EMITTING DIODE DISPLAY SCREEN 审中-公开
标题翻译： LED-ANZEIGEBILDSCHIRM
公开(公告)号：EP3026704A1
公开(公告)日：2016-06-01
申请号：EP14829619.7
申请日：2014-07-14
申请人： Leyard Optoelectronic Co., Ltd
发明人： LU, Changjun , YU, Jie , LIU, Zhiyong , PAN, Tong
IPC分类号： H01L25/075 , H01L33/00
CPC分类号： H01L25/0753 , H01L25/167 , H01L33/483 , H01L33/62 , H01L2224/11
摘要： A Light Emitting Diode (LED) display screen includes: an LED display screen substrate (200), wherein the LED display screen substrate (200) is arranged with a driving circuit, an output end of the driving circuit includes: a first positive electrode (202) and a first negative electrode (204); an LED chip (210), located on the first surface,; a first jointing part (222) and a second jointing part (204), wherein the first positive electrode (202) is jointed to and electrically connected to the second positive electrode (212), and the first negative electrode (204) is jointed to and electrically connected to the second negative electrode (214) by the second jointing part (224). The LED display screen solves the technical problem in the related art that the minimum dot pitch of an LED display screen is excessively large due to a limited size of a support in a conventional encapsulated lamp bead.
摘要翻译：发光二极管（LED）显示屏包括：LED显示屏基板（200），其中所述LED显示屏基板（200）布置有驱动电路，所述驱动电路的输出端包括：第一正极（ 202）和第一负极（204）; 位于所述第一表面上的LED芯片（210）; 第一接合部（222）和第二接合部（204），其中，所述第一正极（202）与所述第二正极（212）接合并电连接，所述第一负极（204）被接合到并通过第二接合部（224）与第二负极（214）电连接。 LED显示屏解决了现有技术中的技术问题，由于传统封装的灯珠中的支撑体的尺寸有限，LED显示屏的最小点间距过大。

14. 发明公开

EP2840596A4 SOLDER BUMP AND FORMING METHOD THEREFOR, AND SUBSTRATE HAVING SOLDER BUMP AND MANUFACTURING METHOD FOR SUBSTRATE HAVING SOLDER BUMP 有权
标题翻译：颠簸和生产工艺和基质，用于与颠簸颠簸基底和方法
公开(公告)号：EP2840596A4
公开(公告)日：2016-04-27
申请号：EP12874866
申请日：2012-04-17
申请人： TANIGUROGUMI CORP
发明人： TANIGURO KATSUMORI
IPC分类号： H01L21/60 , B23K37/06 , H05K3/34
CPC分类号： B23K37/06 , H01L21/4853 , H01L23/49811 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/05026 , H01L2224/05147 , H01L2224/05571 , H01L2224/05647 , H01L2224/11312 , H01L2224/11472 , H01L2224/1181 , H01L2224/11821 , H01L2224/11849 , H01L2224/131 , H01L2224/13111 , H01L2224/13113 , H01L2224/13118 , H01L2224/1312 , H01L2224/13139 , H01L2224/13155 , H01L2224/16503 , H01L2224/94 , H01L2924/00014 , H05K3/282 , H05K3/3468 , H05K13/0465 , H05K2203/0557 , H05K2203/0746 , H05K2203/1344 , H01L2924/00012 , H01L2924/01028 , H01L2924/0105 , H01L2924/01047 , H01L2924/01029 , H01L2924/014 , H01L2924/0132 , H01L2224/11 , H01L2224/05552
摘要： Provided is a solder bump forming method capable of forming solder bumps having a desired constant thickness, without any failure such as copper corrosion, on a mounting board such as a printed circuit board having fine copper electrodes. The solder bump forming method includes: a process in which a prepared mask (5) is placed on a prepared substrate (1) and then a molten solder jet is blown to fill an opening of the mask (5) with molten solder (11a) until the molten solder (11a) exceeds the thickness of the mask (5); a process of removing a part of the molten solder (11a) that exceeds the thickness of the mask (5) to form a solder bump (11) having a predetermined thickness; and a process of removing the mask (5). The molten solder (11a) is molten lead-free solder that includes tin as a main ingredient and at least nickel as a sub ingredient, and further includes one or more other ingredients such as silver, copper, and germanium. The part of the molten solder (11a) that exceeds the thickness of the mask (5) is removed by using a blade or an air cutter or by spraying a solution (18) that includes organic fatty acid having 12 to 20 carbon atoms.
摘要翻译：本发明提供一种焊锡凸块形成装置，能够形成具有所期望的恒定的厚度的焊料凸块的方法，而没有任何故障：如铜腐蚀，在安装基板上：如具有微细铜电极的印刷电路板。焊料凸块形成方法，包括：在其中一个准备好的掩模（5）在（1），然后将熔融焊料射流被吹入以填充在与熔融焊剂（11A），所述掩模（5）的开口部的预备基板放置在处理直到熔融焊料（11A）超过掩模的厚度（5）; 除去熔融焊料（11）那样的一部分的过程超过所述掩模（5）的厚度，以形成具有预定厚度的焊料凸块（11）; 和去除所述掩模的工序（5）。熔融焊料（11）熔融的无铅焊料确实包括锡作为主要成分和至少镍作为副成分，并且进一步包括一种或多种其它成分：例如银，铜，和锗。熔融焊料（11）的部分确实超过了掩模（5）的厚度是通过使用刀片或切割器以空气或通过喷雾的溶液（18）中除去没有包括具有12至20个碳原子的有机脂肪酸。

15. 发明公开

EP2858112A4 METHOD FOR MANUFACTURING IMAGING DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：方法用于生产成像设备和方法的半导体元件
公开(公告)号：EP2858112A4
公开(公告)日：2016-04-13
申请号：EP13796999
申请日：2013-04-04
申请人： OLYMPUS CORP
发明人： FUJIMORI NORIYUKI , IGARASHI TAKATOSHI , YOSHIDA KAZUHIRO
IPC分类号： H01L27/14 , H01L21/786 , H01L23/12 , H01L23/29 , H01L23/31 , H01L27/146
CPC分类号： H01L25/50 , H01L21/78 , H01L21/786 , H01L22/10 , H01L22/20 , H01L23/3121 , H01L27/14618 , H01L27/14638 , H01L27/14687 , H01L2224/11 , H01L2924/0002 , H01L2924/00

16. 发明公开

EP2930742A2 Semiconductor device and electronic circuit device 审中-公开
标题翻译： Halbleitervorrichtung und elektronische Schaltvorrichtung
公开(公告)号：EP2930742A2
公开(公告)日：2015-10-14
申请号：EP15155779.0
申请日：2015-02-19
申请人： Kabushiki Kaisha Toshiba
发明人： Yamada, Hiroshi
IPC分类号： H01L21/60 , H01L23/34 , H01L23/538 , H01L23/433
CPC分类号： H01L23/5386 , H01L21/568 , H01L23/295 , H01L23/36 , H01L23/4334 , H01L23/49816 , H01L23/5389 , H01L24/19 , H01L24/96 , H01L25/0652 , H01L2224/0401 , H01L2224/04105 , H01L2224/05568 , H01L2224/0558 , H01L2224/05644 , H01L2224/05655 , H01L2224/05666 , H01L2224/12105 , H01L2224/13111 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13166 , H01L2224/13184 , H01L2224/1403 , H01L2224/14135 , H01L2224/16225 , H01L2224/24137 , H01L2224/24195 , H01L2224/32225 , H01L2224/73204 , H01L2224/94 , H01L2924/01029 , H01L2924/01047 , H01L2924/1424 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/0105 , H01L2924/00 , H01L2224/11
摘要： A semiconductor device according to an embodiment includes a first semiconductor unit including a plurality of first semiconductor chips (12a,12b), an organic resin (16) provided between the first semiconductor chips, a wiring layer (18) provided above the first semiconductor chips to electrically connect the first semiconductor chips to each other, and a plurality of connecting terminals (24) provided on an upper portion of the wiring layer and a second semiconductor unit (22) fixed to a wiring layer side of the first semiconductor unit, the second semiconductor unit fixed to a region sandwiched between the connecting terminals, the second semiconductor unit having a second semiconductor chip, the second semiconductor unit electrically connected to the first semiconductor unit.
摘要翻译：根据实施例的半导体器件包括：第一半导体单元，包括多个第一半导体芯片（12a，12b）;设置在第一半导体芯片之间的有机树脂（16），设置在第一半导体芯片将第一半导体芯片彼此电连接，以及设置在布线层的上部的多个连接端子（24）和固定到第一半导体单元的布线层侧的第二半导体单元（22），第二半导体单元固定到夹在所述连接端子之间的区域，所述第二半导体单元具有第二半导体芯片，所述第二半导体单元电连接到所述第一半导体单元。

17. 发明授权

EP2454752B1 SEMICONDUCTOR-ON-INSULATOR WITH BACKSIDE HEAT DISSIPATION 有权转让
标题翻译：背部散热的SOI
公开(公告)号：EP2454752B1
公开(公告)日：2015-09-09
申请号：EP10734619.9
申请日：2010-07-14
申请人： Silanna Semiconductor U.S.A., Inc.
发明人： NYGAARD, Paul A. , MOLIN, Stuart B. , STUBER, Michael A.
IPC分类号： H01L21/78 , H01L23/36 , H01L21/84 , H01L27/12 , H01L21/336 , H01L29/786 , H01L23/367
CPC分类号： H01L27/1207 , H01L21/76256 , H01L21/78 , H01L21/84 , H01L23/36 , H01L23/3677 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/11 , H01L24/13 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/80 , H01L24/83 , H01L24/94 , H01L27/1203 , H01L29/78603 , H01L29/78606 , H01L2221/6834 , H01L2221/6835 , H01L2221/68377 , H01L2224/03002 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/03464 , H01L2224/03845 , H01L2224/0401 , H01L2224/05572 , H01L2224/08225 , H01L2224/11002 , H01L2224/13022 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/16227 , H01L2224/29186 , H01L2224/29188 , H01L2224/2919 , H01L2224/32225 , H01L2224/48 , H01L2224/80006 , H01L2224/8022 , H01L2224/80801 , H01L2224/80894 , H01L2224/83005 , H01L2224/8322 , H01L2224/83801 , H01L2224/8385 , H01L2224/9202 , H01L2224/9212 , H01L2224/92142 , H01L2224/94 , H01L2924/00014 , H01L2924/1305 , H01L2924/14 , H01L2924/3011 , H01L2924/3511 , H01L2924/014 , H01L2224/11 , H01L2924/00 , H01L2924/053 , H01L2924/00012 , H01L2224/83 , H01L2224/80 , H01L2224/03 , H01L2224/45099
摘要： Embodiments of the present invention provide for the dissipation of heat from semiconductor-on-insulator (SOI) structures. In one embodiment, a method for fabricating an integrated circuit is disclosed. In a first step, active circuitry is formed in an active layer of a SOI wafer. In a second step, substrate material is removed from a substrate layer disposed on a back side of the SOI wafer. In a third step, insulator material is removed from the back side of the SOI wafer to form an excavated insulator region. In a fourth step, a thermal dissipation layer is deposited on said excavated insulator region. The thermal dissipation layer is thermally conductive and electrically insulating.

18. 发明公开

EP2868778A3 Plating bath and method 有权
标题翻译：电镀和程序
公开(公告)号：EP2868778A3
公开(公告)日：2015-08-12
申请号：EP14191883.9
申请日：2014-11-05
申请人： Rohm and Haas Electronic Materials LLC
发明人： Woertink, Julia , Qin, Yi , Prange, Jonathan D. , Lopez Montesinos, Pedro O.
IPC分类号： C25D7/12 , C25D3/32 , C25D3/60
CPC分类号： C25D3/32 , C25D3/60 , C25D7/123 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/94 , H01L2224/05611 , H01L2224/05655 , H01L2224/11462 , H01L2224/13082 , H01L2224/13083 , H01L2224/131 , H01L2224/13111 , H01L2224/13147 , H01L2224/13155 , H01L2224/94 , H05K3/3473 , H01L2924/00012 , H01L2924/00014 , H01L2224/11 , H01L2924/01047 , H01L2924/01079 , H01L2924/01029 , H01L2924/01083 , H01L2924/01049 , H01L2924/0103 , H01L2924/01051 , H01L2924/01025 , H01L2924/014 , H01L2924/01322 , H01L2924/01026
摘要： Tin electroplating baths having certain brightening agents and nonionic surfactants provide tin-containing solder deposits having good morphology, reduced void formation and improved within-die uniformity.

19. 发明公开

EP2761651A4 METHOD FOR HANDLING VERY THIN DEVICE WAFERS 失效
标题翻译：方法处理非常薄晶圆组件
公开(公告)号：EP2761651A4
公开(公告)日：2015-07-29
申请号：EP11873373
申请日：2011-09-30
申请人： INTEL CORP
发明人： LEE KEVIN J
IPC分类号： H01L21/60 , H01L21/56 , H01L21/683 , H01L21/768 , H01L23/485
CPC分类号： H01L24/11 , H01L21/6835 , H01L21/76898 , H01L23/5384 , H01L24/02 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L2221/68327 , H01L2221/6834 , H01L2221/6835 , H01L2221/68359 , H01L2221/68381 , H01L2224/0231 , H01L2224/0401 , H01L2224/05009 , H01L2224/05568 , H01L2224/05624 , H01L2224/05647 , H01L2224/06181 , H01L2224/11001 , H01L2224/1183 , H01L2224/1184 , H01L2224/11849 , H01L2224/13023 , H01L2224/13025 , H01L2224/13109 , H01L2224/13111 , H01L2224/13116 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/17181 , H01L2224/27003 , H01L2224/271 , H01L2224/27436 , H01L2224/27848 , H01L2224/2919 , H01L2224/73104 , H01L2224/81191 , H01L2224/81204 , H01L2224/81815 , H01L2224/83191 , H01L2224/83192 , H01L2224/83856 , H01L2224/83862 , H01L2224/92 , H01L2224/9202 , H01L2224/9211 , H01L2224/94 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/00014 , H01L2924/01026 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/013 , H01L2924/014 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/1461 , H01L2924/181 , H01L2924/3512 , H01L2924/00 , H01L2924/0105 , H01L2924/0665 , H01L2924/00012 , H01L2224/81 , H01L2224/83 , H01L2224/03 , H01L2224/05552 , H01L2224/11 , H01L2224/27 , H01L2224/11848 , H01L21/304
摘要： A structure and method of handling a device wafer during through-silicon via (TSV) processing are described in which a device wafer is bonded to a temporary support substrate with a permanent thermosetting material. Upon removal of the temporary support substrate a planar frontside bonding surface including a reflowed solder bump and the permanent thermosetting material is exposed.

20. 发明公开

EP2865006A1 INTEGRATED CIRCUIT PACKAGE HAVING OFFSET VIAS 审中-公开
标题翻译：具有偏移接触孔的集成电路封装
公开(公告)号：EP2865006A1
公开(公告)日：2015-04-29
申请号：EP13808814.1
申请日：2013-06-25
申请人： Advanced Micro Devices, Inc.
发明人： SU, Michael, Zhuoying , LEI, Fu , KUECHENMEISTER, Frank
IPC分类号： H01L23/528 , H01L21/768
CPC分类号： H01L23/3192 , H01L21/76804 , H01L23/562 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L2224/03462 , H01L2224/0401 , H01L2224/05558 , H01L2224/05572 , H01L2224/056 , H01L2224/0603 , H01L2224/06051 , H01L2224/06131 , H01L2224/06141 , H01L2224/11462 , H01L2224/11472 , H01L2224/11474 , H01L2224/1148 , H01L2224/13017 , H01L2224/13022 , H01L2224/13027 , H01L2224/13111 , H01L2224/13147 , H01L2224/1403 , H01L2224/14051 , H01L2224/14104 , H01L2224/14131 , H01L2224/16237 , H01L2224/73204 , H01L2224/81191 , H01L2224/81815 , H01L2224/94 , H01L2924/00014 , H01L2924/15311 , H01L2924/00012 , H01L2924/01047 , H01L2924/01029 , H01L2224/05552 , H01L2224/03 , H01L2224/11
摘要： Integrated circuit packages comprise vias, each of which extends from a pad in communication with an integrated circuit on a semiconductor chip through insulating material overlying the semiconductor chip to an attachment surface facing a substrate. The portion of each via proximate the attachment surface is laterally offset from the portion proximate the pad from which it extends in a direction away from the centre of the semiconductor chip. Metallic material received in the vias mechanically and electrically interconnects the semiconductor chip to the substrate.

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