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1. 发明公开

EP2865006A4 INTEGRATED CIRCUIT PACKAGE HAVING OFFSET VIAS 审中-公开
标题翻译：具有偏移接触孔的集成电路封装
公开(公告)号：EP2865006A4
公开(公告)日：2016-03-23
申请号：EP13808814
申请日：2013-06-25
申请人： ADVANCED MICRO DEVICES INC
发明人： SU MICHAEL ZHUOYING , LEI FU , KUECHENMEISTER FRANK
IPC分类号： H01L23/528 , H01L21/768 , H01L23/31 , H01L23/485
CPC分类号： H01L23/3192 , H01L21/76804 , H01L23/562 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L2224/03462 , H01L2224/0401 , H01L2224/05558 , H01L2224/05572 , H01L2224/056 , H01L2224/0603 , H01L2224/06051 , H01L2224/06131 , H01L2224/06141 , H01L2224/11462 , H01L2224/11472 , H01L2224/11474 , H01L2224/1148 , H01L2224/13017 , H01L2224/13022 , H01L2224/13027 , H01L2224/13111 , H01L2224/13147 , H01L2224/1403 , H01L2224/14051 , H01L2224/14104 , H01L2224/14131 , H01L2224/16237 , H01L2224/73204 , H01L2224/81191 , H01L2224/81815 , H01L2224/94 , H01L2924/00014 , H01L2924/15311 , H01L2924/00012 , H01L2924/01047 , H01L2924/01029 , H01L2224/05552 , H01L2224/03 , H01L2224/11
摘要： Integrated circuit packages comprise vias, each of which extends from a pad in communication with an integrated circuit on a semiconductor chip through insulating material overlying the semiconductor chip to an attachment surface facing a substrate. The portion of each via proximate the attachment surface is laterally offset from the portion proximate the pad from which it extends in a direction away from the center of the semiconductor chip. Metallic material received in the vias mechanically and electrically interconnects the semiconductor chip to the substrate.

2. 发明公开

EP3412122A1 OPEN-PASSIVATION BALL GRID ARRAY PADS 审中-公开
公开(公告)号：EP3412122A1
公开(公告)日：2018-12-12
申请号：EP16825661.8
申请日：2016-12-21
申请人： Qualcomm Incorporated
发明人： KIM, Daeik Daniel , VELEZ, Mario Francisco , YUN, Changhan Hobie , ZUO, Chengjie , BERDY, David Francis , KIM, Jonghae , MUDAKATTE, Niranjan Sunil
IPC分类号： H05K3/34 , H01L23/31 , H05K3/00 , H05K1/11 , H05K1/03
CPC分类号： H01L24/11 , H01L23/15 , H01L23/3171 , H01L23/3192 , H01L23/49816 , H01L24/14 , H01L2224/11003 , H01L2224/11005 , H01L2224/1148 , H01L2224/1405 , H01L2224/14104 , H01L2224/145 , H05K1/0306 , H05K1/111 , H05K3/0052 , H05K2201/0154 , H05K2201/0195 , H05K2201/09845 , Y02P70/611
摘要： A conductive bump assembly may include a passive substrate. The conductive bump assembly may also include a conductive bump pad supported by the passive substrate and surrounded by a first passivation layer opening. The conductive bump assembly may further include a second passivation layer opening on the passive substrate. The second passivation layer opening may be merged with the first passivation layer opening surrounding the conductive bump pad proximate an edge of the passive substrate. The conductive bump assembly may also include a conductive bump on the conductive bump pad.

3. 发明公开

EP2865006A1 INTEGRATED CIRCUIT PACKAGE HAVING OFFSET VIAS 审中-公开
标题翻译：具有偏移接触孔的集成电路封装
公开(公告)号：EP2865006A1
公开(公告)日：2015-04-29
申请号：EP13808814.1
申请日：2013-06-25
申请人： Advanced Micro Devices, Inc.
发明人： SU, Michael, Zhuoying , LEI, Fu , KUECHENMEISTER, Frank
IPC分类号： H01L23/528 , H01L21/768
CPC分类号： H01L23/3192 , H01L21/76804 , H01L23/562 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L2224/03462 , H01L2224/0401 , H01L2224/05558 , H01L2224/05572 , H01L2224/056 , H01L2224/0603 , H01L2224/06051 , H01L2224/06131 , H01L2224/06141 , H01L2224/11462 , H01L2224/11472 , H01L2224/11474 , H01L2224/1148 , H01L2224/13017 , H01L2224/13022 , H01L2224/13027 , H01L2224/13111 , H01L2224/13147 , H01L2224/1403 , H01L2224/14051 , H01L2224/14104 , H01L2224/14131 , H01L2224/16237 , H01L2224/73204 , H01L2224/81191 , H01L2224/81815 , H01L2224/94 , H01L2924/00014 , H01L2924/15311 , H01L2924/00012 , H01L2924/01047 , H01L2924/01029 , H01L2224/05552 , H01L2224/03 , H01L2224/11
摘要： Integrated circuit packages comprise vias, each of which extends from a pad in communication with an integrated circuit on a semiconductor chip through insulating material overlying the semiconductor chip to an attachment surface facing a substrate. The portion of each via proximate the attachment surface is laterally offset from the portion proximate the pad from which it extends in a direction away from the centre of the semiconductor chip. Metallic material received in the vias mechanically and electrically interconnects the semiconductor chip to the substrate.

4. 发明公开

EP1988573A3 Highly reliable low-cost structure for wafer-level ball grid array packaging 审中-公开
标题翻译：成本效益和在晶片级高度可靠的结构，用于球栅阵列封装
公开(公告)号：EP1988573A3
公开(公告)日：2012-10-17
申请号：EP08006073.4
申请日：2008-03-28
申请人： Broadcom Corporation
发明人： Kaufmann, Matthew V. , Teck, Yang Tan
IPC分类号： H01L23/485 , H01L23/00 , H01L23/31 , H01L23/50 , H01L23/525 , H01L21/60
CPC分类号： H01L24/10 , H01L23/3114 , H01L23/525 , H01L23/562 , H01L24/13 , H01L2224/05001 , H01L2224/05008 , H01L2224/05022 , H01L2224/05027 , H01L2224/051 , H01L2224/05569 , H01L2224/05572 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/13 , H01L2224/13099 , H01L2224/14104 , H01L2224/16 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/14 , H01L2924/00012 , H01L2924/00 , H01L2924/00014 , H01L2924/013
摘要： Methods, systems, and apparatuses for wafer-level integrated circuit (IC) packages are described. An IC package includes an IC chip (702a), an insulating layer (1502) on the IC chip, a plurality of vias (1504a), a plurality of routing interconnects (1506a), and a plurality of bump interconnects (1512a). The IC chip has a plurality of terminals configured in an array on a surface of the IC chip. A plurality of vias through the insulating layer provide access to the plurality of terminals. Each of the plurality of routing interconnects has a first portion (1508) and a second portion (1510). The first portion of each routing interconnect is in contact with a respective terminal (604) of the plurality of terminals though a respective via, and the second portion of each routing interconnect extends over the insulating layer. Each bump interconnect of the plurality of bump interconnects is connected to the second portion of a respective routing interconnect of the plurality of routing interconnects whereby the insulating layer provides stress absorption with regard to stress applied to bump interconnect (1512a).

5. 发明公开

EP3387674A1 CAPACITOR FORMED ON HEAVILY DOPED SUBSTRATE 审中-公开
公开(公告)号：EP3387674A1
公开(公告)日：2018-10-17
申请号：EP16819775.4
申请日：2016-12-07
申请人： Microchip Technology Incorporated
发明人： DIX, Greg , YACH, Randy L. , MAZZILLI, Francesco
IPC分类号： H01L23/522 , H01L23/00 , H01L49/02
CPC分类号： H01L28/60 , H01L21/31105 , H01L21/52 , H01L23/3142 , H01L23/48 , H01L23/5222 , H01L23/5223 , H01L24/03 , H01L24/05 , H01L24/10 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/42 , H01L24/48 , H01L24/81 , H01L24/83 , H01L24/85 , H01L25/0652 , H01L28/00 , H01L28/40 , H01L2224/0391 , H01L2224/0401 , H01L2224/04026 , H01L2224/04042 , H01L2224/13022 , H01L2224/131 , H01L2224/14104 , H01L2224/1412 , H01L2224/16145 , H01L2224/2929 , H01L2224/293 , H01L2224/32145 , H01L2224/48101 , H01L2224/48105 , H01L2224/48137 , H01L2224/49175 , H01L2224/73257 , H01L2224/73265 , H01L2224/81815 , H01L2224/8192 , H01L2924/00014 , H01L2924/1205 , H01L2224/45099 , H01L2924/014 , H01L2924/0665
摘要： The teachings of the present disclosure may be applied to the manufacture and design of capacitors. In some embodiments of these teachings, a capacitor may be formed on a heavily doped substrate. For example, a method for manufacturing a capacitor may include: depositing an oxide layer on a first side of a heavily doped substrate; depositing a first metal layer on the oxide layer; and depositing a second metal layer on a second side of the heavily doped substrate.

6. 发明公开

EP3361502A1 SEMICONDUCTOR PACKAGE WITH RIGID UNDER BUMP METALLURGY (UBM) STACK 有权转让
公开(公告)号：EP3361502A1
公开(公告)日：2018-08-15
申请号：EP18155510.3
申请日：2018-02-07
申请人： MediaTek Inc.
发明人： Yu, Ta-Jen , Chen, Chi-Yuan , Hsu, Wen-Sung
IPC分类号： H01L23/485 , H01L23/29
CPC分类号： H01L24/13 , H01L23/3192 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/14 , H01L2224/03462 , H01L2224/0401 , H01L2224/05022 , H01L2224/05027 , H01L2224/0508 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05552 , H01L2224/05554 , H01L2224/05555 , H01L2224/05559 , H01L2224/05572 , H01L2224/0558 , H01L2224/05582 , H01L2224/05647 , H01L2224/05666 , H01L2224/06051 , H01L2224/11462 , H01L2224/13007 , H01L2224/13012 , H01L2224/13013 , H01L2224/13014 , H01L2224/13027 , H01L2224/13083 , H01L2224/131 , H01L2224/13147 , H01L2224/13155 , H01L2224/13582 , H01L2224/13655 , H01L2224/14051 , H01L2224/14104 , H01L2924/00012 , H01L2924/00014 , H01L2924/014
摘要： The invention provides a semiconductor package. The semiconductor package includes a semiconductor die and a conductive pillar bump structure and a conductive plug. The semiconductor die has a die pad thereon. The conductive pillar bump structure is positioned overlying the die pad. The conductive pillar bump structure includes an under bump metallurgy (UBM) stack having a first diameter and a conductive plug on the UBM stack. The conductive plug has a second diameter that is different than the first diameter.

7. 发明公开

EP2393128A1 Method for manufacturing light-emitting device and light-emitting device manufactured by the same 审中-公开
标题翻译：制造发光器件的方法以及通过该方法制造的发光器件
公开(公告)号：EP2393128A1
公开(公告)日：2011-12-07
申请号：EP10178705.9
申请日：2010-09-23
申请人： Kabushiki Kaisha Toshiba
发明人： Akimoto, Yosuke , Togawa, Ryuichi , Kojima, Akihiro , Iduka, Miyuki , Sugizaki, Yoshiaki
IPC分类号： H01L33/00 , H01L33/44
CPC分类号： H01L33/0079 , H01L33/44 , H01L33/62 , H01L2224/11 , H01L2224/14104 , H01L2924/00012
摘要： A method for manufacturing a light-emitting device (110,111,120,130) is disclosed. The method includes removing a substrate (10) from a semiconductor layer (5). The semiconductor layer (5) is provided on a first main surface (10a) of the substrate (10). The semiconductor layer (5) includes a light-emitting layer (33). At least a top surface (5a) and side surfaces (5b) of the semiconductor layer (5) are covered with a first insulating film (13). A first electrode portion (14) and a second electrode portion (15) electrically continuous to the semiconductor layer (5) are provided. The first insulating film (13) is covered with a second insulating film (16). The removing is performed by irradiating the semiconductor layer (5) with laser light (LSR) from a side of a second main surface (10b) of the substrate (10). The second main surface (10b) is opposite to the first main surface (10a). Each of band-gap energy of the second insulating film (16) and band-gap energy of the semiconductor layer (5) are smaller than energy of the laser light (LSR). Also a light-emitting device is disclosed which can be produced using the method of manufacturing.
摘要翻译：一种用于制造发光器件（110111120130）方法是游离缺失盘。该方法包括除去半导体层（5）的衬底（10）。在半导体层（5）设置在基板（10）的第一主表面（10A）。在半导体层（5）包括发光层（33）。至少一个顶面（5a）和侧表面（5b）中的半导体层（5）覆盖有第一绝缘膜 - （13）。本发明提供一种第一电极部分（14）和第二电极部分（15）电连续的半导体层（5）。第一绝缘电影（13）覆盖有第二绝缘膜 - （16）。除去执行通过从基板（10）的第二主面（10b）的一侧照射激光（LSR）的半导体层（5）。第二主面（10b）的相对于该第一主面（10a）中。每个第二绝缘膜 - （16）和带隙能量的半导体层（5）的带隙能量的比激光光（LSR）的能量小。因此，一个发光装置是盘游离缺失可使用制造方法来制造。

8. 发明公开

EP1988573A2 Highly reliable low-cost structure for wafer-level ball grid array packaging 审中-公开
标题翻译： Kostengünstigeund sehrzuverlässigeStrukturfürBall-Grid-Array-Pakete auf Wafer-Ebene
公开(公告)号：EP1988573A2
公开(公告)日：2008-11-05
申请号：EP08006073.4
申请日：2008-03-28
申请人： Broadcom Corporation
发明人： Kaufmann, Matthew V. , Teck, Yang Tan
IPC分类号： H01L23/485 , H01L23/00 , H01L23/31 , H01L23/50
CPC分类号： H01L24/10 , H01L23/3114 , H01L23/525 , H01L23/562 , H01L24/13 , H01L2224/05001 , H01L2224/05008 , H01L2224/05022 , H01L2224/05027 , H01L2224/051 , H01L2224/05569 , H01L2224/05572 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/13 , H01L2224/13099 , H01L2224/14104 , H01L2224/16 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/14 , H01L2924/00012 , H01L2924/00 , H01L2924/00014 , H01L2924/013
摘要： Methods, systems, and apparatuses for wafer-level integrated circuit (IC) packages are described. An IC package includes an IC chip (702a), an insulating layer (1502) on the IC chip, a plurality of vias (1504a), a plurality of routing interconnects (1506a), and a plurality of bump interconnects (1512a). The IC chip has a plurality of terminals configured in an array on a surface of the IC chip. A plurality of vias through the insulating layer provide access to the plurality of terminals. Each of the plurality of routing interconnects has a first portion (1508) and a second portion (1510). The first portion of each routing interconnect is in contact with a respective terminal (604) of the plurality of terminals though a respective via, and the second portion of each routing interconnect extends over the insulating layer. Each bump interconnect of the plurality of bump interconnects is connected to the second portion of a respective routing interconnect of the plurality of routing interconnects whereby the insulating layer provides stress absorption with regard to stress applied to bump interconnect (1512a).
摘要翻译：描述了用于晶片级集成电路（IC）封装的方法，系统和装置。 IC封装包括IC芯片（702a），IC芯片上的绝缘层（1502），多个通孔（1504a），多个路由互连（1506a）和多个凸块互连（1512a）。 IC芯片具有在IC芯片的表面上配置成阵列的多个端子。通过绝缘层的多个通孔提供对多个端子的访问。多个路由互连中的每一个具有第一部分（1508）和第二部分（1510）。每个路由互连的第一部分通过相应的通孔与多个终端中的相应终端（604）接触，并且每个路由互连的第二部分在绝缘层上延伸。多个凸块互连的每个凸起互连连接到多个路由互连的相应路由互连的第二部分，由此绝缘层提供关于施加到凸块互连（1512a）的应力的应力吸收。

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