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11. 发明授权

EP1641958B1 METHODS OF FORMING A PHOSPHORUS DOPED SILICON DIOXIDE LAYER 有权
标题翻译：法形成的荧光体掺杂的二氧化硅的
公开(公告)号：EP1641958B1
公开(公告)日：2008-09-17
申请号：EP04777377.5
申请日：2004-06-30
申请人： Micron Technology, Inc.
发明人： VAARTSTRA, Brian, A.
IPC分类号： C23C16/40
CPC分类号： C23C16/45531 , C23C16/045 , C23C16/401 , C23C16/402 , H01L21/02129 , H01L21/02216 , H01L21/02271 , H01L21/0228 , H01L21/31625 , H01L21/76227
摘要： This invention includes methods of forming a phosphorus doped silicon dioxide comprising layers, and methods of forming trench isolation in the fabrication of integrated circuitry. In one implementation, a method of forming a phosphorus doped silicon dioxide comprising layer includes positioning a substrate within a deposition chamber. First and second vapor phase reactants are introduced in alternate and temporally separated pulses to the substrate within the chamber in a plurality of deposition cycles under conditions effective to deposit a phosphorus doped silicon dioxide comprising layer on the substrate. One of the first and second vapor phase reactants is PO(OR)3 where R is hydrocarbyl, and an other of the first and second vapor phase reactants is Si(OR)3OH where R is hydrocarbyl.

12. 发明公开

EP1596432A1 Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：EP1596432A1
公开(公告)日：2005-11-16
申请号：EP05009851.6
申请日：2005-05-04
申请人： SONY CORPORATION
发明人： Nagaoka, Kohjiro Sony Corp.
IPC分类号： H01L21/762
CPC分类号： H01L21/76227 , H01L21/76224
摘要： In order to improve embeddability of an embedded insulating film to a filling portion to have a preferable embedded structure, the present invention provides a semiconductor device having an embedded structure in which an embedded insulating film is embedded in a filling portion formed in or on a substrate. The embedded structure includes an underlying insulating film containing a silicon nitride film formed on an inner wall of the filling portion by a chemical vapor deposition method using material gas containing hexachlorodisilane, and an embedded insulating film formed by filling in the filling portion via the underlying insulating film.
摘要翻译：为了提高嵌入绝缘膜对填充部分的嵌入性以具有优选的嵌入结构，本发明提供了一种具有嵌入结构的半导体器件，其中嵌入绝缘膜嵌入在衬底中或衬底上形成的填充部分中。嵌入结构包括下面的绝缘膜和嵌入的绝缘膜，该绝缘膜包含通过化学气相沉积方法在填充部分的内壁上形成的氮化硅膜，该绝缘膜通过经由下面的绝缘体填充填充部分而形成电影。

13. 发明公开

EP0507596A2 A method for forming planarized shallow trench isolation in an integrated circuit and a structure formed thereby 失效
标题翻译：一种用于浅隔离区和由该方法生产的集成电路结构的制备方法。
公开(公告)号：EP0507596A2
公开(公告)日：1992-10-07
申请号：EP92302941.7
申请日：1992-04-03
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Liou, Fu-Tai , Chen, Fusen E.
IPC分类号： H01L21/76
CPC分类号： H01L21/76227
摘要： A method for forming isolation structures in an integrated circuit, and the structures so formed, are disclosed. After definition of active regions of the surface is accomplished by provision of masking layers, recesses are etched into the exposed locations, to a depth on the order of the final thickness of the insulating isolation structure. Sidewall spacers of silicon dioxide, or another insulating amorphous material, are disposed along the sidewalls of the recesses, with silicon at the bottom of the recesses exposed. Selective epitaxial growth of silicon then forms a layer of silicon within the recesses, preferably to a thickness on the order of half of the depth of the recess. The epitaxial silicon is thermally oxidized, filling the recesses with thermal silicon dioxide, having a top surface which is substantially coplanar with the active regions of the surface. According to an alternative embodiment, the formation of the sidewall spacers may be done in such a manner that narrower recesses remain filled with the material of the sidewall spacers.
摘要翻译：一种用于在集成电路中形成隔离结构的方法，并且这些结构这样形成，是游离缺失盘。表面的有源区的定义是由规定的掩模层的完成之后，凹部被蚀刻到暴露的位置，至深度绝缘隔离结构的最终厚度的数量级上。二氧化硅，或其它绝缘无定形材料的侧壁间隔物，在露出的凹部的底面沿所述凹部的侧壁安置，有硅。硅的选择性外延生长然后形成凹部内的硅的层，优选地为厚度的凹部的深度的一半的量级。外延硅热氧化，填充热二氧化硅凹部，具有一顶表面的所有其与表面的有源区域基本共面。。据的替代实施例中，侧壁间隔物的形成可以以这样的方式搜索来完成做窄的凹部保持充满侧壁间隔件的材料。

14. 发明授权

EP0015677B1 Method of producing semiconductor devices 失效
标题翻译：生产半导体器件的方法
公开(公告)号：EP0015677B1
公开(公告)日：1983-10-19
申请号：EP80300454.8
申请日：1980-02-15
申请人： VLSI TECHNOLOGY RESEARCH ASSOCIATION
发明人： Togei, Ryoiku
IPC分类号： H01L21/76 , H01L21/268 , H01L21/31 , H01L21/86
CPC分类号： H01L21/76227 , H01L21/02381 , H01L21/02532 , H01L21/02675 , H01L21/268 , H01L21/321 , Y10S148/093

15. 发明公开

EP0061855A1 Method for manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：EP0061855A1
公开(公告)日：1982-10-06
申请号：EP82301254.7
申请日：1982-03-11
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Sasaki, Yoshitaka
IPC分类号： H01L21/76
CPC分类号： H01L21/32 , H01L21/321 , H01L21/76205 , H01L21/76208 , H01L21/76224 , H01L21/76227 , Y10S438/944
摘要： Disclosed is a method for manufacturing a semiconductor device of high reliability, high performance and high integration with high yield. The method of this invention has the steps of forming at least one groove (24) in a semiconductor substrate (21 forming a non-single-crystalline semiconductor film (28) to cover an entire surface of the semiconductor substrate (21) including an inner surface of the groove (24), selectively etching the non-single-crystalline semiconductor film (28) so as to leave the non-single-crystalline semiconductor film (28) on at least a side wall of the groove (24), and forming an oxide isolation layer (32) in the groove (24) by thermal oxidation.
摘要翻译：公开了一种高可靠性，高性能和高集成度且高成品率的半导体器件的制造方法。本发明的方法具有以下步骤：在形成非单晶半导体膜（28）的半导体衬底（21）中形成至少一个凹槽（24）以覆盖半导体衬底（21）的整个表面，所述半导体衬底（24）的表面，选择性地蚀刻非单晶半导体膜（28），以便在槽（24）的至少一个侧壁上留下非单晶半导体膜（28），以及通过热氧化在沟槽（24）中形成氧化物隔离层（32）。

16. 发明公开

EP0054659A1 Method for forming dielectric isolation regions in a monocrystalline silicon substrate 失效
标题翻译：一种用于在单晶硅衬底的制造介电隔离区的方法。
公开(公告)号：EP0054659A1
公开(公告)日：1982-06-30
申请号：EP81108546.3
申请日：1981-10-20
申请人： International Business Machines Corporation
发明人： Riseman, Jacob
IPC分类号： H01L21/76
CPC分类号： H01L21/76227
摘要： Dielectric isolation regions are formed in a monocrystalline silicon substrate (10) through forming trenches (20) in the substrate (10) by reactive ion etching after having etched openings in a layered structure (14, 15) of silicon dioxide and silicon nitride on the surface of the substrate (10). The substantially vertical side walls (21) of the trenches (20) in the substrate (10) are oxidized prior to depositing polycrystalline silicon on the side walls as a whole. By selective doping of the portion (27) of the polycrystalline silicon on the side walls of the openings in the layered structure (14, 15), the polycrystalline silicon on the side walls of the openings in the layered structure (14, 15) will oxidize at least twice as fast as the polycrystalline silicon (26) on the side walls (21) in the substrate (10). Thermal oxidation causes the polycrystalline silicon to close the upper end of each of the trenches (20) while leaving an air space (29) therebeneath to form the dielectric isolation regions.

17. 发明公开

EP1978548A4 PROCESS FOR PRODUCING SILICEOUS FILM AND SUBSTRATE WITH SILICEOUS FILM PRODUCED THEREBY 有权转让
标题翻译：用于生产硅膜和衬底，生产SILIZIUMOXIDHALTIGEM FILM THIS WAY
公开(公告)号：EP1978548A4
公开(公告)日：2011-11-23
申请号：EP07713624
申请日：2007-01-17
申请人： AZ ELECTRONIC MATERIALS JAPAN , AZ ELECTRONIC MATERIALS USA
发明人： ISHIKAWA TOMONORI , NAKAGUMA TERUNO
IPC分类号： H01L21/316 , C23C16/56 , H01L21/312 , H01L21/762
CPC分类号： H01L21/76227 , C23C16/56 , H01L21/02164 , H01L21/02222 , H01L21/02282 , H01L21/02304 , H01L21/02337 , H01L21/3125 , H01L21/316

18. 发明公开

EP1978548A1 PROCESS FOR PRODUCING SILICEOUS FILM AND SUBSTRATE WITH SILICEOUS FILM PRODUCED THEREBY 有权转让
标题翻译： VERFAHREN ZUR HERSTELLUNG EINES SILIZIUMOXIDHALTIGEN FILMS
公开(公告)号：EP1978548A1
公开(公告)日：2008-10-08
申请号：EP07713624.0
申请日：2007-01-17
申请人： AZ Electronic Materials (Japan) K.K. , AZ Electronic Materials USA Corp.
发明人： ISHIKAWA, Tomonori , NAKAGUMA, Teruno
IPC分类号： H01L21/316 , C23C16/40 , H01L21/76
CPC分类号： H01L21/76227 , C23C16/56 , H01L21/02164 , H01L21/02222 , H01L21/02282 , H01L21/02304 , H01L21/02337 , H01L21/3125 , H01L21/316
摘要： An objective of the present invention is to provide a process for producing a siliceous film which has a uniform quality independently of sites and in both the inside and outside of the grooves and is free from voids and cracks in the inside of the grooves. A substrate with the siliceous film can be produced by forming an insulating film having a high hydrogen content on a surface of a silicon substrate having concavoconvexes, then coating a composition containing a polysilazane compound on the substrate, and heating the coated substrate to convert the polysilazane compound to a silicon dioxide film.
摘要翻译：本发明的目的在于提供一种无缝地均匀地形成均匀的硅质膜的方法，并且在槽的内部和外部均不产生空隙和裂纹。具有硅质膜的基板可以通过在具有凹凸的硅基板的表面上形成具有高氢含量的绝缘膜，然后在基板上涂布含有聚硅氮烷化合物的组合物，并加热涂覆的基板以将聚硅氮烷与二氧化硅膜复合。

19. 发明公开

EP1665340A2 FORMATION OF A SILICON GERMANIUM-ON-INSULATOR STRUCTURE BY OXIDATION OF A BURIED POROUS SILICON LAYER 有权
标题翻译：形成硅 - 锗ON-绝缘体结构BY氧化掩埋多孔硅层的
公开(公告)号：EP1665340A2
公开(公告)日：2006-06-07
申请号：EP04809708.3
申请日：2004-09-10
申请人： International Business Machines Corporation
发明人： BEDELL, Stephen, W. , CHOE, Kwang Su , FOGEL, Keith, F. , SADANA, Devendra, K.
IPC分类号： H01L21/00
CPC分类号： H01L21/76227 , C22F1/10 , H01L21/02378 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02667 , H01L21/76245 , H01L29/78603
摘要： A simple and direct method of forming a SiGe-on-insulator that relies on the oxidation of a porous silicon layer (or region) that is created beneath a Ge-containing layer is provided. The method includes the steps of providing a structure comprising a Si-containing substrate having a hole-rich region formed therein and a Ge-containing layer atop the Si-containing substrate; converting the hole-rich region into a porous region; and annealing the structure including the porous region to provide a substantially relaxed SiGe-on-insulator material.

20. 发明授权

EP0716442B1 Integrated circuit fabrication utilizing LOCOS process 失效
标题翻译：通过LOCOS方法的装置的集成电路的制造
公开(公告)号：EP0716442B1
公开(公告)日：2001-10-17
申请号：EP95308768.1
申请日：1995-12-05
申请人： AT&T Corp.
发明人： Lee, Kuo-Hua , Yu, Chen-Hua Douglas
IPC分类号： H01L21/76
CPC分类号： H01L21/76264 , H01L21/76227 , H01L21/76281

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