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11. 发明公开

EP2648234A4 LIGHT RECEIVING ELEMENT, SEMICONDUCTOR EPITAXIAL WAFER, METHOD FOR MANUFACTURING THE LIGHT RECEIVING ELEMENT AND THE SEMICONDUCTOR EPITAXIAL WAFER, AND DETECTING APPARATUS 审中-公开
公开(公告)号：EP2648234A4
公开(公告)日：2018-01-03
申请号：EP11844996
申请日：2011-11-29
申请人： SUMITOMO ELECTRIC INDUSTRIES
发明人： MIURA KOHEI , INADA HIROSHI , IGUCHI YASUHIRO , SAITO TADASHI
IPC分类号： H01L31/10 , H01L21/02 , H01L21/205 , H01L27/146 , H01L31/0304
CPC分类号： H01L31/109 , B82Y20/00 , H01L21/02392 , H01L21/02463 , H01L21/02466 , H01L21/02505 , H01L21/02546 , H01L21/02549 , H01L27/1446 , H01L27/1464 , H01L31/0304 , H01L31/035236 , H01L31/075 , H01L31/105 , H01L31/184 , Y02E10/544 , Y02E10/548 , Y02P70/521
摘要： A light receiving element includes an InP substrate that is transparent to light having a wavelength of 3 to 12 µm, a buffer layer located in contact with the InP substrate, and a light-receiving layer having a multiple quantum well structure, the light-receiving layer having a cutoff wavelength of 3 µm or more and being lattice-matched with the buffer layer. In the light receiving element, the buffer layer is epitaxially grown on the InP substrate while the buffer layer and the InP substrate exceed a range of a normal lattice-matching condition, and the buffer layer is constituted by a GaSb layer.

12. 发明公开

EP3036770A1 HIGH RESISTANCE LAYER FOR III-V CHANNEL DEPOSITED ON GROUP IV SUBSTRATES FOR MOS TRANSISTORS 有权
标题翻译：用于MOS晶体管的第IV族衬底上III-V沟道的高电阻层
公开(公告)号：EP3036770A1
公开(公告)日：2016-06-29
申请号：EP13891735.6
申请日：2013-08-23
申请人： Intel Corporation
发明人： GLASS, Glenn A. , MURTHY, Anand S.
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/205 , H01L21/02241 , H01L21/02247 , H01L21/02373 , H01L21/02461 , H01L21/02463 , H01L21/02466 , H01L21/02546 , H01L21/02549 , H01L21/0262 , H01L21/30604 , H01L21/30612 , H01L21/7605 , H01L21/76224 , H01L21/76232 , H01L21/76264 , H01L27/0255 , H01L29/0653 , H01L29/0673 , H01L29/1033 , H01L29/1054 , H01L29/1079 , H01L29/1083 , H01L29/165 , H01L29/267 , H01L29/66522 , H01L29/66795 , H01L29/78 , H01L29/7848 , H01L29/785
摘要： Techniques are disclosed for using a high resistance layer between a III-V channel layer and a group IV substrate for semiconducting devices, such as metal-oxide-semiconductor (MOS) transistors. The high resistance layer can be used to minimize (or eliminate) current flow from source to drain that follows a path other than directly through the channel. In some cases, the high resistance layer may be a III-V wide bandgap layer. In some such cases, the wide bandgap layer may have a bandgap greater than 1.4 electron volts (eV), and may even have a bandgap greater than 2.0 eV. In other cases, the wide bandgap layer may be partially or completely converted to an insulator through oxidation or nitridation, for example. The resulting structures may be used with planar, finned, or nanowire/nanoribbon transistor architectures to help prevent substrate leakage problems.
摘要翻译：公开了在半导体器件如金属氧化物半导体（MOS）晶体管的III-V沟道层和IV族衬底之间使用高电阻层的技术。高电阻层可以用于最小化（或消除）从源极流到漏极的电流，该电流遵循除了直接通过通道之外的路径。在一些情况下，高电阻层可以是III-V宽带隙层。在一些这样的情况下，宽带隙层可以具有大于1.4电子伏特（eV）的带隙，并且甚至可以具有大于2.0eV的带隙。在其他情况下，例如，宽带隙层可以通过氧化或氮化而部分或完全转化为绝缘体。所得到的结构可以与平面，翅片或纳米线/纳米带晶体管架构一起使用，以帮助防止衬底泄漏问题。

13. 发明公开

EP2461374A4 SEMICONDUCTOR ELEMENT AND METHOD FOR MANUFACTURING SAME 审中-公开
公开(公告)号：EP2461374A4
公开(公告)日：2015-12-30
申请号：EP10806309
申请日：2010-07-07
申请人： SUMITOMO ELECTRIC INDUSTRIES
发明人： FUJII KEI , ISHIZUKA TAKASHI , AKITA KATSUSHI , NAGAI YOUICHI , TANABE TATSUYA
IPC分类号： H01L21/20 , H01L31/105 , H01L31/18
CPC分类号： H01L31/035236 , B82Y20/00 , H01L21/02392 , H01L21/02463 , H01L21/02466 , H01L21/02507 , H01L21/02546 , H01L21/02549 , H01L21/0262 , H01L31/1035 , H01L31/109 , H01L31/1844 , Y02E10/544 , Y02P70/521

14. 发明公开

EP2732459A1 MONOLITHISCHE INTEGRIERTE HALBLEITERSTRUKTUR 无效
标题翻译：单一组合HALBLEITERSTRUKTUR
公开(公告)号：EP2732459A1
公开(公告)日：2014-05-21
申请号：EP12740874.8
申请日：2012-04-25
申请人： NASP III/V GmbH
发明人： KUNERT, Bernadette
IPC分类号： H01L21/02
CPC分类号： H01L29/205 , H01L21/02381 , H01L21/02458 , H01L21/02461 , H01L21/02463 , H01L21/02466 , H01L21/02505 , H01L21/02538 , H01L21/0262
摘要： The invention relates to a monolithic integrated semiconductor structure containing the following layer structure: A) a substrate layer based on doped or undoped Si; B) optionally a layer having the composition B
x Al
y Ga
z N
t P
v, wherein x=0-0.1, y=0-1, z=0-1, t=0-0.1, and v=0.9-1; C) a relaxation layer having the composition B
x Al
y Ga
z In
u P
v Sb
w , wherein x=0-0.1, y=0-1, z=0-1, u=0-1, v=0-1, and w=0-1, wherein w and/or u on the side facing layer A) or B) are/is less than, equal to or greater than on the side facing away from layer A) or B), and wherein v=1-w and/or y=1-u-x-z; D) optionally a layer for blocking misfit dislocations having the composition B
x Al
y Ga
z In
u P
v Sb
w N
t , wherein x=0-0.1, y=0-1, z=0-1, u=0-1, v=0-1, w=0-1 and t=0-0.1; E) optionally a layer for the hetero offset having the composition B
x Al
y Ga
z In
u P
v Sb
w N
t As
r , wherein x=0-0.1, y=0-1, z=0-1, u=0-1, v=0-1, w=0-1, t=0-0.1 and r=0-1; and F) an arbitrary, preferably group III/V, semiconductor material, or a combination of several different arbitrary semiconductor materials, wherein the above stoichiometric indices for all group III elements always result in 1 in sum, and wherein the above stoichiometric indices for all group V elements likewise always result in 1 in sum.
摘要翻译：单片集成半导体结构包括：A）Si载体层，B）具有组成BxAlyGazNtPv的层，其中x = 0-0.1，y = 0-1，z = 0-1，t = 0-0.1，v = 0.9-1，C）具有组成BxAlyGazInuPvSbw的松弛层，其中x = 0-0.1，y = 0-1，z = 0-1，u = 0-1，v = 0-1，w = 0-1 其中w和/或u位于面向层A）或B）小于，等于或大于在背离层A）或B）的一侧上的侧面，并且其中v = 1-w和/或 y = 1-u-x-z，D）III / V族半导体材料。所有III族元素和所有V族元素的上述化学计量指数的总和均等于1。

15. 发明公开

EP2427921A1 SEMICONDUCTOR DEVICES GROWN ON INDIUM-CONTAINING SUBSTRATES UTILIZING INDIUM DEPLETION MECHANISMS 审中-公开
标题翻译：使用铟消耗机制在含铟衬底上生长的半导体器件
公开(公告)号：EP2427921A1
公开(公告)日：2012-03-14
申请号：EP10719829.3
申请日：2010-04-30
申请人： 3M Innovative Properties Company
发明人： MILLER, Thomas J., , HAASE, Michael A., , SUN, Xiaoguang,
IPC分类号： H01L33/00 , H01L21/02 , H01L33/50 , H01L33/28
CPC分类号： H01L33/0087 , H01L21/02392 , H01L21/02463 , H01L21/02466 , H01L21/02469 , H01L21/0256 , H01L21/02568 , H01L21/02576 , H01L21/02631 , H01L33/08 , H01L33/28 , H01L33/502
摘要： We have observed anomalous behavior of II-VI semiconductor devices grown on certain semiconductor substrates, and have determined that the anomalous behavior is likely the result of indium atoms from the substrate migrating into the II-VI layers during growth. The indium can thus become an unintended dopant in one or more of the II-VI layers grown on the substrate, particularly layers that are close to the growth substrate, and can detrimentally impact device performance. We describe a variety of semiconductor constructions and techniques effective to deplete the migrating indium within a short distance in the growth layers, or to substantially prevent indium from migrating out of the substrate, or to otherwise substantially isolate functional II-VI layers from the migrating indium, so as to maintain good device performance.
摘要翻译：我们观察到在某些半导体衬底上生长的II-VI半导体器件的异常行为，并且已经确定异常行为可能是由衬底中的铟原子在生长期间迁移到II-VI层中导致的。因此，铟可能成为在衬底上生长的一个或多个II-VI层中的无意的掺杂剂，特别是靠近生长衬底的层，并且可能不利地影响器件性能。我们描述了各种半导体构造和技术，有效地消除生长层中短距离内的迁移铟，或者基本上防止铟迁移出衬底，或者以其他方式将迁移的铟中的功能II-VI层基本上分离，以保持良好的器件性能。

16. 发明公开

EP1168466A3 Method for manufacturing semiconductors thin film, and magnetoelectric conversion element provided with semiconductor thin film thereby manufactured 有权
标题翻译：一种用于制备半导体薄膜工艺，并且磁电转换元件具有这样的薄膜
公开(公告)号：EP1168466A3
公开(公告)日：2006-01-04
申请号：EP01114662.8
申请日：2001-06-19
申请人： MURATA MANUFACTURING CO., LTD.
发明人： Ueda, Masaya, (A170)Intellectual Property Dept. , Sato, Tomoharu, (A170)Intellectual Property Dept. , Nishikawa, Masanaga, (170)Intell. Property Dept.
IPC分类号： H01L43/10 , H01L43/12
CPC分类号： H01L43/12 , H01L21/02381 , H01L21/02466 , H01L21/02491 , H01L21/02502 , H01L21/02549 , H01L21/02631 , H01L21/02658 , H01L43/14
摘要： A method for manufacturing a semiconductor thin film having high carrier mobility, and a magnetoelectric conversion element provided with the semiconductor thin film manufactured by the aforementioned method are provided. The temperature of the Si single crystal substrate is raised to 270°C to 320°C, and an In buffer layer is formed by an electron beam heating type vacuum evaporation method. Subsequently, an initial seed layer made of Sb and In is formed. The temperature of the Si single crystal substrate is raised to 460°C to 480°C, and thereafter, a retention time approximated by a predetermined function of the temperature of the Si single crystal substrate is provided. Then, a main growth layer made of Sb and In is formed.
摘要翻译：本发明提供一种用于制造具有高载流子迁移的半导体薄膜，并且设置有通过上述方法制造的半导体薄膜的磁电转换元件的方法。在Si单晶衬底的温度升高到270℃至320℃，并在缓冲层是通过电子束加热式真空蒸镀法形成。随后，由Sb和在初始种子层上形成。在Si单晶衬底的温度升高到460℃至480℃，并且此后，提供了一种通过在Si单晶衬底的温度的预定函数近似的保留时间。然后，由Sb和In的主生长层中形成。

17. 发明授权

EP0632485B1 Method of fabricating semiconductor thin film and method of fabricating hall-effect device 失效
标题翻译：一种用于制造半导体薄膜及其制造方法的霍尔效应组装方法
公开(公告)号：EP0632485B1
公开(公告)日：1999-12-22
申请号：EP94108235.6
申请日：1994-05-27
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： Kawasaki, Tetuo , Koretika, Tetuhiro , Kitabatake, Makoto , Hirao, Takashi
IPC分类号： H01L21/20 , H01L43/14
CPC分类号： H01L43/08 , H01L21/02381 , H01L21/02466 , H01L21/02502 , H01L21/02549 , H01L21/02631 , H01L43/065 , Y10S438/974

18. 发明公开

EP0840942A4 GaAs SUBSTRATE WITH COMPOSITIONALLY GRADED AlGaAsSb BUFFER FOR FABRICATION OF HIGH-INDIUM FETS 失效
标题翻译：砷化镓衬底，梯度复合A1GaAsSB BUFFER用于生产场效应晶体管HIGH铟含量
公开(公告)号：EP0840942A4
公开(公告)日：1999-11-03
申请号：EP96941332
申请日：1996-11-08
申请人： LOCKHEED CORP
发明人： GILL DAVID M , UPPAL PARVEZ NASIR
IPC分类号： H01L21/20 , H01L29/10 , H01L21/203 , H01L29/205 , H01L31/0304
CPC分类号： H01L29/1075 , H01L21/02395 , H01L21/02463 , H01L21/02466 , H01L21/0251 , H01L21/02543 , H01L21/02546
摘要： Semiconductor devices made in high-indium-content semiconductor material (16) have advantageous properties, but similar substrate materials are hard to handle. A buffer layer (18) makes a lattice-constant transition between a GaAs substrate and a high-indium epitaxially deposited semiconductor such as those lattice-matched to InP. The buffer layer (18) is an epitaxial layer including atoms of two Group III elements, and atoms of two Group V elements, with the ratio of the atoms of at least one group varied along the depth of the buffer layer, in a manner which makes a transition of the lattice constant between that of the substrate and the high-indium semiconductor material. The Group III elements are gallium and aluminum, and the Group V elements are arsenic and antimony.

19. 发明授权

EP0531550B1 FIELD EFFECT TRANSISTOR 失效
标题翻译： FELDEFFEKTTRANSISTOR
公开(公告)号：EP0531550B1
公开(公告)日：1997-12-29
申请号：EP92907880
申请日：1992-03-27
申请人： ASAHI CHEMICAL IND
发明人： SHIBASAKI ICHIRO , NAGASE KAZUHIRO
IPC分类号： H01L21/20 , H01L29/10 , H01L29/201 , H01L29/778 , H01L29/772 , H01L29/812
CPC分类号： H01L29/7783 , H01L21/0237 , H01L21/02395 , H01L21/02433 , H01L21/02461 , H01L21/02463 , H01L21/02466 , H01L21/02502 , H01L21/02543 , H01L21/02546 , H01L21/02549 , H01L29/1075 , H01L29/201
摘要： A field effect transistor in which a first compound semiconductor layer (2) functioning as a buffer layer, an InAs layer (3) functioning as an electron traveling layer, and a second compound semiconductor layer (4) functioning as an electron feeding layer or a barrier layer are formed in succession on a semiconductor substrate (1) having a different lattice constant from that of InAs. The first compound semiconductor layer (2) is in lattice matching with InAs substantially, and is formed of one selected from among AlGaAsSb, AlGaPSb, AlInAsSb or AlInPSb, whose band gaps are larger than that of InAs, and has a simple structure. On the substrate (1) having the different lattice constant from the InAs layer (3), a FET having excellent high-frequency characteristics can be realized.
摘要翻译：一种场效应晶体管，其中用作缓冲层的第一化合物半导体层（2），用作电子传输层的InAs层（3）和用作电子馈送层或第二化合物半导体层（4）的第二化合物半导体层在具有与InAs不同的晶格常数的半导体衬底（1）上依次形成阻挡层。第一化合物半导体层（2）实质上与InAs晶格匹配，并且由选自AlGaAsSb，AlGaPSb，AlInAsSb或AlInPSb中的一种形成，其带隙大于InAs，并且具有简单的结构。在具有与InAs层（3）不同的晶格常数的衬底（1）上，可以实现具有优异的高频特性的FET。

20. 发明公开

EP0632485A3 Method of fabricating semicondutor thin film and method of fabricating hall-effect device 失效
标题翻译：一种用于制造半导体薄膜及其制造方法的霍尔效应器件的方法。
公开(公告)号：EP0632485A3
公开(公告)日：1995-08-23
申请号：EP94108235.6
申请日：1994-05-27
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： Kawasaki, Tetuo , Koretika, Tetuhiro , Kitabatake, Makoto , Hirao, Takashi
IPC分类号： H01L21/20 , H01L43/14
CPC分类号： H01L43/08 , H01L21/02381 , H01L21/02466 , H01L21/02502 , H01L21/02549 , H01L21/02631 , H01L43/065 , Y10S438/974
摘要： A method of fabricating a semiconductor thin film (4) is initiated with preparing a substrate (1) having a surface consisting of a single crystal of Si. The surface has an oxide film. Then, the oxide film is removed. The dangling bonds of the Si atoms on the surface are terminated with hydrogen atoms. An initial layer (2) is formed on the substrate of the single crystal of Si terminated with the hydrogen atoms, of at least one selected from the group consisting of Al, Ga, and In. A buffer layer (3) containing at least In and Sb is formed on the initial layer. A semiconductor thin film (4) containing at least In and Sb is formed on the buffer layer (3) at a temperature higher than the temperature at which the buffer layer (3) is started to be formed.
There is also disclosed a method of fabricating a Hall-effect device. This method is initiated with forming a semiconductor thin film by making use of the above-described fabrication method. Then, electrodes are attached to the thin film.

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