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11. 发明公开

EP3289445A1 FLOATING POINT COMPUTATION APPARATUS AND METHOD 有权
标题翻译：浮点计算装置和方法
公开(公告)号：EP3289445A1
公开(公告)日：2018-03-07
申请号：EP16802335.6
申请日：2016-02-15
申请人： Huawei Technologies Co. Ltd.
发明人： HO, Huong , KAFROUNI, Michel
IPC分类号： G06F9/38
CPC分类号： G06F7/485 , G06F7/506 , G06F2207/5063
摘要： A method comprises receiving a first N-bit unsigned number and a second N-bit unsigned number, receiving a control signal indicating a m-bit shifting operation and processing the first N-bit unsigned number, the second N-bit unsigned number and the control signal in an add-and-shift apparatus, wherein an addition/subtraction operation and the m-bit shifting operation are performed in parallel in the add-and-shift apparatus.

12. 发明公开

EP0981080A1 Carry look-ahead addition circuits 有权
标题翻译： Schaltungen zurÜbertragvorgriffsaddition
公开(公告)号：EP0981080A1
公开(公告)日：2000-02-23
申请号：EP99304339.7
申请日：1999-06-03
申请人： Stmicroelectronics, Ltd.
发明人： Knowles, Simon
IPC分类号： G06F7/50
CPC分类号： G06F7/508 , G06F2207/5063
摘要： A method of designing an addition circuit, and an addition circuit designed according to the method are described. The design technique is optimised to facilitate design of an addition circuit of minimum depth. The design technique takes into account the number of logical stages of the addition circuit and the manner in which those stages are connected by spanning paths to create fan-out nodes. The number of fan-out nodes per level can be optimised.
摘要翻译：描述了一种设计加法电路的方法，以及根据该方法设计的加法电路。优化了设计技术，以便于设计最小深度的加法电路。设计技术考虑了加法电路的逻辑级数以及通过跨越路径连接这些级的方式来创建扇出节点。可以优化每个级别的扇出节点数量。

13. 发明公开

EP0853274A3 Tree structured arithmetic and logic circuits 失效
标题翻译： Baumstrukturierte arithmetische und logische Schaltungen
公开(公告)号：EP0853274A3
公开(公告)日：1999-11-10
申请号：EP97403097.5
申请日：1997-12-19
申请人： SONY CORPORATION
发明人： Hirairi, Koji
IPC分类号： G06F7/00 , G06F7/50 , G06F7/544
CPC分类号： G06F7/74 , G06F7/026 , G06F7/508 , G06F7/544 , G06F2207/5063
摘要： A method of operation of an arithmetic and logic unit, a storage medium, and an arithmetic and logic unit introducing a technique and concept of converting a serial structure of decisions having an order dependency to an indeterminate code binary tree which can be processed in parallel so as to simplify the configuration and enable higher speed operation processing. Where a serial structure of decisions having an order dependency is converted to a binary tree structure using decision nodes not having dependency input/outputs as leaves and higher priority determination nodes as the nodes other than the leaves, the decision nodes having dependency input/outputs are replaced by decision nodes not having dependency input/outputs provided with connotation decision nodes and indeterminate code generation nodes.
摘要翻译：一种算术和逻辑单元，存储介质和算术和逻辑单元的操作方法，其引入将具有顺序依赖性的决定的串行结构转换为可以并行处理的不确定代码二进制树的技术和概念以简化配置并实现更高速度的操作处理。在具有顺序依赖性的决策的串行结构使用不具有依赖输入/输出的判定节点作为叶片和较高优先级确定节点作为除了叶子之外的节点而被转换为二叉树结构的情况下，具有相关输入/输出的判定节点是由不具有内含决策节点和不确定代码生成节点提供的依赖输入/输出的决策节点代替。

14. 发明公开

EP0853274A2 Tree structured arithmetic and logic circuits 失效
标题翻译：树状结构的算术和逻辑电路
公开(公告)号：EP0853274A2
公开(公告)日：1998-07-15
申请号：EP97403097.5
申请日：1997-12-19
申请人： SONY CORPORATION
发明人： Hirairi, Koji
IPC分类号： G06F7/00 , G06F7/50 , G06F7/544
CPC分类号： G06F7/74 , G06F7/026 , G06F7/508 , G06F7/544 , G06F2207/5063
摘要： A method of operation of an arithmetic and logic unit, a storage medium, and an arithmetic and logic unit introducing a technique and concept of converting a serial structure of decisions having an order dependency to an indeterminate code binary tree which can be processed in parallel so as to simplify the configuration and enable higher speed operation processing.
Where a serial structure of decisions having an order dependency is converted to a binary tree structure using decision nodes not having dependency input/outputs as leaves and higher priority determination nodes as the nodes other than the leaves, the decision nodes having dependency input/outputs are replaced by decision nodes not having dependency input/outputs provided with connotation decision nodes and indeterminate code generation nodes.

15. 发明公开

EP0442665A2 Lookahead adder with universal logic gates 失效
标题翻译：具有通用逻辑门的前瞻加法器
公开(公告)号：EP0442665A2
公开(公告)日：1991-08-21
申请号：EP91301012.0
申请日：1991-02-07
申请人： Hewlett-Packard Company
发明人： Lamb, Joel D.
IPC分类号： G06F7/50 , H03K19/094
CPC分类号： G06F7/508 , G06F2207/3876 , G06F2207/5063 , H03K19/0948
摘要： A lookahead adder with identical logic gates (MCLA) in all but the first of its lookahead sections. All such identical gates implement the logic function M = X + Y.Z.
摘要翻译：除了第一个先行部分之外的所有其他逻辑门（MCLA）的前瞻加法器。所有这些相同的门都实现了逻辑功能M = X + Y.Z.

16. 发明授权

EP2013705B1 ADDITIONNEUR N BITS ET PROCÉDÉ D'ADDITION CORRESPONDANT 有权
标题翻译： N位加法器和相关联的加入法
公开(公告)号：EP2013705B1
公开(公告)日：2015-11-11
申请号：EP07731319.5
申请日：2007-04-19
申请人： S.A.R.L. Daniel Torno
发明人： TORNO, Daniel
IPC分类号： G06F7/506 , G06F7/508
CPC分类号： G06F7/506 , G06F7/508 , G06F2207/5063

17. 发明公开

EP1296223A3 Adder incrementer circuit 审中-公开
标题翻译：添加和增加
公开(公告)号：EP1296223A3
公开(公告)日：2005-09-14
申请号：EP02256594.9
申请日：2002-09-23
申请人： Broadcom Corporation
发明人： Evans, Richard James
IPC分类号： G06F7/50
CPC分类号： G06F7/508 , G06F7/5055 , G06F7/506 , G06F2207/5063
摘要： In association with a circuit for adding binary numbers, it is often useful to increment the sum by a value of 1, for example on a conditional basis. Each of the combined adder and incrementer circuits embodying the invention also provides an output indicating whether a CarryOut signal resulted from the incrementing operation, or whether the Carryout signal resulted from the addition. The preferred embodiments utilize prefix-type adder circuits using a single carry chain. Alternate embodiments generate a CarryOut signal as a function of the incrementing operation, using either generate and propagate signals or from generate and kill signals from the carry chain.

18. 发明授权

EP1081590B1 An incrementer/decrementer having a reduced fan-out architecture 有权
标题翻译：增量器/递减器具有降低的起动负载架构
公开(公告)号：EP1081590B1
公开(公告)日：2004-12-08
申请号：EP00306101.7
申请日：2000-07-18
申请人： Agilent Technologies, Inc. (a Delaware corporation)
发明人： Martin, Robert J. , Dix, Gregory S. , Lin, Linda L.
IPC分类号： G06F7/50
CPC分类号： G06F7/5055 , G06F7/508 , G06F2207/5063

19. 发明授权

EP0981080B1 Parallel addition circuits with optimized fan out interconnections 有权
标题翻译：并行加法器具有优化的扇出链接
公开(公告)号：EP0981080B1
公开(公告)日：2003-09-17
申请号：EP99304339.7
申请日：1999-06-03
申请人： STMicroelectronics, Ltd.
发明人： Knowles, Simon
IPC分类号： G06F7/50
CPC分类号： G06F7/508 , G06F2207/5063

20. 发明公开

EP1081590A1 An incrementer/decrementer having a reduced fan-out architecture 有权
标题翻译： Ein Inkrementierer / Dekrementierer mit verringerter Ausgangsbelastungsarchitektur
公开(公告)号：EP1081590A1
公开(公告)日：2001-03-07
申请号：EP00306101.7
申请日：2000-07-18
申请人： Agilent Technologies Inc
发明人： Martin, Robert J. , Dix, Gregory S. , Lin, Linda L.
IPC分类号： G06F7/50
CPC分类号： G06F7/5055 , G06F7/508 , G06F2207/5063
摘要： An incrementer/decrementer architecture (100) having a reduced internal block fanout which is achieved efficiently in terms of the silicon area needed to implement the incrementer/decrementer (100). The incrementer/decrementer (100) of the present invention is characterized by a modified tree structure having operators (21, 31, 35, 41, 44, 48, 51, 23, 25, 33, 37, 42, 46, 75, 76, 77, 78, 79, 80, 81, 82, 51-54, 83-86, 55, 57, 59, 63, 56, 58, 61, 64) located in such a manner that the maximum internal block fanout is equal to (incrementer/decrementer width)/8 for incrementer/decrementers (100) having a width of at least 16 bits. For incrementer/decrementers (100) having a width of less than 16 bits, the internal block fanout is 2. The routing complexity is increased in order to implement redundant overlapping operations which, in turn, decreases the internal block fanout. However, increases in routing complexity can be accomplished within the minimum X-by-Y area of each stage of the incrementer/decrementer (100). Therefore, the overall performance of the incrementer/decrementer (100) of the present invention can be optimized while meeting minimum area requirements.
摘要翻译：具有减少的内部块扇出的增量/减法器架构（100），其在实现递增器/递减器（100）所需的硅面积方面有效地实现。本发明的递增器/减量器（100）的特征在于具有操作者（21,31,35,41,44,48,51,23,25,33,37,42,46,75,76）的改进的树结构，77,78,79,80,81,82,51-54,83-86,55,57,59,63,56,58,61,64）以最大内部块扇出相等的方式设置到具有至少16位宽度的增量/减量器（100）的（递增器/减量器宽度）/ 8。对于宽度小于16位的增量器/减法器（100），内部块扇出为2.为了实现冗余重叠操作，增加了路由复杂度，从而减少了内部块扇出。然而，路由复杂度的增加可以在递增器/递减器（100）的每个级的最小X-by-Y区域内完成。因此，可以在满足最小面积要求的同时优化本发明的增量递减器（100）的整体性能。

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