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1. 发明公开

EP1111615A1 Logic circuit 审中-公开
标题翻译： Logische Schaltung
公开(公告)号：EP1111615A1
公开(公告)日：2001-06-27
申请号：EP00400539.3
申请日：2000-02-29
申请人： SONY CORPORATION
发明人： Hirairi, Koji
IPC分类号： G11C7/00 , H03K3/037
CPC分类号： H03K3/356139 , G11C7/1006 , H03K3/037 , H03K3/356156
摘要： The logic circuit includes a logic circuit portion comprised of a dual-rail type logic tree, a synchronization type sensing latch means (130) comprised of a sense amplifier (131) for differentially amplifying results of evaluation of the logic circuit portion in synchronization with a clock, a logic tree disconnection controlling circuit (133), and a group of switches for disconnection of the logic tree, and a set and reset latch means for holding a logic for one cycle of the synchronization signal. In an idle stage, the sense amplifier (131) is deactivated, the dual-rail type logic tree unit and sensing latch (130) are connected, and the output terminals of the dual-rail type logic tree are short-circuited. In the drive stage, the sense amplifier (131) is activated and the output terminals of the dual-rail logic tree are opened. In the final determination stage, the sense amplifier (131) is activated and the logic tree and sensing latch unit (130) are disconnected. The glitches are thus eliminated to reduce the power consumption and increase the speed.
摘要翻译：逻辑电路包括由双轨型逻辑树构成的逻辑电路部分，同步型感测锁存装置（130），其包括读出放大器（131），用于与逻辑电路部分同步地差分地放大逻辑电路部分的评估结果时钟，逻辑树断开控制电路（133）和用于断开逻辑树的一组开关，以及用于保持同步信号的一个周期的逻辑的置位和复位锁存装置。在空闲阶段，读出放大器（131）被去激活，双轨型逻辑树单元和感测锁存器（130）连接，双轨型逻辑树的输出端短路。在驱动级中，感测放大器（131）被激活，双轨逻辑树的输出端被打开。在最终确定阶段，感测放大器（131）被激活，并且逻辑树和感测锁存单元（130）被断开。因此消除毛刺以降低功耗并提高速度。

2. 发明公开

EP1111782A2 Differential sense amplifier circuit and dynamic logic circuit using the same 审中-公开
标题翻译：差动读出放大器电路和其在动态逻辑电路中的应用
公开(公告)号：EP1111782A2
公开(公告)日：2001-06-27
申请号：EP00400538.5
申请日：2000-02-29
申请人： SONY CORPORATION
发明人： Hirairi, Koji
IPC分类号： H03K3/356
CPC分类号： G11C7/065 , G11C7/1006 , H03K3/356156
摘要： A dynamic logic circuit (300) where a duality logic tree (200) is connected to a sense amplifier (100) through a switch, which reduces the power consumption and suppresses coupling noise by controlling the connection of the logic tree (200) and the sense amplifier (100) by the voltages of the input and output nodes of the sense amplifier (100).

3. 发明公开

EP0853274A3 Tree structured arithmetic and logic circuits 失效
标题翻译： Baumstrukturierte arithmetische und logische Schaltungen
公开(公告)号：EP0853274A3
公开(公告)日：1999-11-10
申请号：EP97403097.5
申请日：1997-12-19
申请人： SONY CORPORATION
发明人： Hirairi, Koji
IPC分类号： G06F7/00 , G06F7/50 , G06F7/544
CPC分类号： G06F7/74 , G06F7/026 , G06F7/508 , G06F7/544 , G06F2207/5063
摘要： A method of operation of an arithmetic and logic unit, a storage medium, and an arithmetic and logic unit introducing a technique and concept of converting a serial structure of decisions having an order dependency to an indeterminate code binary tree which can be processed in parallel so as to simplify the configuration and enable higher speed operation processing. Where a serial structure of decisions having an order dependency is converted to a binary tree structure using decision nodes not having dependency input/outputs as leaves and higher priority determination nodes as the nodes other than the leaves, the decision nodes having dependency input/outputs are replaced by decision nodes not having dependency input/outputs provided with connotation decision nodes and indeterminate code generation nodes.
摘要翻译：一种算术和逻辑单元，存储介质和算术和逻辑单元的操作方法，其引入将具有顺序依赖性的决定的串行结构转换为可以并行处理的不确定代码二进制树的技术和概念以简化配置并实现更高速度的操作处理。在具有顺序依赖性的决策的串行结构使用不具有依赖输入/输出的判定节点作为叶片和较高优先级确定节点作为除了叶子之外的节点而被转换为二叉树结构的情况下，具有相关输入/输出的判定节点是由不具有内含决策节点和不确定代码生成节点提供的依赖输入/输出的决策节点代替。

4. 发明公开

EP0853274A2 Tree structured arithmetic and logic circuits 失效
标题翻译：树状结构的算术和逻辑电路
公开(公告)号：EP0853274A2
公开(公告)日：1998-07-15
申请号：EP97403097.5
申请日：1997-12-19
申请人： SONY CORPORATION
发明人： Hirairi, Koji
IPC分类号： G06F7/00 , G06F7/50 , G06F7/544
CPC分类号： G06F7/74 , G06F7/026 , G06F7/508 , G06F7/544 , G06F2207/5063
摘要： A method of operation of an arithmetic and logic unit, a storage medium, and an arithmetic and logic unit introducing a technique and concept of converting a serial structure of decisions having an order dependency to an indeterminate code binary tree which can be processed in parallel so as to simplify the configuration and enable higher speed operation processing.
Where a serial structure of decisions having an order dependency is converted to a binary tree structure using decision nodes not having dependency input/outputs as leaves and higher priority determination nodes as the nodes other than the leaves, the decision nodes having dependency input/outputs are replaced by decision nodes not having dependency input/outputs provided with connotation decision nodes and indeterminate code generation nodes.

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