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11. 发明公开

EP3311384A1 ULTRA-DEEP POWER DOWN MODE CONTROL IN A MEMORY DEVICE 有权
标题翻译：存储设备中的超深度休眠模式控制
公开(公告)号：EP3311384A1
公开(公告)日：2018-04-25
申请号：EP16812082.2
申请日：2016-04-13
申请人： Adesto Technologies Corporation
发明人： LEWIS, Derric , DINH, John , INTRATER, Gideon , GONZALES, Nathan
IPC分类号： G11C5/14
CPC分类号： G06F3/0625 , G06F1/24 , G06F1/3275 , G06F1/3287 , G06F1/3296 , G06F3/0634 , G06F3/0659 , G06F3/068 , G06F13/4282 , G06F2213/0016 , G11C5/148 , G11C11/417 , Y02D10/14 , Y02D10/151
摘要： A method of controlling an ultra-deep power down (UDPD) mode in a memory device, can include: receiving a write command from a host via an interface; beginning a write operation on the memory device to execute the write command; reading an auto-UDPD (AUDPD) configuration bit from a status register; completing the write operation on the memory device; automatically entering the UDPD mode upon completion of the write operation in response to the AUDPD configuration bit being set; and entering a standby mode upon completion of the write operation in response to the AUDPD configuration bit being cleared.

12. 发明公开

EP3238077A1 FAULT TOLERANT AUTOMATIC DUAL IN-LINE MEMORY MODULE REFRESH 有权
标题翻译：容错自动双列直插式内存模块刷新
公开(公告)号：EP3238077A1
公开(公告)日：2017-11-01
申请号：EP15874018.3
申请日：2015-11-24
申请人： Intel Corporation
发明人： JAYAKUMAR, Sarathy , KUMAR, Mohan J.
IPC分类号： G06F13/16 , G06F12/02
CPC分类号： G06F11/1441 , G06F1/30 , G06F1/3275 , G06F11/2015 , G06F12/0246 , G06F12/0638 , G06F12/0891 , G06F2212/205 , G06F2212/7208 , G06F2212/7209 , G11C5/04 , G11C5/148 , G11C7/20 , G11C14/0036 , G11C14/0045
摘要： Methods and apparatus to fault tolerant Automatic DIMM (Dual In-line Memory Module) Refresh or ADR are described. In an embodiment, a processor includes non-volatile memory to store data from one or more volatile buffers of the processor. The data from the one or more volatile buffers of the processor are stored into the non-volatile memory in response to occurrence of an event that is to lead to a system reset or shut down. Other embodiments are also disclosed and claimed.
摘要翻译：描述了容错自动DIMM（双列直插式存储器模块）刷新或ADR的方法和装置。在一个实施例中，处理器包括非易失性存储器以存储来自处理器的一个或多个易失性缓冲器的数据。响应于导致系统重置或关闭的事件的发生，来自处理器的一个或多个易失性缓冲器的数据被存储到非易失性存储器中。其他实施例也被公开和要求保护。

13. 发明授权

EP2564321B1 MEMORY USAGE SCANNING 有权转让
标题翻译：内存使用扫描
公开(公告)号：EP2564321B1
公开(公告)日：2017-09-27
申请号：EP11777778.9
申请日：2011-04-06
申请人： Microsoft Technology Licensing, LLC
发明人： WORTHINGTON, Bruce L. , SHARDA, Vishal , ZHANG, Qi , IYIGUN, Mehmet , BAK, Yevgeniy
IPC分类号： G06F12/1009 , G06F1/32 , G06F11/34 , G06F3/06
CPC分类号： G06F3/0625 , G06F1/3225 , G06F1/3268 , G06F1/3275 , G06F3/0647 , G06F3/0688 , G06F11/3471 , G06F12/1009 , G06F2201/88 , Y02D10/13 , Y02D10/14 , Y02D10/154 , Y02D10/34
摘要： A memory scanning system may scan memory objects to determine usage frequency by scanning each memory object using a mapping of the processes stored in memory. The scanning may be performed multiple times to generate a usage history for each page or unit of memory. In some cases, scanning may be performed at different frequencies to determine multiple classifications of usage. The mapping may create a detailed topology of memory usage, including multiple classifications of access frequency, as well as several other classifications. Based on the topology, the objects in memory may be copied to another storage medium or optimized for performance or power consumption.
摘要翻译：存储器扫描系统可以扫描存储器对象以通过使用存储在存储器中的过程的映射扫描每个存储器对象来确定使用频率。扫描可以被执行多次以产生每个页面或存储单元的使用历史。在一些情况下，扫描可以以不同的频率执行以确定多个使用分类。该映射可以创建内存使用的详细拓扑，包括访问频率的多个分类以及其他几个分类。基于拓扑结构，内存中的对象可能会被复制到另一个存储介质或针对性能或功耗进行优化。

14. 发明公开

EP3049890A4 POWER CONSUMPTION REDUCTION IN A COMPUTING DEVICE 审中-公开
标题翻译： REDUZIERUNG DES ENERGIEVERBRAUCHES EINER BERECHNUNGSVORRICHTUNG
公开(公告)号：EP3049890A4
公开(公告)日：2017-06-21
申请号：EP14848616
申请日：2014-09-22
申请人： INTEL CORP
发明人： MATTHEWS SHANE , HALL CHRISTOPHER
IPC分类号： G06F1/32
CPC分类号： G06F1/3287 , G06F1/3203 , G06F1/3268 , G06F1/3275 , H04N1/00 , Y02D10/14 , Y02D10/154 , Y02D10/171
摘要： Various techniques for reducing power consumption of a computing device are described herein. In one example, a method includes detecting that the computing device is to execute a first operation for a first hardware component. The method can also include determining that the computing device is not to execute a second operation for a second hardware component during a period of time. Furthermore, the method can include loading operation data corresponding to the first operation into a processor cache from a non-volatile storage device and detecting that the first operation is not to request memory data from a volatile storage device. The method can also include removing power from at least one storage device.
摘要翻译：这里描述了用于降低计算设备的功耗的各种技术。在一个示例中，一种方法包括检测计算设备将执行第一硬件组件的第一操作。该方法还可以包括确定计算设备在一段时间内不对第二硬件组件执行第二操作。此外，该方法可以包括将对应于第一操作的操作数据从非易失性存储设备加载到处理器高速缓存中，并且检测到第一操作不从易失性存储设备请求存储器数据。该方法还可以包括从至少一个存储设备去除电力。

15. 发明授权

EP2557480B1 Image forming apparatus, microcontroller, and methods for controlling image forming apparatus and microcontroller 有权转让
标题翻译：图像形成装置，微控制器以及用于控制图像形成装置和微控制器的方法
公开(公告)号：EP2557480B1
公开(公告)日：2017-05-17
申请号：EP12179841.7
申请日：2012-08-09
申请人： S-Printing Solution Co., Ltd.
发明人： Park, Jin-kyu , Jung, Ji-won , Park, Ho-beom
IPC分类号： G06F1/32 , G09G5/00
CPC分类号： G06F1/3265 , G06F1/3275 , Y02D10/14 , Y02D10/153 , Y02D50/20
摘要： An image forming apparatus, a microcontroller, and methods for controlling the image forming apparatus and the microcontroller are provided. The microcontroller include: a memory controller which is connected to an external memory operating in a self-refresh mode if a normal mode changes to a low power mode, performs a control operation by using the external memory in the normal mode, and outputs a preset signal which is to cancel the self-refresh mode if the low power mode changes to the normal mode; a memory interface unit which transmits the preset signal to a main memory; and a signal detector which detects whether the preset signal has been output. Here, the memory controller powers off the memory interface unit if the normal mode changes to the low power mode and powers on the memory interface unit if the low power mode changes to the normal mode, and the output of the preset signal is detected by the signal detector.
摘要翻译：提供了图像形成装置，微控制器以及用于控制图像形成装置和微控制器的方法。微控制器包括：存储器控制器，如果正常模式改变为低功率模式，则连接到以自刷新模式操作的外部存储器，在正常模式下通过使用外部存储器执行控制操作，并且输出预置如果低功率模式改变为正常模式，则取消自刷新模式的信号; 存储器接口单元，其将预设信号发送到主存储器; 以及检测预设信号是否已被输出的信号检测器。这里，如果正常模式改变为低功率模式，则存储器控制器断电存储器接口单元，并且如果低功率模式改变为正常模式，则通电存储器接口单元，并且预置信号的输出由信号检测器。

16. 发明公开

EP3161643A1 DISUNITED SHARED-INFORMATION AND PRIVATE-INFORMATION CACHES 审中-公开
标题翻译：在私人信息下获取信息CACHESPEICHERFÜRGEMEINSAM GENUTZTE
公开(公告)号：EP3161643A1
公开(公告)日：2017-05-03
申请号：EP15729061.0
申请日：2015-06-08
申请人： Qualcomm Incorporated
发明人： PATSILARAS, George , RYCHLIK, Bohuslav , ROHILLAH, Anwar
IPC分类号： G06F12/08 , G06F1/32
CPC分类号： G06F12/0811 , G06F1/3275 , G06F1/3287 , G06F12/0815 , G06F12/0837 , G06F12/084 , G06F12/0848 , G06F2212/1024 , G06F2212/1028 , G06F2212/1056 , G06F2212/283 , G06F2212/314 , G06F2212/601 , Y02D10/13 , Y02D10/14 , Y02D10/171
摘要： Systems and methods pertain to a multiprocessor system comprising disunited cache structures. A first private-information cache is coupled to a first processor of the multiprocessor system. The first private-information cache is configured to store information that is private to the first processor. A first shared-information cache which is disunited from the first private-information cache is also coupled to the first processor. The first shared-information cache is configured to store information that is shared/shareable between the first processor and one or more other processors of the multiprocessor system.
摘要翻译：系统和方法涉及包含不均匀缓存结构的多处理器系统。第一私人信息缓存耦合到多处理器系统的第一处理器。第一私人信息缓存被配置为存储对第一处理器是私有的信息。与第一专用信息高速缓存分离的第一共享信息高速缓存也耦合到第一处理器。第一共享信息缓存被配置为存储在第一处理器与多处理器系统的一个或多个其他处理器之间共享/共享的信息。

17. 发明公开

EP3142015A1 LOW-POWER MEMORY-ACCESS METHOD AND ASSOCIATED APPARATUS 审中-公开
标题翻译：津巴布韦多米尼加共和国麻省理工学院
公开(公告)号：EP3142015A1
公开(公告)日：2017-03-15
申请号：EP16175228.2
申请日：2016-06-20
申请人： MediaTek Inc.
发明人： LEE, Yen-Lin , LI, Yun-Ching , HSIAO, Chih-Hsiang , HSIEH, Yu-Cheng , TU, Li-Chun
IPC分类号： G06F12/0804 , G06F1/32
CPC分类号： G06F1/3287 , G06F1/3275 , G06F3/0619 , G06F3/065 , G06F3/0685 , G06F12/0238 , G06F12/0638 , G06F12/0804 , G06F12/1081 , G06F13/28 , G06F2212/1028 , G06F2212/1044 , G06F2212/205 , G06F2212/656 , G11C14/0036 , Y02D10/13 , Y02D10/14 , Y02D10/171
摘要： A low-power memory access method and associated apparatus are provided. The apparatus includes a memory controller and a processing unit. The memory controller is coupled to a first memory and a second memory, and includes: a memory management circuit, for allocating physical memory addresses of the first memory and the second memory and controlling access of the first memory and the second memory; and a direct-memory-access (DMA) controller. The processing unit is for accessing the first memory and the second memory via the memory controller. When the apparatus is in an active mode, the memory management circuit copies a portion of data stored in the second memory to the first memory for use by the processing unit, and records dirty data information when the portion of data in the first memory differs from that in the second memory.
摘要翻译：提供了一种低功率存储器存取方法及相关装置。该装置包括存储器控制器和处理单元。存储器控制器耦合到第一存储器和第二存储器，并且包括：存储器管理电路，用于分配第一存储器和第二存储器的物理存储器地址并控制第一存储器和第二存储器的存取; 和直接存储器访问（DMA）控制器。处理单元用于经由存储器控制器访问第一存储器和第二存储器。当装置处于活动模式时，存储器管理电路将存储在第二存储器中的数据的一部分复制到第一存储器供处理单元使用，并且当第一存储器中的数据部分不同时记录脏数据信息在第二个记忆中。

18. 发明公开

EP2979270A4 AUTO-SUSPEND AND AUTO-RESUME OPERATIONS FOR A MULTI-DIE NAND MEMORY DEVICE 审中-公开
标题翻译：多纳米器件的自我暂停和自我接收操作
公开(公告)号：EP2979270A4
公开(公告)日：2016-11-09
申请号：EP14774103
申请日：2014-02-13
申请人： INTEL CORP
发明人： GHALAM ALI , NOBUNAGA DEAN , GUO JASON
IPC分类号： G11C16/34 , G11C16/30
CPC分类号： G11C16/30 , G06F1/3275 , G11C5/148 , G11C8/12 , G11C16/225 , Y02B60/1228 , Y02D10/14
摘要： A method and apparatus that controls a peak-current condition in a multi-die memory, such as a solid-state drive, by determining by at least one die of the multi-die memory whether a subsequent memory operation is a high-current memory operation, such as an operation to enable a charge pump of the die, an operation to charge a bit line of the die, or a program/erase loop operation, or a combination thereof. The die enters a suspended-operation mode if the subsequent memory operation is determined to be a high current memory operation. Operation is resumed by the die in response to a resume operation event, such as, but not limited to, a command specifically address to the die, an indication from another die that a high-current memory operation is complete. Once operation is resumed, the die performs the high-current memory operation.
摘要翻译：一种通过由多芯片存储器的至少一个管芯确定后续存储器操作是否是高电流存储器来控制多管芯存储器（例如固态驱动器）中的峰值电流状态的方法和装置操作，例如使能芯片的电荷泵的操作，对芯片的位线充电的操作，或编程/擦除循环操作，或其组合。如果后续存储器操作被确定为高电流存储器操作，则芯片进入暂停操作模式。响应于恢复操作事件，例如但不限于对芯片的特定地址的命令，来自另一管芯的指示大电流存储器操作完成的操作由管芯复原。一旦操作恢复，芯片执行高电流存储器操作。

19. 发明公开

EP3037914A1 SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译： SCHALTUNG MIT INTEGRIERTEM HALBEITER
公开(公告)号：EP3037914A1
公开(公告)日：2016-06-29
申请号：EP15194694.4
申请日：2015-11-16
申请人： Kabushiki Kaisha Toshiba
发明人： Kohara, Yoshihisa
IPC分类号： G06F1/32 , H04W52/02 , H04L29/08
CPC分类号： G06F1/3237 , G06F1/3206 , G06F1/324 , G06F1/3243 , G06F1/3275 , G06F1/3287 , H04N13/275 , Y02B70/12 , Y02B70/123 , Y02B70/126 , Y02B70/32 , Y02D10/128 , Y02D10/14 , Y02D10/152 , Y02D10/171 , Y02D50/20
摘要： According to one embodiment, a semiconductor integrated circuit includes the following configuration. A arithmetic processing circuit includes a first processor core performing arithmetic processing and a common unit containing a cache memory storing data and programs, and the first processor core or the common unit is divided into a first circuit and a second circuit. The first clock gating circuit supplies or stops a clock to the first circuit. The first power switch supplies or cuts off a power supply voltage to the first circuit. The second clock gating circuit supplies or stops the clock to the second circuit. The second power switch supplies or cuts off the power supply voltage to the second circuit. The controller controls the clock gating circuits and the power switches.
摘要翻译：根据一个实施例，半导体集成电路包括以下配置。算术处理电路包括执行算术处理的第一处理器核心和包含存储数据和程序的高速缓冲存储器的公共单元，并且第一处理器核或公共单元被分成第一电路和第二电路。第一个时钟门控电路为第一个电路提供或停止时钟。第一个电源开关提供或切断第一个电路的电源电压。第二时钟门控电路将时钟提供或停止到第二电路。第二个电源开关提供或切断第二个电路的电源电压。控制器控制时钟门控电路和电源开关。

20. 发明公开

EP3030949A1 SYSTEM AND METHOD FOR MEMORY CHANNEL INTERLEAVING WITH SELECTIVE POWER OR PERFORMANCE OPTIMIZATION 有权
标题翻译：系统和方法SPEICHERKANALVERSCHACHTELUNG选择性服务或性能优化
公开(公告)号：EP3030949A1
公开(公告)日：2016-06-15
申请号：EP14756166.6
申请日：2014-08-07
申请人： Qualcomm Incorporated
发明人： CHUN, Dexter , LI, Yanru , TU, Alex , LO, Haw-jing
IPC分类号： G06F1/32 , G06F12/06
CPC分类号： G06F1/3275 , G06F12/0607 , G06F2212/1028 , G11C14/0009 , Y02D10/13 , Y02D10/14
摘要： Systems and methods are disclosed for providing memory channel interleaving with selective power or performance optimization. One such method involves configuring a memory address map for two or more memory devices accessed via two or more respective memory channels with an interleaved region and a linear region. The interleaved region comprises an interleaved address space for relatively higher performance use cases. The linear region comprises a linear address space for relatively lower power use cases. Memory requests are received from one or more clients. The memory requests comprise a preference for power savings or performance. Received memory requests are assigned to the linear region or the interleaved region according to the preference for power savings or performance.
摘要翻译：系统和方法是游离缺失盘用于提供存储器通道具有选择性功率或性能优化交织。一个搜索方法包括配置存储器地址映射用于通过与交错的两个或更多respectivement存储器通道区域和线性区域访问的两个或更多个存储器设备。的交织地址空间交错的区域包括相对更高的性能使用情况。线性区域包括用于相对较低的功率使用情况的线性地址空间。内存请求从一个或多个客户的好评。存储请求包括用于节能和性能的偏好。接收到的存储器请求被分配给线性区域或交错区域gemäß到偏爱功率节省或性能。

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