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1. 发明公开

EP3178005A1 CACHE LINE COMPACTION OF COMPRESSED DATA SEGMENTS 有权
标题翻译：压缩数据段的缓存线压缩
公开(公告)号：EP3178005A1
公开(公告)日：2017-06-14
申请号：EP15742447.4
申请日：2015-07-09
申请人： Qualcomm Incorporated
发明人： TURNER, Andrew Edmund , PATSILARAS, George , RYCHLIK, Bohuslav
IPC分类号： G06F12/08
CPC分类号： G06F12/0875 , G06F12/0802 , G06F12/0886 , G06F2212/1021 , G06F2212/401 , G06F2212/45 , G06F2212/608
摘要： Methods, devices, and non-transitory process-readable storage media for compacting data within cache lines of a cache. An aspect method may include identifying, by a processor of the computing device, a base address (e.g., a physical or virtual cache address) for a first data segment, identifying a data size (e.g., based on a compression ratio) for the first data segment, obtaining a base offset based on the identified data size and the base address of the first data segment, and calculating an offset address by offsetting the base address with the obtained base offset, wherein the calculated offset address is associated with a second data segment. In some aspects, the method may include identifying a parity value for the first data segment based on the base address and obtaining the base offset by performing a lookup on a stored table using the identified data size and identified parity value.
摘要翻译：用于压缩高速缓存的高速缓存行内的数据的方法，设备和非瞬态过程可读存储介质。方面方法可以包括由计算设备的处理器识别第一数据段的基地址（例如，物理或虚拟高速缓存地址），识别第一数据段的数据大小（例如，基于压缩比）数据段，基于所识别的数据大小和第一数据段的基地址获得基础偏移量，以及通过用所获得的基础偏移量偏移基础地址来计算偏移地址，其中计算出的偏移地址与第二数据相关联分割。在一些方面中，该方法可以包括基于基地址识别第一数据段的奇偶校验值，并且通过使用识别的数据大小和识别的奇偶校验值在存储的表上执行查找来获得基准偏移量。

2. 发明公开

EP3132354A1 METHOD AND APPARATUS FOR LOWERING BANDWIDTH AND POWER IN A CACHE USING READ WITH INVALIDATE 审中-公开
标题翻译：方法和装置减少带宽和性能与老式无效掉CACHE
公开(公告)号：EP3132354A1
公开(公告)日：2017-02-22
申请号：EP15719898.7
申请日：2015-03-31
申请人： Qualcomm Incorporated
发明人： PATSILARAS, George , KHAN, Moinul H. , CHAURASIA, Pankaj , RYCHLIK, Bohuslav , WANG, Feng , ROHILLAH, Anwar Q. , PALACHARLA, Subbarao
IPC分类号： G06F12/08 , G06F12/12 , G06F1/32
CPC分类号： G06F12/0833 , G06F1/3275 , G06F12/0808 , G06F12/0868 , G06F12/126 , G06F12/128 , G06F2212/62 , Y02D10/13 , Y02D10/14
摘要： Ephemeral data stored in a cache is read when needed but is not written to system memory so as to save power and bandwidth. In an embodiment, a no-writeback bit associated with the ephemeral data is set in response to a read-no-writeback instruction. Data in a cache line for which its no-writeback bit has been set is not written back into system memory. Accordingly, when evicting cache lines, if a cache line has a no-writeback bit set, then the data in that cache line is discarded without being written back to system memory.
摘要翻译：存储在缓存中的数据临时需要，但是没有写入到系统内存，从而节省功率和带宽时被读取。，在与所述临时数据相关联的无回写位实施方式响应于读无回写指令被设定。在针对其无回写位已经设置的高速缓存行的数据不写回系统内存。因此，当驱逐高速缓存线中，如果高速缓存行有一个无回写位设置，然后在高速缓存中的数据没有线被丢弃而不被回写到系统存储器中。

3. 发明公开

EP3183658A1 SUPPLEMENTAL WRITE CACHE COMMAND FOR BANDWIDTH COMPRESSION 审中-公开
标题翻译：用于带宽压缩的补充写入缓存命令
公开(公告)号：EP3183658A1
公开(公告)日：2017-06-28
申请号：EP15747334.9
申请日：2015-07-24
申请人： Qualcomm Incorporated
发明人： TURNER, Andrew Edmund , PATSILARAS, George , RYCHLIK, Bohuslav
IPC分类号： G06F12/08
CPC分类号： G06F12/0893 , G06F12/0866 , G06F12/0886 , G06F2212/1028 , G06F2212/1044 , G06F2212/401 , Y02D10/13
摘要： Aspects include computing devices, systems, and methods for implementing a cache memory access requests for data smaller than a cache line and eliminating overfetching from a main memory by writing supplemental data to the unfilled portions of the cache line. A cache memory controller may receive a cache memory access request with a supplemental write command for data smaller than a cache line. The cache memory controller may write supplemental to the portions of the cache line not filled by the data in response to a write cache memory access request or a cache miss during a read cache memory access request. In the event of a cache miss, the cache memory controller may retrieve the data from the main memory, excluding any overfetch data, and write the data and the supplemental data to the cache line. Eliminating overfetching reduces bandwidth and power required to retrieved data from main memory.
摘要翻译：各方面包括用于实现针对小于缓存线的数据的缓存存储器访问请求的计算设备，系统和方法，以及通过将补充数据写入到缓存线的未填充部分来消除从主存储器的过度取消。高速缓存存储器控制器可以接收高速缓存存储器访问请求，其中补充写入命令用于比高速缓存行小的数据。高速缓存存储器控制器可以响应于写入高速缓存存取访问请求或读取高速缓冲存储器访问请求期间的高速缓存未命中而向未由数据填充的高速缓存行的部分写入补充。在高速缓存未命中的情况下，高速缓存存储器控制器可以从主存储器检索数据，排除任何超取数据，并将数据和补充数据写入高速缓存行。消除过度取消减少了从主存储器中检索数据所需的带宽和功耗。

4. 发明授权

EP3191967B1 CACHE BANK SPREADING FOR COMPRESSION ALGORITHMS 有权
公开(公告)号：EP3191967B1
公开(公告)日：2018-12-26
申请号：EP15747325.7
申请日：2015-07-23
申请人： Qualcomm Incorporated
发明人： PATSILARAS, George , TURNER, Andrew Edmund , RYCHLIK, Bohuslav
IPC分类号： G06F12/0846 , G06F12/0886 , G06F12/0893
CPC分类号： G06F12/0893 , G06F12/0846 , G06F12/0851 , G06F12/0886 , G06F12/1045 , G06F2212/1044 , G06F2212/401
摘要： Aspects include computing devices, systems, and methods for implementing a cache memory access requests for compressed data using cache bank spreading. In an aspect, cache bank spreading may include determining whether the compressed data of the cache memory access fits on a single cache bank. In response to determining that the compressed data fits on a single cache bank, a cache bank spreading value may be calculated to replace/reinstate bank selection bits of the physical address for a cache memory of the cache memory access request that may be cleared during data compression. A cache bank spreading address in the physical space of the cache memory may include the physical address of the cache memory access request plus the reinstated bank selection bits. The cache bank spreading address may be used to read compressed data from or write compressed data to the cache memory device.

5. 发明授权

EP3170084B1 METHOD AND APPARATUS FOR A SHARED CACHE WITH DYNAMIC PARTITIONING 有权
公开(公告)号：EP3170084B1
公开(公告)日：2018-06-06
申请号：EP15734017.5
申请日：2015-06-25
申请人： Qualcomm Incorporated
发明人： PALACHARLA, Subbarao , KHAN, Moinul , ARTIERI, Alain , BHOLE, Kedar , CHAMARTY, Vinod , LI, Yanru , SANKURATRI, Raghu , PATSILARAS, George , THIRUNAGARI, Pavan Kumar , TURNER, Andrew Edmund , WOO, Jeong-Ho
IPC分类号： G06F12/0895 , G06F12/084 , G06F12/0893 , G06F9/50
CPC分类号： G06F12/0893 , G06F1/3203 , G06F1/3275 , G06F1/3287 , G06F9/50 , G06F12/084 , G06F12/0864 , G06F12/0888 , G06F12/0895 , G06F17/30902 , G06F2212/1028 , G06F2212/1044 , G06F2212/152 , G06F2212/601 , G06F2212/6042 , Y02D10/13
摘要： Aspects include computing devices, systems, and methods for dynamically partitioning a system cache by sets and ways into component caches. A system cache memory controller may manage the component caches and manage access to the component caches. The system cache memory controller may receive system cache access requests and reserve locations in the system cache corresponding to the component caches correlated with component cache identifiers of the requests. Reserving locations in the system cache may activate the locations in the system cache for use by a requesting client, and may also prevent other client from using the reserved locations in the system cache. Releasing the locations in the system cache may deactivate the locations in the system cache and allow other clients to use them. A client reserving locations in the system cache may change the amount of locations it has reserved within its component cache.

6. 发明公开

EP3191967A1 CACHE BANK SPREADING FOR COMPRESSION ALGORITHMS 有权
标题翻译：用于压缩算法的CACHE BANK扩展
公开(公告)号：EP3191967A1
公开(公告)日：2017-07-19
申请号：EP15747325.7
申请日：2015-07-23
申请人： Qualcomm Incorporated
发明人： PATSILARAS, George , TURNER, Andrew Edmund , RYCHLIK, Bohuslav
IPC分类号： G06F12/08
CPC分类号： G06F12/0893 , G06F12/0846 , G06F12/0851 , G06F12/0886 , G06F12/1045 , G06F2212/1044 , G06F2212/401
摘要： Aspects include computing devices, systems, and methods for implementing a cache memory access requests for compressed data using cache bank spreading. In an aspect, cache bank spreading may include determining whether the compressed data of the cache memory access fits on a single cache bank. In response to determining that the compressed data fits on a single cache bank, a cache bank spreading value may be calculated to replace/reinstate bank selection bits of the physical address for a cache memory of the cache memory access request that may be cleared during data compression. A cache bank spreading address in the physical space of the cache memory may include the physical address of the cache memory access request plus the reinstated bank selection bits. The cache bank spreading address may be used to read compressed data from or write compressed data to the cache memory device.
摘要翻译：各方面包括用于使用高速缓存存储区扩展来实现对压缩数据的高速缓存存储器访问请求的计算设备，系统和方法。在一个方面，高速缓存存储体扩展可以包括确定高速缓存存储器访问的压缩数据是否适合单个高速缓存存储体。响应于确定压缩数据适合于单个高速缓存存储体，可以计算高速缓存存储体扩展值以替换/恢复可以在数据期间清除的高速缓存存取请求的高速缓存存储器的物理地址的存储体选择位压缩。高速缓冲存储器的物理空间中的高速缓冲存储体扩展地址可以包括高速缓存存取请求的物理地址加上恢复的存储体选择位。高速缓冲存储体扩展地址可用于从高速缓冲存储器设备读取压缩数据或将压缩数据写入高速缓冲存储设备。

7. 发明公开

EP3170084A1 METHOD AND APPARATUS FOR A SHARED CACHE WITH DYNAMIC PARTITIONING 有权
标题翻译：方法和装置与动态分区共同的高速缓存存储器
公开(公告)号：EP3170084A1
公开(公告)日：2017-05-24
申请号：EP15734017.5
申请日：2015-06-25
申请人： Qualcomm Incorporated
发明人： PALACHARLA, Subbarao , KHAN, Moinul , ARTIERI, Alain , BHOLE, Kedar , CHAMARTY, Vinod , LI, Yanru , SANKURATRI, Raghu , PATSILARAS, George , THIRUNAGARI, Pavan Kumar , TURNER, Andrew Edmund , WOO, Jeong-Ho
IPC分类号： G06F12/08 , G06F9/50
CPC分类号： G06F12/0893 , G06F9/50 , G06F12/084 , G06F12/0895 , G06F2212/1044 , G06F2212/152 , G06F2212/601 , G06F2212/6042 , Y02D10/13
摘要： Aspects include computing devices, systems, and methods for dynamically partitioning a system cache by sets and ways into component caches. A system cache memory controller may manage the component caches and manage access to the component caches. The system cache memory controller may receive system cache access requests and reserve locations in the system cache corresponding to the component caches correlated with component cache identifiers of the requests. Reserving locations in the system cache may activate the locations in the system cache for use by a requesting client, and may also prevent other client from using the reserved locations in the system cache. Releasing the locations in the system cache may deactivate the locations in the system cache and allow other clients to use them. A client reserving locations in the system cache may change the amount of locations it has reserved within its component cache.
摘要翻译：方面包括计算设备，系统和方法，用于动态地划分由集和方法的系统的高速缓存成组分缓存。一种系统，高速缓冲存储器控制器可以管理组件的高速缓存和管理对组件的高速缓存。系统高速缓存存储器控制器可以接收在系统缓存对应于与所述请求的组件标识符高速缓存相关联的高速缓存组件的高速缓存系统的访问请求和储备位置。在系统缓存预留的位置可以由请求的客户端激活系统中的高速缓存使用的位置，并且因此可以防止其他客户机使用在系统缓存的保留位置。释放系统缓存中的位置可以停用系统缓存的位置，并允许其他客户机使用。客户端系统中的高速缓存保留位置可以改变它的高速缓存部件中的保留位置的量。

8. 发明公开

EP4378082A1 DATA RE-ENCODING FOR ENERGY-EFFICIENT DATA TRANSFER IN A COMPUTING DEVICE 审中-实审
公开(公告)号：EP4378082A1
公开(公告)日：2024-06-05
申请号：EP22751181.3
申请日：2022-06-17
申请人： QUALCOMM INCORPORATED
发明人： IPEK, Engin , RYCHLIK, Bohuslav , PATSILARAS, George , KULKARNI, Prajakt , HANKENDI, Can , ALI, Fahad , GEMAR, Jeffrey , SEVERSON, Matthew
IPC分类号： H03M7/04 , H03M5/14 , G06F13/00 , G06F9/00 , G11C7/10 , H03M7/30
CPC分类号： H03M7/6047 , H03M7/04 , H03M5/145 , G11C7/1006 , Y02D10/00

9. 发明公开

EP4226251A1 READ OPTIONAL AND WRITE OPTIONAL COMMANDS 审中-实审
公开(公告)号：EP4226251A1
公开(公告)日：2023-08-16
申请号：EP21778649.0
申请日：2021-09-02
申请人： QUALCOMM INCORPORATED
发明人： TURNER, Andrew Edmund , PATSILARAS, George , MA, Zhenbiao , PALACHARLA, Subbarao , RYCHLIK, Bohuslav , ZGHAL, Tarek , KOOB, Christopher
IPC分类号： G06F13/36

10. 发明公开

EP3256946A1 METHODS OF SELECTING AVAILABLE CACHE IN MULTIPLE CLUSTER SYSTEM 审中-公开
标题翻译：在多个集群系统中选择可用高速缓存的方法
公开(公告)号：EP3256946A1
公开(公告)日：2017-12-20
申请号：EP15813677.0
申请日：2015-12-10
申请人： Qualcomm Incorporated
发明人： WANG, Feng , RYCHLIK, Bohuslav , PATSILARAS, George , TURNER, Andrew Edmund , ROHILLAH, Anwar Quinones
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F12/0851 , G06F12/0875 , G06F12/0897 , G06F2212/1021 , G06F2212/283 , G06F2212/608 , Y02D10/13
摘要： Aspects include computing devices, systems, and methods for implementing selecting an available shared cache memory as a victim cache. The computing device may identify a remote shared cache memory with available shared cache memory space for use as the victim cache. To select the appropriate available shared cache memory, the computing device may retrieve data for the identified remote shared cache memory or a processor cluster associated with the identified remote shared cache memory relating to a metric, such as performance speed, efficiency, or effective victim cache size. Using the retrieved data, the computing device may determine the identified remote shared cache memory to use as the victim cache and select the determined remote shared cache memory to use as the victim cache.

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