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11. 发明公开

EP2779228A2 Semiconductor package having an over-temperature protection circuit utilizing multiple temperature threshold values 有权转让
标题翻译： Halbleitergehäusemit einerÜbertemperaturschutzschaltungunter Verwendung mehrfacher Temperaturschwellwerte
公开(公告)号：EP2779228A2
公开(公告)日：2014-09-17
申请号：EP14156513.5
申请日：2014-02-25
申请人： International Rectifier Corporation
发明人： Fernando, Dean , Barbosa, Roel
IPC分类号： H01L23/34
摘要： According to an exemplary implementation, a semiconductor package includes a multi-phase power inverter having power switches and situated on a leadframe of the semiconductor package. The semiconductor package further includes an over-temperature protection circuit configured to reduce current through the power switches based on multiple temperature threshold values of the power switches and a sensed temperature of the power switches. The over-temperature protection circuit can be configured to enter first and second modes based on the multiple temperature threshold values and the sensed temperature, where the second mode reduces current through the power switches to a greater extent than the first mode.
摘要翻译：根据示例性实施例，半导体封装包括具有电源开关并位于半导体封装的引线框架上的多相电力逆变器。半导体封装还包括过温保护电路，其被配置为基于功率开关的多个温度阈值和功率开关的感测温度来减小通过功率开关的电流。过温保护电路可以被配置为基于多个温度阈值和感测温度进入第一和第二模式，其中第二模式通过电力开关将电流降低到比第一模式更大的程度。

12. 发明公开

EP2775520A2 Open source Power Quad Flat No-Lead (PQFN) leadframe 有权转让
标题翻译：开源电源四通无引线（PQFN）-Leitungsrahmen
公开(公告)号：EP2775520A2
公开(公告)日：2014-09-10
申请号：EP14150001.7
申请日：2014-01-01
申请人： International Rectifier Corporation
发明人： Fernando, Dean , Barbosa, Roel , Takahashi, Toshio
IPC分类号： H01L23/495
CPC分类号： H01L23/49575 , H01L23/4952 , H01L23/49548 , H01L23/49582 , H01L2224/0603 , H01L2224/32245 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/4903 , H01L2224/49171 , H01L2224/73265 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/181 , H01L2924/30111 , H02M7/003 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： According to an exemplary implementation, a power quad flat no-lead (PQFN) leadframe includes U-phase, V-phase, and W-phase power switches situated on the PQFN leadframe. A drain of the U-phase power switch is connected to a U-phase output strip of the PQFN leadframe. A source of the U-phase power switch is connected to a U-phase current sense terminal. The U-phase output strip can substantially traverse across the PQFN leadframe. Another U-phase power switch is situated on the PQFN leadframe with a source of the another U-phase power switch connected to the U-phase output strip of the PQFN leadframe. The PQFN leadframe can include a leadframe island within the U-phase output strip. At least one wirebond may be connected to the U-phase output strip.
摘要翻译：根据示例性实现，功率四边形无引线（PQFN）引线框架包括位于PQFN引线框架上的U相，V相和W相功率开关。 U相电源开关的漏极连接到PQFN引线框的U相输出条。 U相电源开关的源极连接到U相电流检测端子。 U相输出条可以基本横穿PQFN引线框。另一个U相电源开关位于PQFN引线框架上，另一个U相电源开关的源极连接到PQFN引线框架的U相输出条。 PQFN引线框架可以包括U相输出条带内的引线框岛。至少一个引线键可以连接到U相输出条。

13. 发明公开

EP2629334A3 Power transistor having segmented gate 失效转让
标题翻译： Leistungstransistor mit segmentiertem门
公开(公告)号：EP2629334A3
公开(公告)日：2014-07-16
申请号：EP13153373.9
申请日：2013-01-31
申请人： International Rectifier Corporation
发明人： Briere, Michael A. , Thapar, Naresh
IPC分类号： H01L29/778 , H01L29/423 , H01L21/335
CPC分类号： H01L29/778 , H01L29/2003 , H01L29/42368 , H01L29/66431 , H01L29/66462 , H01L29/66477 , H01L29/7787 , H01L29/78
摘要： There are disclosed herein various implementations of a transistor having a segmented gate region. Such a transistor may include at least one segmentation dielectric segment and two or more gate dielectric segments. The segmentation dielectric segment or segments are thicker than the gate dielectric segments, and is/are situated between the gate dielectric segments. The segmentation dielectric segment or segments cause an increase in the effective gate length so as to improve resistance to punch-through breakdown between a drain electrode and a source electrode of the transistor when the transistor is off.
摘要翻译：这里公开了具有分段栅极区域的晶体管的各种实现方式。这种晶体管可以包括至少一个分割电介质段和两个或更多个栅极电介质段。分段电介质段或段比栅介质段更厚，并且位于栅电介质段之间。分段电介质段或段导致有效栅极长度的增加，以便当晶体管截止时，提高晶体管的漏电极和源极之间的穿通击穿阻力。

14. 发明公开

EP2469583A3 Stress modulated group iii-v semiconductor device and related method 有权转让
标题翻译：应力调制III-V族半导体器件及相关方法
公开(公告)号：EP2469583A3
公开(公告)日：2013-09-18
申请号：EP11189846.6
申请日：2011-11-18
申请人： International Rectifier Corporation
发明人： Chandolu, Anilkumar , Birkhahn, Ronald H. , Larsen, Troy , Hughes, Brett , Hoff, Steve , Nelson, Scott , Brown, Robert , Sass, Leanne
IPC分类号： H01L21/335 , H01L29/778 , H01L29/20
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/205 , H01L29/66431
摘要： According to one embodiment, a group III-V semiconductor device comprises a compositionally graded body disposed over a substrate and below a buffer layer supporting an active area of the group III-V semiconductor device. The compositionally graded body includes a first region applying compressive stress to the substrate. The compositionally graded body further includes a stress modulating region over the first region, where the stress modulating region applies tensile stress to the substrate. In one embodiment, a method for fabricating a group III-V semiconductor device comprises providing a substrate for the group III-V semiconductor device and forming a first region of a compositionally graded body over the substrate to apply compressive stress to the substrate. The method further comprises forming a stress modulating region of the compositionally graded body over the first region, where the stress modulating region applies tensile stress to the substrate.

15. 发明公开

EP2525394A1 Thermally enhanced semiconductor package with exposed conductive clip 有权转让
标题翻译：半导体封装用感谢的暴露终端良好的热性能
公开(公告)号：EP2525394A1
公开(公告)日：2012-11-21
申请号：EP12165278.8
申请日：2012-04-24
申请人： International Rectifier Corporation
发明人： Cho, Eung San
IPC分类号： H01L21/48 , H01L23/492 , H01L23/495
CPC分类号： H01L23/49568 , H01L21/78 , H01L23/3735 , H01L23/49524 , H01L23/49562 , H01L23/49575 , H01L23/49844 , H01L24/37 , H01L24/40 , H01L24/48 , H01L24/49 , H01L24/84 , H01L24/97 , H01L25/072 , H01L25/18 , H01L2224/05554 , H01L2224/0603 , H01L2224/37147 , H01L2224/40095 , H01L2224/40137 , H01L2224/40139 , H01L2224/40225 , H01L2224/40227 , H01L2224/48227 , H01L2224/49171 , H01L2224/73221 , H01L2224/84801 , H01L2224/8485 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/1306 , H01L2924/15787 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： One exemplary disclosed embodiment comprises a semiconductor package including an inside pad, a transistor (240,260), and a conductive clip (280) coupled to the inside pad (212c) and a terminal of the transistor. A top surface of the conductive clip is substantially exposed at the top of the package, and a side surface of the conductive clip is exposed at a side of the package. By supporting the semiconductor package on an outside pad (212e) during the fabrication process and by removing the outside pad during singulation, the conductive clip may be kept substantially parallel and in alignment with the package substrate while optimizing the package form factor compared to conventional packages. The exposed top surface of the conductive clip may be further attached to a heat sink for enhanced thermal dissipation.
摘要翻译：一个示范实施例游离缺失盘包括一半导体封装，其包括上内垫，晶体管（240.260），以及耦合到所述内部焊盘（212C）和所述晶体管的端子的导电夹（280）。导电夹的顶表面基本上是暴露在封装的顶部，和导电夹子的侧表面在包装的一个侧面露出。由上到在制造过程期间外垫（212E）以及通过去除单颗化期间外部衬垫支承的半导体封装，同时优化了包形式因子相比于传统的包中的导电夹可以保持基本上与所述封装基板平行和对齐，导电夹的暴露的顶表面可以被进一步附接至散热器，用于增强散热。

16. 发明公开

EP2518880A2 Integrated power stage 有权转让
标题翻译： Integrierte Stromstufe
公开(公告)号：EP2518880A2
公开(公告)日：2012-10-31
申请号：EP12165466.9
申请日：2012-04-25
申请人： International Rectifier Corporation
发明人： Briere, Michael A.
IPC分类号： H02M7/00
CPC分类号： H02M7/003 , H01L21/8258 , H01L24/13 , H01L24/16 , H01L27/0688 , H01L27/085 , H01L27/092 , H01L2224/16227 , H01L2224/16265 , H01L2924/19041 , H01L2924/19042 , H01L2924/19104
摘要： In one implementation, an integrated power stage includes a common die situated over a load stage, the common die includes a driver stage and power switches. The power switches include a control transistor and a sync transistor. A drain of the control transistor receives an input voltage of the common die on one side (e.g., on a top surface) of the common die. A source of the control transistor is coupled to a drain of the sync transistor and provides an output voltage of the common die on an opposite side (e.g., on a bottom surface) of the common die. An interposer may be included under the power stage and includes an output inductor and optionally an output capacitor coupled to the output voltage of the common die on the opposite side of the common die.
摘要翻译：在一个实现中，集成功率级包括位于负载级上的公共管芯，公共管芯包括驱动器级和功率开关。电源开关包括控制晶体管和同步晶体管。控制晶体管的漏极在公共管芯的一侧（例如，在顶表面上）接收公共管芯的输入电压。控制晶体管的源极耦合到同步晶体管的漏极，并且在公共管芯的相对侧（例如，在底表面上）提供公共管芯的输出电压。插入器可以包括在功率级之下，并且包括输出电感器和可选地与公共管芯的相对侧上的公共管芯的输出电压耦合的输出电容器。

17. 发明公开

EP2515332A2 Bondwireless Power Module with Three-Dimensional Current Routing 有权转让
标题翻译： BondWireless-Strommodul mit Dreidimensionalem Strom-Routing
公开(公告)号：EP2515332A2
公开(公告)日：2012-10-24
申请号：EP12159773.6
申请日：2012-03-15
申请人： International Rectifier Corporation
发明人： Hauenstein, Henning M. , Gorgerino, Andrea
IPC分类号： H01L23/498
摘要： According to an exemplary embodiment, a bondwireless power module includes a common output pad coupling an emitter/anode node of a high side device to a collector/cathode node of a low side device. The bondwireless power module also includes a high side conductive clip connecting a collector of the high side device to a cathode of the high side device, and causing current to traverse through the high side conductive clip to another high side conductive clip in another power module. The bondwireless power module further includes a low side conductive clip connecting an emitter of the low side device to an anode of the low side device, and causing current to traverse through the low side conductive clip to another low side conductive clip in the another power module. The bondwireless power module can be a motor drive inverter module.
摘要翻译：根据示例性实施例，无焊丝功率模块包括将高侧器件的发射极/阳极节点耦合到低侧器件的集电极/阴极节点的公共输出焊盘。无接线电源模块还包括将高侧器件的集电极连接到高侧器件的阴极的高侧导电夹子，并使电流穿过高侧导电夹子穿过另一个电源模块中的另一个高侧导电夹子。无键电源模块还包括将低侧器件的发射极连接到低侧器件的阳极的低侧导电夹子，并使电流穿过低侧导电夹子穿过另一功率模块中的另一低侧导电夹。无键电源模块可以是电机驱动逆变器模块。

18. 发明公开

EP2511952A1 Stacked composite device including a group III-V transistor and a group IV vertical transistor 有权转让
标题翻译：具有处于组装结构的III-V族晶体管和垂直晶体管的IV族堆叠式装置
公开(公告)号：EP2511952A1
公开(公告)日：2012-10-17
申请号：EP12163106.3
申请日：2012-04-04
申请人： International Rectifier Corporation
发明人： McDonald, Tim , Briere, Michael A.
IPC分类号： H01L25/07 , H03K17/567
CPC分类号： H01L25/074 , H01L2224/48091 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/30107 , H03K17/567 , H01L2924/00014 , H01L2924/00
摘要： In one implementation, a stacked composite device comprises a group IV vertical transistor and a group III-V transistor stacked over the group IV vertical transistor. A drain of the group IV vertical transistor is in contact with a source of the group III-V transistor, a source of the group IV vertical transistor is coupled to a gate of the group III-V transistor to provide a composite source on a bottom side of the stacked composite device, and a drain of the group III-V transistor provides a composite drain on a top side of the stacked composite device. A gate of the group IV vertical transistor provides a composite gate on the top side of the stacked composite device.
摘要翻译：在一个实现中，叠层型的复合装置包括IV族垂直晶体管和堆叠在组IV的垂直晶体管一III-V族晶体管。 IV族垂直晶体管的漏极与所述III-V族晶体管的源极，该组IV垂直晶体管耦合到所述III-V族晶体管的栅极的源极，以在底部提供复合源极接触该叠层型的复合元件，并且III-V族晶体管的漏极的侧面提供关于叠层型的复合设备的顶侧的复合漏极。 IV族垂直晶体管的栅极提供在层叠复合设备的顶侧上的复合栅。

19. 发明公开

EP2503692A1 Composite Semiconductor Device with Higher Threshold Voltage 有权转让
标题翻译： Zusammengesetzte Halbleitervorrichtung mit hoher Schwellenspannung
公开(公告)号：EP2503692A1
公开(公告)日：2012-09-26
申请号：EP12159775.1
申请日：2012-03-15
申请人： International Rectifier Corporation
发明人： Zhang, Jason
IPC分类号： H03K17/567 , H03K17/16 , H03K17/10 , H03K17/30
CPC分类号： H03K17/30 , H03K17/107 , H03K17/168 , H03K17/567 , H03K2017/6875
摘要： There are disclosed herein various implementations of composite III-nitride semiconductor devices having turn-on prevention control. In one exemplary implementation, a normally OFF composite semiconductor device comprises a normally ON III-nitride power transistor (110) and a low voltage (LV) device (120) cascoded with the normally ON III-nitride power transistor to form the normally OFF composite semiconductor device. The LV device (120) is configured to have a noise-resistant threshold voltage to provide the turn-on prevention control for the normally OFF composite semiconductor device by preventing noise current from flowing through a channel of the normally ON III-nitride power transistor in a noisy system.
摘要翻译：这里公开了具有开启防止控制的复合III族氮化物半导体器件的各种实现方式。在一个示例性实施方式中，正常关闭复合半导体器件包括正常的III族氮化物功率晶体管（110）和与正常的III族氮化物功率晶体管共模形成的常态OFF复合材料的低电压（LV）器件（120）半导体器件。 LV装置（120）被配置为具有抗噪声阈值电压，以通过防止噪声电流流过正常导通的III族氮化物功率晶体管的沟道来为正常关闭复合半导体器件提供导通防止控制一个嘈杂的系统。

20. 发明公开

EP2503691A1 High Voltage Composite Semiconductor Device with Protection for a Low Voltage Device 有权转让
标题翻译：高电压与低电压对一个装置保护复合半导体器件
公开(公告)号：EP2503691A1
公开(公告)日：2012-09-26
申请号：EP12159774.4
申请日：2012-03-15
申请人： International Rectifier Corporation
发明人： Zhang, Jason , Bramian, Tony
IPC分类号： H03K17/567 , H03K17/74 , H03K17/16 , H03K17/081 , H03K17/10
CPC分类号： H03K17/08116 , H03K17/107 , H03K17/567
摘要： There are disclosed herein various implementations of composite semiconductor devices including a voltage protected device. In one exemplary implementation, a normally OFF composite semiconductor device comprises a normally ON III-nitride power transistor (310) having a first output capacitance (C1)(318), and a low voltage (LV) device (320) cascoded with the normally ON III-nitride power transistor to form the normally OFF composite semiconductor device (300), the LV device having a second output capacitance (C2)(348). A ratio of the first output capacitance to the second output capacitance is set based on a ratio of a drain voltage of the normally ON III-nitride power transistor to a breakdown voltage of the LV device so as to provide voltage protection for the LV device.
摘要翻译：有在包括电压保护装置的复合半导体装置的各种实施方式中游离缺失光盘。与常串接在一个示例性的实施方式中，常关闭复合半导体器件包括具有第一输出电容（C1）（318），和低电压的常开III族氮化物功率晶体管（310）（LV）器件（320） ON III族氮化物功率晶体管以形成常关闭型复合半导体装置（300），具有第二输出电容（C2）（348）的LV设备。第一输出电容与第二输出电容的比例是基于正常的漏极电压ON III族氮化物功率晶体管的到LV器件的击穿电压的比率设定成提供用于LV器件电压保护。

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