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11. 发明公开

EP0390453A3 Circuitry and method for providing an output signal indicative of the time delay between two asynchronous clock signals 失效
标题翻译：用于提供两个异步时钟信号之间时间延迟的输出信号的电路和方法
公开(公告)号：EP0390453A3
公开(公告)日：1992-06-17
申请号：EP90303171.4
申请日：1990-03-23
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： McClure, David Charles , Lysinger, Mark Alan
IPC分类号： G06F5/06 , G01R29/02
CPC分类号： G06F5/12 , G01R29/0273 , G06F7/026 , G06F2205/126
摘要： In the preferred embodiment of the invention, a first-in, first-out (FIFO) memory includes flag generation circuitry which utilizes a write clock counter and a read clock counter to provide the number of write clock pulses received. since the previous write reset signal and the number of read clock pulses received by the FIFO since the previous read reset signal. A subtractor circuit subtracts the number of read clock pulses from the number of write clock pulses, and this difference is compared in a comparator circuit to determine if the difference is greater than a preset value. This determination provides the information as to the relative fullness of the FIFO.

12. 发明公开

EP0837562A3 A precharging output driver circuit 失效
标题翻译：预充电输出驱动器电路
公开(公告)号：EP0837562A3
公开(公告)日：1998-05-20
申请号：EP98100115.9
申请日：1992-12-16
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： McClure, David Charles , Lysinger, Mark Alan , Slemmer, William Carl
IPC分类号： H03K19/003 , H03K19/017 , G11C7/00
CPC分类号： H03K19/00361
摘要： A push-pull output driver circuit is disclosed which includes control circuitry for controlling the gates of the driver transistors to effect precharge of the output terminal at the beginning of a cycle. Precharge is initiated at the beginning of each cycle, for example indicated by an address transition. The prior data state at the output is stored, and enables the opposing driver transistor from that which drove the stored prior data state by enabling a gated level detector with hysteresis, such as a Schmitt trigger, associated therewith. The transistor that drove the stored prior data state is disabled, thus precluding oscillations during precharge. The gated Schmitt triggers each receive the voltage of the output terminal and, when enabled, turn on a transistor which couples the output terminal to the gate of the driver transistor. The Schmitt triggers also control the precharge to terminate when the output terminal has reached an intermediate voltage, and so that oscillations are minimized as a result of the hysteresis characteristic. Connection of the output terminal to the gate of the precharging driver transistor helps to eliminate overshoot during precharge.
摘要翻译：公开了一种推挽输出驱动器电路，其包括控制电路，用于控制驱动器晶体管的栅极以在周期开始时对输出端子进行预充电。预充电在每个周期开始时启动，例如由地址转换指示。存储输出端处的先前数据状态，并且通过启用具有滞后的门控电平检测器（例如与之相关联的施密特触发器）来启用与驱动所存储的在先数据状态的驱动晶体管相反的驱动晶体管。驱动所存储的先前数据状态的晶体管被禁用，因此排除了预充电期间的振荡。门控施密特触发每个接收输出端子的电压，并且当被使能时，导通将输出端子耦合到驱动晶体管的栅极的晶体管。施密特触发器还控制预充电，当输出端子达到中间电压时终止，并且由于滞后特性而使振荡最小化。输出端连接到预充电驱动晶体管的栅极有助于消除预充电期间的过冲。

13. 发明公开

EP0745859A3 Configurable probe pads to facilitate parallel testing of integrated circuit devices 失效
标题翻译：用于集成电路的容易平行测试配置的接触带
公开(公告)号：EP0745859A3
公开(公告)日：1997-08-06
申请号：EP96302949.1
申请日：1996-04-26
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Brannigan, Michael Joseph , Lysinger, Mark Alan , McClure, David Charles
IPC分类号： G01R1/04
CPC分类号： G01R31/2884 , G01R31/2831 , G11C29/48
摘要： According to the present invention, parallel testing of integrated circuit devices are facilitated such that it is not necessary that integrated circuit devices to be parallel tested be "ends only" devices. A side pad located along the sides, rather than the ends, of the integrated circuit device is electrically connected by muitiplexing circuitry to a corresponding configurable probe pad located along the ends of the device. During parallel testing of the device, the side pad is effectively tested when the configurable probe pad is probed and tested. While the configurable probe pad is tested during parallel testing, the side pad is not directly exercised. Following parallel testing, the side pad is bonded to the device package but the configurable probe pad is not bonded to the device package.

14. 发明授权

EP0437081B1 Redundancy for serial memory 失效
标题翻译：冗余串行存储器
公开(公告)号：EP0437081B1
公开(公告)日：1997-04-23
申请号：EP90314116.6
申请日：1990-12-21
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： McClure, David Charles , Lysinger, Mark Alan
IPC分类号： G06F11/20
CPC分类号： G11C29/86 , G11C8/04

15. 发明公开

EP0390453A2 Circuitry and method for providing an output signal indicative of the time delay between two asynchronous clock signals 失效
标题翻译：电路和方法，用于为两个异步时钟之间的时间延迟的代表性的恢复信号的输出信号。
公开(公告)号：EP0390453A2
公开(公告)日：1990-10-03
申请号：EP90303171.4
申请日：1990-03-23
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： McClure, David Charles , Lysinger, Mark Alan
IPC分类号： G06F5/06 , G01R29/02
CPC分类号： G06F5/12 , G01R29/0273 , G06F7/026 , G06F2205/126
摘要： In the preferred embodiment of the invention, a first-in, first-out (FIFO) memory includes flag generation circuitry which utilizes a write clock counter and a read clock counter to provide the number of write clock pulses received. since the previous write reset signal and the number of read clock pulses received by the FIFO since the previous read reset signal. A subtractor circuit subtracts the number of read clock pulses from the number of write clock pulses, and this difference is compared in a comparator circuit to determine if the difference is greater than a preset value. This determination provides the information as to the relative fullness of the FIFO.
摘要翻译：在本发明的优选实施方式，以先入，先出（FIFO）存储器包括标志生成电路，其利用写时钟计数器和读时钟计数器，以提供接收到的写时钟脉冲的数目。由于先前的写复位信号和从先前读出的复位信号由FIFO接收的读出时钟脉冲数。减法器电路中减去从写入时钟脉冲数读出时钟脉冲的数量，并且该差值与一个比较器电路，以确定性矿如果该差大于预先设定的值大。这种判断提供信息到FIFO的相对丰满。

16. 发明公开

EP0390452A2 Synchronization circuit using N-bit counters in a memory circuit 失效
标题翻译： Synchronisationsschaltung。
公开(公告)号：EP0390452A2
公开(公告)日：1990-10-03
申请号：EP90303170.6
申请日：1990-03-23
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： McClure, David Charles , Lysinger, Mark Alan
IPC分类号： H03K3/037 , H03K23/50 , H04J3/06
CPC分类号： H04J3/0626
摘要： The synchronization circuit of the preferred embodiment is a T flip flop which has a first output which changes state on the leading edge of the clock signal, and a second output which changes state on the trailing edge of the clock signal. The T flip flop has an exclusive OR gate input in which the T input is combined with the first output. The output of the exclusive OR is coupled to an internal node when the clock signal is at a first logic state, and isolated from the internal node when the clock signal is at a second logic state. The internal node is coupled to the first output when the clock signal is at the second logic state and isolated from the internal node when the clock signal is at the first logic state. The first output signal is coupled to the second output signal when the clock signal is at the first logic state, and isolated from the second output terminal when the clock signal is at the second logic state.
摘要翻译：优选实施例的同步电路是T触发器，其具有改变时钟信号的前沿上的状态的第一输出和改变时钟信号后沿状态的第二输出。 T触发器具有异或门输入，其中T输入与第一输出相结合。当时钟信号处于第一逻辑状态时，异或的输出耦合到内部节点，并且当时钟信号处于第二逻辑状态时，该异或的输出与内部节点隔离。当时钟信号处于第一逻辑状态时，内部节点耦合到第一输出，当时钟信号处于第二逻辑状态并且当时钟信号处于第一逻辑状态时与内部节点隔离。当时钟信号处于第一逻辑状态时，第一输出信号耦合到第二输出信号，并且当时钟信号处于第二逻辑状态时与第二输出端隔离。

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