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11. 发明公开

EP0390452A2 Synchronization circuit using N-bit counters in a memory circuit 失效
标题翻译： Synchronisationsschaltung。
公开(公告)号：EP0390452A2
公开(公告)日：1990-10-03
申请号：EP90303170.6
申请日：1990-03-23
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： McClure, David Charles , Lysinger, Mark Alan
IPC分类号： H03K3/037 , H03K23/50 , H04J3/06
CPC分类号： H04J3/0626
摘要： The synchronization circuit of the preferred embodiment is a T flip flop which has a first output which changes state on the leading edge of the clock signal, and a second output which changes state on the trailing edge of the clock signal. The T flip flop has an exclusive OR gate input in which the T input is combined with the first output. The output of the exclusive OR is coupled to an internal node when the clock signal is at a first logic state, and isolated from the internal node when the clock signal is at a second logic state. The internal node is coupled to the first output when the clock signal is at the second logic state and isolated from the internal node when the clock signal is at the first logic state. The first output signal is coupled to the second output signal when the clock signal is at the first logic state, and isolated from the second output terminal when the clock signal is at the second logic state.
摘要翻译：优选实施例的同步电路是T触发器，其具有改变时钟信号的前沿上的状态的第一输出和改变时钟信号后沿状态的第二输出。 T触发器具有异或门输入，其中T输入与第一输出相结合。当时钟信号处于第一逻辑状态时，异或的输出耦合到内部节点，并且当时钟信号处于第二逻辑状态时，该异或的输出与内部节点隔离。当时钟信号处于第一逻辑状态时，内部节点耦合到第一输出，当时钟信号处于第二逻辑状态并且当时钟信号处于第一逻辑状态时与内部节点隔离。当时钟信号处于第一逻辑状态时，第一输出信号耦合到第二输出信号，并且当时钟信号处于第二逻辑状态时与第二输出端隔离。

12. 发明公开

EP0837562A2 A precharging output driver circuit 失效
标题翻译： Ausgangspufferschaltung mit Vorladung
公开(公告)号：EP0837562A2
公开(公告)日：1998-04-22
申请号：EP98100115.9
申请日：1992-12-16
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： McClure, David Charles , Lysinger, Mark Alan , Slemmer, William Carl
IPC分类号： H03K19/003 , H03K19/017 , G11C7/00
CPC分类号： H03K19/00361
摘要： A push-pull output driver circuit is disclosed which includes control circuitry for controlling the gates of the driver transistors to effect precharge of the output terminal at the beginning of a cycle. Precharge is initiated at the beginning of each cycle, for example indicated by an address transition. The prior data state at the output is stored, and enables the opposing driver transistor from that which drove the stored prior data state by enabling a gated level detector with hysteresis, such as a Schmitt trigger, associated therewith. The transistor that drove the stored prior data state is disabled, thus precluding oscillations during precharge. The gated Schmitt triggers each receive the voltage of the output terminal and, when enabled, turn on a transistor which couples the output terminal to the gate of the driver transistor. The Schmitt triggers also control the precharge to terminate when the output terminal has reached an intermediate voltage, and so that oscillations are minimized as a result of the hysteresis characteristic. Connection of the output terminal to the gate of the precharging driver transistor helps to eliminate overshoot during precharge.
摘要翻译：公开了一种推挽输出驱动器电路，其包括控制电路，用于控制驱动晶体管的栅极以在一个周期开始时实现输出端子的预充电。预充电在每个周期开始时启动，例如由地址转换指示。存储输出端的先前数据状态，并通过启用与其相关联的具有滞后的门控电平检测器（例如施密特触发器）使相对的驱动器晶体管能够驱动存储的先前数据状态。驱动存储的先前数据状态的晶体管被禁用，从而阻止在预充电期间的振荡。门控施密特触发器每个都接收输出端子的电压，并且在使能时，打开将输出端子耦合到驱动晶体管的栅极的晶体管。当输出端子达到中间电压时，施密特触发器也可控制预充电，从而由于滞后特性使振荡最小化。将输出端子连接到预充电驱动晶体管的栅极有助于在预充电期间消除过冲。

13. 发明公开

EP0760518A3 Circuitry and methodology to test single bit failures of integrated circuit memory devices 失效
标题翻译：用于测试集成电路存储器件的单比特故障的电路和方法
公开(公告)号：EP0760518A3
公开(公告)日：1997-03-26
申请号：EP96305856.5
申请日：1996-08-09
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： McClure, David Charles , Lysinger, Mark Alan , Sigmund, Frank Josef , Michlowsky, John Anthony
IPC分类号： G11C29/00
CPC分类号： G11C29/30 , G11C29/04
摘要： According to the present invention, a structure and method for analyzing single bit failures of an integrated circuit memory device is disclosed. According to the method for analyzing a single bit failure of an integrated circuit memory device, a test mode is entered, bitline load devices of the integrated circuit memory device are turned off, a single bit of the integrated circuit memory device is selected, the device is placed into a write mode, a plurality of bitlines true and a plurality of bitlines complement of the integrated circuit memory device not associated with the single bit are then set to a low logic level, the bitline true and the bitline complement associated with the single bit is connected to a supply bus and a supply complement bus which is connected to test pads. Finally, the electrical characteristics of the single bit can be monitored on the test pads. According to the structure of the present invention, bitline load devices of the integrated circuit memory device are controlled by a test mode signal, the state of which determines when the test mode will be entered. These bitline load devices are connected to the bitlines true and complement which in turn are connected to the memory cell. Select devices, such as column select transistors, are connected to the bitline true and bitline complement; they are also connected to driver circuitry by a bus, such as a write bus, a read bus or a write/read bus. The driver circuitry is supplied with supply voltages as well as data signals. Further, a buffer circuit allows bitlines true and bitlines complement not associated with the single bit being tested to be pulled to a logic low level. A dummy structure also provides the opportunity to directly monitor the bitlines of the integrated circuit memory device without the need for microprobing.
摘要翻译：根据本发明，公开了一种用于分析集成电路存储器件的单位故障的结构和方法。根据用于分析集成电路存储器件的单位故障的方法，进入测试模式，关闭集成电路存储器件的位线负载设备，选择集成电路存储器件的单个位，设备被置于写入模式，真集中的多个位线和与该单个位不相关的集成电路存储器装置的多个位线补充被设置为低逻辑电平，位线真和位线补充与单个位连接到电源总线和连接到测试焊盘的电源补充总线。最后，可以在测试焊盘上监测单个位的电气特性。根据本发明的结构，集成电路存储器件的位线负载设备由测试模式信号控制，测试模式信号的状态决定何时将进入测试模式。这些位线负载器件连接到位线真正的和补充的，其又连接到存储器单元。选择器件，例如列选择晶体管，连接到位线真和位线补充; 它们也通过诸如写总线，读总线或写/读总线之类的总线连接到驱动器电路。驱动器电路提供电源电压以及数据信号。此外，缓冲器电路允许位线真实，并且与被测试的单个位无关的位线补充被拉至逻辑低电平。虚拟结构还提供了直接监视集成电路存储器器件的位线的机会，而不需要微调。

14. 发明公开

EP0760518A2 Circuitry and methodology to test single bit failures of integrated circuit memory devices 失效
标题翻译：装置和方法用于在存储器集成电路单个比特的测试
公开(公告)号：EP0760518A2
公开(公告)日：1997-03-05
申请号：EP96305856.5
申请日：1996-08-09
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： McClure, David Charles , Lysinger, Mark Alan , Sigmund, Frank Josef , Michlowsky, John Anthony
IPC分类号： G11C29/00
CPC分类号： G11C29/30 , G11C29/04
摘要： According to the present invention, a structure and method for analyzing single bit failures of an integrated circuit memory device is disclosed. According to the method for analyzing a single bit failure of an integrated circuit memory device, a test mode is entered, bitline load devices of the integrated circuit memory device are turned off, a single bit of the integrated circuit memory device is selected, the device is placed into a write mode, a plurality of bitlines true and a plurality of bitlines complement of the integrated circuit memory device not associated with the single bit are then set to a low logic level, the bitline true and the bitline complement associated with the single bit is connected to a supply bus and a supply complement bus which is connected to test pads. Finally, the electrical characteristics of the single bit can be monitored on the test pads. According to the structure of the present invention, bitline load devices of the integrated circuit memory device are controlled by a test mode signal, the state of which determines when the test mode will be entered. These bitline load devices are connected to the bitlines true and complement which in turn are connected to the memory cell. Select devices, such as column select transistors, are connected to the bitline true and bitline complement; they are also connected to driver circuitry by a bus, such as a write bus, a read bus or a write/read bus. The driver circuitry is supplied with supply voltages as well as data signals. Further, a buffer circuit allows bitlines true and bitlines complement not associated with the single bit being tested to be pulled to a logic low level. A dummy structure also provides the opportunity to directly monitor the bitlines of the integrated circuit memory device without the need for microprobing.
摘要翻译：。根据本发明，一种结构和方法，用于分析的集成电路存储器装置的单个位故障是游离缺失盘。。根据用于分析的集成电路存储器装置的单个位失效的方法中，测试模式输入，该集成电路存储设备的位线的负载装置断开，集成电路存储器装置的单个位被选择时，该装置被置于写模式，位线真多元性而不是与单个比特相关联的集成电路存储器装置的位线补体的多元随后设置为低逻辑电平，位线真，并与单个相关联的位线补位被连接到被连接到测试焊盘的电源总线和电源总线的补全部。最后，将单个位的电特性可以在测试焊盘进行监测。。根据本发明的结构中，集成电路存储器件的位线负荷装置由测试模式信号控制，这bestimmt的状态。当测试模式将被输入。这些位线负载装置连接到所述位线真和补充而这又被连接到存储单元。选择装置，颜色：如列选择晶体管，连接到所述位线真值和位线补码; 它们被如此通过总线连接到驱动器电路，检查作为写总线，读总线或读/写总线上。该驱动器电路提供的电源电压以及数据信号。此外，缓冲电路允许位线真和位线补不与被测试的单个位被拉到逻辑低电平相关联。甲虚设所以结构提供了机会，直接监视集成电路存储器件的位线，而无需微探针。

15. 发明公开

EP0390452A3 Synchronization circuit using N-bit counters in a memory circuit 失效
标题翻译：同步电路
公开(公告)号：EP0390452A3
公开(公告)日：1992-08-26
申请号：EP90303170.6
申请日：1990-03-23
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： McClure, David Charles , Lysinger, Mark Alan
IPC分类号： H03K3/037 , H03K23/50 , H04J3/06
CPC分类号： H04J3/0626
摘要： The synchronization circuit of the preferred embodiment is a T flip flop which has a first output which changes state on the leading edge of the clock signal, and a second output which changes state on the trailing edge of the clock signal. The T flip flop has an exclusive OR gate input in which the T input is combined with the first output. The output of the exclusive OR is coupled to an internal node when the clock signal is at a first logic state, and isolated from the internal node when the clock signal is at a second logic state. The internal node is coupled to the first output when the clock signal is at the second logic state and isolated from the internal node when the clock signal is at the first logic state. The first output signal is coupled to the second output signal when the clock signal is at the first logic state, and isolated from the second output terminal when the clock signal is at the second logic state.

16. 发明公开

EP0390453A3 Circuitry and method for providing an output signal indicative of the time delay between two asynchronous clock signals 失效
标题翻译：用于提供两个异步时钟信号之间时间延迟的输出信号的电路和方法
公开(公告)号：EP0390453A3
公开(公告)日：1992-06-17
申请号：EP90303171.4
申请日：1990-03-23
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： McClure, David Charles , Lysinger, Mark Alan
IPC分类号： G06F5/06 , G01R29/02
CPC分类号： G06F5/12 , G01R29/0273 , G06F7/026 , G06F2205/126
摘要： In the preferred embodiment of the invention, a first-in, first-out (FIFO) memory includes flag generation circuitry which utilizes a write clock counter and a read clock counter to provide the number of write clock pulses received. since the previous write reset signal and the number of read clock pulses received by the FIFO since the previous read reset signal. A subtractor circuit subtracts the number of read clock pulses from the number of write clock pulses, and this difference is compared in a comparator circuit to determine if the difference is greater than a preset value. This determination provides the information as to the relative fullness of the FIFO.

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