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11. 发明公开

EP0049990A2 Folded bit line-shared sense amplifiers 失效
标题翻译： GeteilteLeseverstärkerfürgefaltete Bit-Leitungen。
公开(公告)号：EP0049990A2
公开(公告)日：1982-04-21
申请号：EP81304614.1
申请日：1981-10-05
申请人： INMOS CORPORATION
发明人： Eaton, Sargent Sheffield, Jr. , Wooten, Rudolph
IPC分类号： G11C11/24
CPC分类号： G11C11/4097 , G11C11/409 , G11C11/4091
摘要： For sensing the logic state of an accessed memory cell in a dynamic MOS random access memory, a shared sense amplifier (14) is positioned between and coupled to first and second bit lines (A,B) via first and second isolation transistors (10,12) and is also positioned between and coupled to third and fourth bit lines (C,D) via third and fourth isolation transistors (16,18). In use, a memory cell capacitor (26) is coupled to a selected bit line (A) and a dummy cell capacitor (C D ) is coupled to the adjacent bit line (B). A decoding circuit (64,76) selectively activates the shared sense amplifier (14) to sense a voltage difference between the bit lines and to latch into a corresponding logic state for reading by inputoutput buss lines (17,19). After the logic state is read, the circuit (64,76) enables the memory cell capacitor (26) to be refreshed for further sensing.
摘要翻译：为了感测动态MOS随机存取存储器中访问的存储单元的逻辑状态，共享读出放大器（14）位于第一和第二位线（A，B）之间，并通过第一和第二隔离晶体管（10，并且还经由第三和第四隔离晶体管（16,18）定位并耦合到第三和第四位线（C，D）。在使用中，存储单元电容器（26）耦合到所选择的位线（A），并且虚设单元电容器（CD）耦合到相邻位线（B）。解码电路（64,76）选择性地激活共享读出放大器（14）以感测位线之间的电压差，并锁存到用于由输入/输出母线（17,19）读取的相应逻辑状态。在读取逻辑状态之后，电路（64,76）使存储单元电容器（26）被刷新以用于进一步的感测。

12. 发明公开

EP0049630A2 Dummy cell arrangement for an MOS memory 失效
标题翻译：空单元阵列中的存储器MOS。
公开(公告)号：EP0049630A2
公开(公告)日：1982-04-14
申请号：EP81304604.2
申请日：1981-10-05
申请人： INMOS CORPORATION
发明人： Heightley, John D. , Eaton, Sargent Sheffield, Jr.
IPC分类号： G11C11/24
CPC分类号： G11C11/4099
摘要： A dummy cell arrangement is provided for sensing the logic state of an accessed memory cell (M1) in an MOS memory in which a memory cell capacitor (C M ) of a predetermined size is associated with each memory cell. A plurality of dummy cells (D1-D4) are included, each of which has a dummy capacitor (C D ) of substantially the same predetermined size as the memory cell capacitor. When the state of an accessed memory cell is to be sensed, its memory cell capacitor (C M ) is coupled to a bit line (A) to change the voltage thereon and a selected dummy cell capacitor (C D ) is coupled to a pair of bit lines (B, E) so as to effect substantially equal transfers of charge between the dummy capacitor and the bit lines to which it is coupled. The resulting voltage on the memory cell capacitor's bit line (A) is compared to the voltage on one of the dummy capacitor's bit lines (B) so as to determine the logic state of the accessed memory cell.

13. 发明公开

EP0045133A3 Bootstrap driver circuits for an MOS memory 失效
标题翻译：用于MOS存储器的BOOTSTRAP驱动电路
公开(公告)号：EP0045133A3
公开(公告)日：1982-02-10
申请号：EP81302873
申请日：1981-06-25
申请人： INMOS CORPORATION
发明人： Sud, Rahul , Hardee, Kim Carver
IPC分类号： H03K05/02 , G11C08/00 , G11C11/40
CPC分类号： H03K19/01735 , G11C7/12 , G11C8/08 , H03K5/023 , H03K19/01855
摘要： A high speed, low power bootstrap driver is disclosed for use in an MOS memory. The basic driver includes first and second enhancement mode transistors (12, 14) for receiving a digital input (16). The drain of the first transistor (12) is coupled to a high impedance depletion mode transistor (22), and the drain of the latter transistor is coupled to the source of a low impedance transistor (26). Another enhancement mode transistor (30) is coupled via its sources to the drain of the second enhancement mode transistor (14) and is coupled via its gate to the drain of the first enhancement mode transistor (12). A capacitor (34) is connected between the drain of the high impedance transistor (22) and the drain of the second enhancement mode transistor (14). When a low level input is received, the drain of the first enhancement mode transistor (12) is rapidly bootstrapped to a high level voltage above the positive power supply for use as an output signal (18).

14. 发明公开

EP0045133A2 Bootstrap driver circuits for an MOS memory 失效
标题翻译：用于MOS存储器自举驱动电路。
公开(公告)号：EP0045133A2
公开(公告)日：1982-02-03
申请号：EP81302873.5
申请日：1981-06-25
申请人： INMOS CORPORATION
发明人： Sud, Rahul , Hardee, Kim Carver
IPC分类号： H03K5/02 , G11C8/00 , G11C11/40
CPC分类号： H03K19/01735 , G11C7/12 , G11C8/08 , H03K5/023 , H03K19/01855
摘要： A high speed, low power bootstrap driver is disclosed for use in an MOS memory. The basic driver includes first and second enhancement mode transistors (12, 14) for receiving a digital input (16). The drain of the first transistor (12) is coupled to a high impedance depletion mode transistor (22), and the drain of the latter transistor is coupled to the source of a low impedance transistor (26). Another enhancement mode transistor (30) is coupled via its sources to the drain of the second enhancement mode transistor (14) and is coupled via its gate to the drain of the first enhancement mode transistor (12). A capacitor (34) is connected between the drain of the high impedance transistor (22) and the drain of the second enhancement mode transistor (14). When a low level input is received, the drain of the first enhancement mode transistor (12) is rapidly bootstrapped to a high level voltage above the positive power supply for use as an output signal (18).

15. 发明公开

EP0044628A2 Redundancy scheme for an MOS memory 失效
标题翻译： Redundanzschemafüreinen MOS-Speicher。
公开(公告)号：EP0044628A2
公开(公告)日：1982-01-27
申请号：EP81302870.1
申请日：1981-06-25
申请人： INMOS CORPORATION
发明人： Hardee, Kim Carver , Sud, Rahul , Heightley, John D.
IPC分类号： G06F11/20
CPC分类号： G11C29/785 , G11C29/808
摘要： An MOS memory has a main array of memory cells (10, 12) and a plurality of spare memory cells (22, 24). Typically, each memory cell is tested for operability by a conventional probe test. A redundancy scheme is provided for substituting spare memory cells for memory cells found to be defective. An on-chip address controller (38-50) responds to the probe test finding a defective cell by permanently storing and rendering continuously available a fully asynchronous electrical indication of the address of the defective cell. The address controller (38-50) compares its stored data with memory cell information received during normal memory operation, and generates a control signal indicative of the receipt of an address which corresponds to a defective cell. A spare cell selector (106, 108) responds to the control signal by electrically accessing a spare memory cell and by prohibiting access of the defective memory cell.
摘要翻译： MOS存储器具有主阵列的存储单元（10,12）和多个备用存储单元（22,24）。通常，通过常规探针测试来测试每个存储单元的可操作性。提供冗余方案用于将备用存储单元替换为发现有缺陷的存储单元。片上地址控制器（38-50）通过永久存储和呈现连续可用的有缺陷单元地址的完全异步电指示来响应探测测试找到有缺陷的单元。地址控制器（38-50）将其存储的数据与在正常存储器操作期间接收到的存储器单元信息进行比较，并且产生指示对与缺陷单元对应的地址的接收的控制信号。备用小区选择器（106,108）通过电存取备用存储单元并禁止访问有缺陷的存储单元来响应控制信号。

16. 发明授权

EP0049988B1 High speed data transfer for a semiconductor memory 失效
标题翻译：用于半导体存储器的高速数据传输
公开(公告)号：EP0049988B1
公开(公告)日：1988-04-27
申请号：EP81304605.9
申请日：1981-10-05
申请人： INMOS CORPORATION
发明人： Eaton, Sargent Sheffield, Jr. , Wooten, David Rudolph
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C7/1033 , G11C8/04

17. 发明授权

EP0126758B1 ANISOTROPIC SILICIDE ETCHING PROCESS 失效
标题翻译：各向异性硅酮蚀刻工艺
公开(公告)号：EP0126758B1
公开(公告)日：1987-12-02
申请号：EP84900081.5
申请日：1983-12-01
申请人： INMOS CORPORATION
发明人： BOURASSA, Ronald, R. , REEDER, Michael, R.
IPC分类号： H01L21/28 , H01L21/306
CPC分类号： H01L21/32137
摘要： A process for anisotropically etching semiconductor products which include a lower dielectric layer (12), an intermediate polysilicon layer (14), and an upper silicide layer (16) such as titanium silicide. A pattern-defining layer (20) will normally overlie the silicide layer to define target areas to be etched. In a first step, the silicide is etched through using Freon 115 chloro, pentafluorethane (C2ClF5) in a plasma etching chamber conditioned to provide a reactive ion etch. The etch is completed in the same chamber using a second gas which includes an amount of Cl2 selected to etch anisotropically through the polysilicon layer without substantially etching the dielectric layer. Preferably, both etches occur after covering inner surfaces of the etching chamber with a material which releases molecules of the character included in the pattern-defining layer, such as Kapton, a polyamide, in the disclosed example.

18. 发明公开

EP0225426A3 A method of fabricating a MOS transistor on a substrate 失效
标题翻译：一种在基板上制作MOS晶体管的方法
公开(公告)号：EP0225426A3
公开(公告)日：1987-10-28
申请号：EP86108855
申请日：1982-12-10
申请人： INMOS CORPORATION
发明人： Ryden, William D. , Hanson, Matthew V. , Derbenwick, Gary F. , Gnadinger, Alfred P. , Adams, James R.
IPC分类号： H01L21/28 , H01L21/00 , H01L29/78
CPC分类号： H01L29/66575 , H01L21/0337 , H01L21/2652 , H01L29/0847 , H01L29/78
摘要： The invention relates to fabrication techniques for the construction of MOS transistors to provide source/drain regions (20,22) which are self-aligned and non-overlapping with respect to their gate electrode (16). The non-overlapping feature is provided by defining a gate electrode (16) over a substrate (10), forming an implant mask of dielectric (18), for example, on the sides of the gate electrode (16), and implanting a source/drain region (20,22) such that the implant mask shields a portion of the substrate from implantation to provide a gap between a side edge of the gate electrode (16) and the implanted regions (20,22). The source/drain region (20,22) is then heat driven until its side edge is substantially aligned with the edge of the gate electrode (16). Self-aligned source/drain contacts are also provided using the implant mask to isolate the gate electrode from the contacts and interconnects.

19. 发明公开

EP0150993A3 A method of fabricating a semiconductor memory structure and a semiconductor memory structure 失效
标题翻译：制造半导体存储器结构和半导体存储器结构的方法
公开(公告)号：EP0150993A3
公开(公告)日：1986-10-15
申请号：EP85300476
申请日：1985-01-24
申请人： INMOS CORPORATION
发明人： Eaton, Sheffield S., Jr. , Hu, Cheng-Cheng
IPC分类号： H01L21/76 , H01L21/82
CPC分类号： H01L27/10844 , H01L27/105 , H01L27/10805 , Y10S148/082
摘要： A method of fabricating a semiconductor memory structure and a semiconductor memory structure having a plurality of memory cells (32, 34, 36), adjacent cells being isolated. The method comprises the steps of developing a relatively thick oxide layer (12) on a silicon substrate (10), etching holes through the oxide layer and implanting impurities in the substrate (10) through said holes to define capacitor regions (16). A dielectric layer (20) is formed over the implants and then a capacitor plate (22) is added over the dielectric layer. The spacing between cells is determined by the etching process, and the method has the advantage that one mask is used for several purposes including defining active transistor areas and the first polysilicon layer. Additional advantages are disclosed including a higher body effect in the isolation transistors, use of a nitride dielectric layer, and a higher, stable threshold voltage in the isolation transistors. Also, modification of the improved process for fabrication of P-channel and N-channel devices can be made.

20. 发明公开

EP0049630A3 Dummy cell arrangement for an MOS memory 失效
标题翻译： MOS存储器的虚拟单元排列
公开(公告)号：EP0049630A3
公开(公告)日：1983-09-14
申请号：EP81304604
申请日：1981-10-05
申请人： INMOS CORPORATION
发明人： Heightley, John D. , Eaton, Sargent Sheffield, Jr.
IPC分类号： G11C11/24
CPC分类号： G11C11/4099
摘要： A dummy cell arrangement is provided for sensing the logic state of an accessed memory cell (M1) in an MOS memory in which a memory cell capacitor (C M ) of a predetermined size is associated with each memory cell. A plurality of dummy cells (D1-D4) are included, each of which has a dummy capacitor (C D ) of substantially the same predetermined size as the memory cell capacitor. When the state of an accessed memory cell is to be sensed, its memory cell capacitor (C M ) is coupled to a bit line (A) to change the voltage thereon and a selected dummy cell capacitor (C D ) is coupled to a pair of bit lines (B, E) so as to effect substantially equal transfers of charge between the dummy capacitor and the bit lines to which it is coupled. The resulting voltage on the memory cell capacitor's bit line (A) is compared to the voltage on one of the dummy capacitor's bit lines (B) so as to determine the logic state of the accessed memory cell.
摘要翻译：提供一个虚拟单元配置，用于在其中具有预定大小的存储器单元电容器（CM）与每个存储器单元相关联的MOS存储器中感测被访问的存储器单元（M1）的逻辑状态。包括多个虚设单元（D1-D4），每个虚设单元具有与存储单元电容器具有基本相同的预定尺寸的虚拟电容器（CD）。当被访问的存储器单元的状态将被感测时，其存储器单元电容器（CM）被耦合到位线（A）以改变其上的电压，并且所选择的虚拟单元电容器（CD）被耦合到一对位线（B，E），从而实现虚拟电容器与其所耦合的位线之间的电荷的基本相等的转移。存储器单元电容器的位线（A）上的所得电压与虚拟电容器的位线（B）中的一者上的电压进行比较，以确定所存取的存储器单元的逻辑状态。

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