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1. 发明公开

EP0049990A2 Folded bit line-shared sense amplifiers 失效
标题翻译： GeteilteLeseverstärkerfürgefaltete Bit-Leitungen。
公开(公告)号：EP0049990A2
公开(公告)日：1982-04-21
申请号：EP81304614.1
申请日：1981-10-05
申请人： INMOS CORPORATION
发明人： Eaton, Sargent Sheffield, Jr. , Wooten, Rudolph
IPC分类号： G11C11/24
CPC分类号： G11C11/4097 , G11C11/409 , G11C11/4091
摘要： For sensing the logic state of an accessed memory cell in a dynamic MOS random access memory, a shared sense amplifier (14) is positioned between and coupled to first and second bit lines (A,B) via first and second isolation transistors (10,12) and is also positioned between and coupled to third and fourth bit lines (C,D) via third and fourth isolation transistors (16,18). In use, a memory cell capacitor (26) is coupled to a selected bit line (A) and a dummy cell capacitor (C D ) is coupled to the adjacent bit line (B). A decoding circuit (64,76) selectively activates the shared sense amplifier (14) to sense a voltage difference between the bit lines and to latch into a corresponding logic state for reading by inputoutput buss lines (17,19). After the logic state is read, the circuit (64,76) enables the memory cell capacitor (26) to be refreshed for further sensing.
摘要翻译：为了感测动态MOS随机存取存储器中访问的存储单元的逻辑状态，共享读出放大器（14）位于第一和第二位线（A，B）之间，并通过第一和第二隔离晶体管（10，并且还经由第三和第四隔离晶体管（16,18）定位并耦合到第三和第四位线（C，D）。在使用中，存储单元电容器（26）耦合到所选择的位线（A），并且虚设单元电容器（CD）耦合到相邻位线（B）。解码电路（64,76）选择性地激活共享读出放大器（14）以感测位线之间的电压差，并锁存到用于由输入/输出母线（17,19）读取的相应逻辑状态。在读取逻辑状态之后，电路（64,76）使存储单元电容器（26）被刷新以用于进一步的感测。

2. 发明授权

EP0049990B1 Folded bit line-shared sense amplifiers 失效
标题翻译：折叠双绞线共模放大器
公开(公告)号：EP0049990B1
公开(公告)日：1987-05-27
申请号：EP81304614.1
申请日：1981-10-05
申请人： INMOS CORPORATION
发明人： Eaton, Sargent Sheffield, Jr. , Wooten, Rudolph
IPC分类号： G11C11/24
CPC分类号： G11C11/4097 , G11C11/409 , G11C11/4091

3. 发明公开

EP0049990A3 Folded bit line-shared sense amplifiers 失效
标题翻译：折叠双绞线共模放大器
公开(公告)号：EP0049990A3
公开(公告)日：1982-10-13
申请号：EP81304614
申请日：1981-10-05
申请人： INMOS CORPORATION
发明人： Eaton, Sargent Sheffield, Jr. , Wooten, Rudolph
IPC分类号： G11C11/24
CPC分类号： G11C11/4097 , G11C11/409 , G11C11/4091
摘要： For sensing the logic state of an accessed memory cell in a dynamic MOS random access memory, a shared sense amplifier (14) is positioned between and coupled to first and second bit lines (A,B) via first and second isolation transistors (10,12) and is also positioned between and coupled to third and fourth bit lines (C,D) via third and fourth isolation transistors (16,18). In use, a memory cell capacitor (26) is coupled to a selected bit line (A) and a dummy cell capacitor (C D ) is coupled to the adjacent bit line (B). A decoding circuit (64,76) selectively activates the shared sense amplifier (14) to sense a voltage difference between the bit lines and to latch into a corresponding logic state for reading by inputoutput buss lines (17,19). After the logic state is read, the circuit (64,76) enables the memory cell capacitor (26) to be refreshed for further sensing.

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