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111. 发明公开

EP3367443A1 METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR 审中-公开
公开(公告)号：EP3367443A1
公开(公告)日：2018-08-29
申请号：EP18157161.3
申请日：2018-02-16
申请人： Toyota Jidosha Kabushiki Kaisha
发明人： ARAUCHI, Takuji , KINPARA, Hiromichi , TSUJIMURA, Masatoshi , YAMASHITA, Yusuke , URAKAMI, Yasushi
IPC分类号： H01L29/78 , H01L29/06 , H01L29/12
CPC分类号： H01L29/063 , H01L21/046 , H01L29/0623 , H01L29/1095 , H01L29/1608 , H01L29/66068 , H01L29/7813
摘要： A silicon carbide trench gate MOSFET device comprising a region (42) includes a high-concentration region (42a) and a low-concentration region (42b) that are arranged along a thickness direction of a silicon carbide substrate. A concentration of a p-type dopant in the low-concentration region (42b) is lower than a concentration of the p-type dopant in the high-concentration region (42a). The high-concentration region (42a) contacts the low-concentration region (42b), and is disposed between a bottom surface (13b) of a gate trench (13) and the low-concentration region (42b). In graph obtained by plotting the concentration of the p-type dopant in the floating region (42) along the thickness direction, a bending point or an inflection point appears on a boundary between the high-concentration region (42a) and the low-concentration region (42b). A content of the p-type dopant in the low-concentration region (42b) is equal to or higher than a content of an n-type dopant in a portion of the drift region (34), which is adjacent to the low-concentration region (42b) in the thickness direction.

112. 发明授权

EP1914807B1 Method for producing semiconductor device 有权
公开(公告)号：EP1914807B1
公开(公告)日：2018-08-29
申请号：EP07019852.8
申请日：2007-10-10
申请人： Nissan Motor Co., Ltd.
发明人： Hayashi, Tetsuya , Hoshi, Masakatsu , Tanaka, Hideaki , Yamagami, Shigeharu
IPC分类号： H01L29/78 , H01L21/336 , H01L29/267 , H01L29/16 , H01L29/06 , H01L29/08
CPC分类号： H01L29/267 , H01L29/0623 , H01L29/0847 , H01L29/1608 , H01L29/66068 , H01L29/7828
摘要： A method for producing a semiconductor device (21) which includes: a semiconductor base (20), a hetero semiconductor region (3) made of a semiconductor material different in band gap from a semiconductor material for the semiconductor base (1,2), and so configured as to form a hetero junction (HJ1) in combination with the semiconductor base (2), a gate insulating film (4) so configured as to contact the hetero junction (HJ1) between the semiconductor base (2) and the hetero semiconductor region (3), a gate electrode (5) so configured as to contact the gate insulating film (4), a source electrode (6) connected to the hetero semiconductor region (3), and a drain electrode (7) connected to the semiconductor base (1). The method includes: forming the following in a self-aligning manner, by using a certain mask material (10): a source contact hole (70) for the source electrode (6), and the gate electrode (5).

113. 发明公开

EP3357084A1 SOURCE-GATE REGION ARCHITECTURE IN A VERTICAL POWER SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：EP3357084A1
公开(公告)日：2018-08-08
申请号：EP16852211.8
申请日：2016-01-28
申请人： D3 Semiconductor LLC
发明人： HARRINGTON, Thomas, E.
IPC分类号： H01L21/82 , H01L21/32 , H01L21/70 , H01L21/77 , H01L21/822
CPC分类号： H01L23/535 , H01L21/28518 , H01L21/76805 , H01L21/76843 , H01L21/76889 , H01L21/76895 , H01L23/53266 , H01L29/0623 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/41775 , H01L29/456 , H01L29/4933 , H01L29/66333 , H01L29/66712 , H01L29/7395 , H01L29/7802 , H01L29/7811
摘要： A vertical drift metal-oxide-semiconductor (VDMOS) transistor with improved contact to source and body regions, and a method of fabricating the same. A masked ion implant of the source regions into opposite-type body regions defines the locations of body contact regions, which are implanted subsequently with a blanket implant. The surface of the source regions and body contact regions are silicide clad, and an overlying insulator layer deposited and planarized. Contact openings are formed through the planarized insulator layer, within which conductive plugs are formed to contact the metal silicide, and thus the source and body regions of the device. A metal conductor is formed overall to the desired thickness, and contacts the conductive plugs to provide bias to the source and body regions.

114. 发明公开

EP3308392A1 INSULATED GATE SWITCHING DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：绝缘栅开关装置及其制造方法
公开(公告)号：EP3308392A1
公开(公告)日：2018-04-18
申请号：EP16731351.9
申请日：2016-06-03
申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA , Denso Corporation
发明人： TAKAYA, Hidefumi , MIZUNO, Shoji , WATANABE, Yukihiko , AOI, Sachiko
IPC分类号： H01L21/336 , H01L29/78 , H01L29/12 , H01L29/06 , H01L29/423
CPC分类号： H01L29/1608 , H01L21/02529 , H01L21/046 , H01L21/0475 , H01L21/049 , H01L29/0623 , H01L29/1095 , H01L29/36 , H01L29/4236 , H01L29/42368 , H01L29/66068 , H01L29/66348 , H01L29/66734 , H01L29/7397 , H01L29/7813
摘要： A method for manufacturing an insulated gate switching device is provided. The method includes: forming a first trench in a surface of a first SiC semiconductor layer; implanting p-type impurities into a bottom surface of the first trench; depositing a second SiC semiconductor layer on an inner surface of the first trench to form a second trench; and forming a gate insulating layer, a gate electrode, a first region and a body region so that the gate insulating layer covers an inner surface of the second trench, the gate electrode is located in the second trench, the first region is of n-type and in contact with the gate insulating layer, the body region is of p-type, separated from the implanted region, and in contact with the gate insulating layer under the first region.

115. 发明公开

EP3301605A1 PUCE ÉLECTRONIQUE PROTÉGÉE 有权
标题翻译：电子芯片保护
公开(公告)号：EP3301605A1
公开(公告)日：2018-04-04
申请号：EP17156779.5
申请日：2017-02-17
申请人： STMICROELECTRONICS (ROUSSET) SAS
发明人： CHAMPEIX, Clement , BORREL, Nicolas , SARAFIANOS, Alexandre
IPC分类号： G06F21/75 , G06F21/77 , G06F21/87 , H01L29/66 , H01L23/00
CPC分类号： H01L29/0623 , G06F21/75 , G06F21/77 , G06F21/78 , G06F21/87 , G06F21/88 , H01L21/823892 , H01L23/57 , H01L23/576 , H01L27/0629 , H01L27/092 , H01L27/0928 , H01L29/107 , H01L29/1095 , H01L29/66181 , H03K5/24
摘要： L'invention concerne une puce électronique, comprenant : un substrat semiconducteur (46) dopé d'un premier type de conductivité ; une couche enterrée (36) dopée d'un deuxième type de conductivité recouvrant le substrat ; un premier caisson (37) dopé du premier type de conductivité recouvrant la couche enterrée ; des circuits (10, 24, 32) séparés de la couche enterrée formés dans et sur le premier caisson et/ou dans et sur des deuxièmes caissons (12, 26, 16) formés dans le premier caisson ; et un détecteur du courant de polarisation (I) de la couche enterrée.
摘要翻译：一种电子芯片，包括：掺杂有第一导电类型的半导体衬底（46）掺杂有覆盖所述衬底的第二类型导电性的掩埋层（36）掺杂有第一类型导电性的第一盒（37），其覆盖埋层; 与在所述第一阱中和所述第一阱上形成的埋层分离的电路（10,24,32）和/或在所述第一阱中形成的第二阱（12,26,16）中和之上的电路; 和埋入层的极化电流检测器（I）。

116. 发明授权

EP2491593B1 SPLIT GATE SEMICONDUCTOR DEVICE WITH CURVED GATE OXIDE PROFILE 有权
标题翻译：分裂栅极半导体器件与曲线栅氧化层剖面
公开(公告)号：EP2491593B1
公开(公告)日：2018-03-21
申请号：EP10825703.1
申请日：2010-10-21
申请人： Vishay-Siliconix
发明人： GAO, Yang , CHEN, Kuo-In , TERRILL, Kyle , SHI, Sharon
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66621 , H01L29/0615 , H01L29/0623 , H01L29/0696 , H01L29/407 , H01L29/66727 , H01L29/66734 , H01L29/7811 , H01L29/7813
摘要： A split gate semiconductor device includes a trench gate having a first electrode region and a second electrode region that are separated from each other by a gate oxide layer and an adjacent dielectric layer. The boundary of the gate oxide layer and the dielectric layer is curved to avoid a sharp corner where the gate oxide layer meets the sidewalls of the trench.

117. 发明公开

EP3276671A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：EP3276671A1
公开(公告)日：2018-01-31
申请号：EP16771899.8
申请日：2016-02-08
申请人： Rohm Co., Ltd.
发明人： NAKANO, Yuki
IPC分类号： H01L29/78 , H01L21/336 , H01L29/06 , H01L29/12
CPC分类号： H01L29/7813 , H01L29/06 , H01L29/0615 , H01L29/0619 , H01L29/0623 , H01L29/0696 , H01L29/12 , H01L29/1608 , H01L29/2003 , H01L29/4236 , H01L29/4238 , H01L29/4925 , H01L29/78 , H01L29/7811
摘要： The semiconductor device of the present invention includes a semiconductor layer which includes an active portion and a gate finger portion, an MIS transistor which is formed at the active portion and includes a gate trench as well as a source region, a channel region and a drain region sequentially along a side surface of the gate trench, a plurality of first gate finger trenches arranged by an extended portion of the gate trench at the gate finger portion, a gate electrode embedded each in the gate trench and the first gate finger trench, a second conductive-type first bottom-portion impurity region formed at least at a bottom portion of the first gate finger trench, a gate finger which crosses the plurality of first gate finger trenches and is electrically connected to the gate electrode, and a second conductive-type electric field relaxation region which is formed more deeply than the bottom portion of the first gate finger trench between the mutually adjacent first gate finger trenches.
摘要翻译：本发明的半导体器件包括：半导体层，其包括有源部分和栅极指状部分; MIS晶体管，其形成在有源部分并且包括栅极沟槽以及源极区域，沟道区域和漏极沿着所述栅极沟槽的侧表面顺序布置的多个第一栅极指状沟槽，由所述栅极沟槽的延伸部分在所述栅极指状部分处布置的多个第一栅极指状沟槽，每个都嵌入所述栅极沟槽和所述第一栅指状沟槽中的栅电极，第二导电型的第一底部杂质区域，其至少形成在第一栅极叉指沟槽的底部;栅极指，其与多个第一栅极叉指沟槽交叉并且与栅极电连接;以及第二导电型的第一底部杂质区，该电场缓和区比相互相邻的第一栅极指tre之间的第一指状栅槽的底部形成得更深 nches。

118. 发明授权

EP2342753B1 INSULATED GATE BIPOLAR TRANSISTOR 有权转让
公开(公告)号：EP2342753B1
公开(公告)日：2018-01-17
申请号：EP09818446.8
申请日：2009-09-30
申请人： IXYS CORPORATION
发明人： SEOK, Kyoung-Wook , TSUKANOV, Vladimir
IPC分类号： H01L29/739 , H01L29/08 , H01L29/423 , H01L29/06
CPC分类号： H01L29/7397 , H01L29/0623 , H01L29/0696 , H01L29/08 , H01L29/0834 , H01L29/4238
摘要： A trench structure of an insulated gate bipolar transistor (IGBT) is formed as a trench net in a P region and extends into an N− layer. The trench net separates the P region into P wells and floating P layers. The P wells contact an emitter electrode while the floating P layers are not in direct contact with the emitter electrode. A gate formed of conductive material and having a surrounding insulation oxide layer is formed in the trench net. An N+ layer may be formed above each floating P layer under the gate. The floating P layers are isolated from the gate and are also not connected to the emitter electrode.

119. 发明授权

EP1994566B1 INSULATED GATE-TYPE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权转让
标题翻译：绝缘栅型半导体器件及其制造方法
公开(公告)号：EP1994566B1
公开(公告)日：2018-01-17
申请号：EP07707920.0
申请日：2007-01-26
申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA
发明人： TAKAYA, Hidefumi , HAMADA, Kimimori , MIYAGI, Kyosuke
IPC分类号： H01L29/78 , H01L21/336 , H01L29/06 , H01L29/08 , H01L29/423 , H01L21/265
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0623 , H01L29/0634 , H01L29/0878 , H01L29/42368 , H01L29/4238 , H01L29/66734 , H01L29/7811
摘要： A semiconductor 100 has a P− body region and an N− drift region in the order from an upper surface side thereof. A gate trench and a terminal trench passing through the P− body region are formed. The respective trenches are surrounded with P diffusion regions at the bottom thereof. The gate trench builds a gate electrode therein. A P−− diffusion region, which is in contact with the end portion in a lengthwise direction of the gate trench and is lower in concentration than the P− body region and the P diffusion region, is formed. The P−− diffusion region is depleted prior to the P diffusion region when the gate voltage is off. The P−− diffusion region serves as a hole supply path to the P diffusion region when the gate voltage is on.

120. 发明公开

EP3010037A4 SILICON CARBIDE SEMICONDUCTOR DEVICE MANUFACTURING METHOD 审中-公开
标题翻译： SILICIUMCARBIDHALBLEITERBAUELEMENTHERSTELLUNGSVERFAHREN
公开(公告)号：EP3010037A4
公开(公告)日：2017-03-22
申请号：EP14810167
申请日：2014-05-08
申请人： SUMITOMO ELECTRIC INDUSTRIES
发明人： TAMASO HIDETO
IPC分类号： H01L21/336 , G03F9/00 , H01L21/027 , H01L21/337 , H01L21/338 , H01L29/12 , H01L29/16 , H01L29/78 , H01L29/808 , H01L29/812
CPC分类号： H01L21/02529 , G03F9/708 , G03F9/7084 , H01L21/0274 , H01L22/12 , H01L23/544 , H01L29/045 , H01L29/0623 , H01L29/1608 , H01L29/401 , H01L29/66068 , H01L29/7813 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A method for manufacturing a silicon carbide semiconductor device includes the following steps. There is prepared a first silicon carbide layer (10) having a first main surface (10a) and a second main surface (10b). A first recess (1) including a side portion (10c) and a bottom portion (10d) is formed in the first main surface (10a) of the first silicon carbide layer (10). A second silicon carbide layer (20) is formed in contact with the first main surface (10a), the side portion (10c), and the bottom portion (10d). An image of a second recess (2) formed at a position facing the first recess (1) of the fourth main surface (20a) is obtained. Alignment is performed based on the image of the second recess (2). The first main surface corresponds to a plane angled off relative to a {0001} plane. A ratio obtained by dividing a depth (D) of the first recess (1) by a thickness (T) of the second silicon carbide layer (20) is more than 0.2. In this way, there can be provided a method for manufacturing a silicon carbide semiconductor device to allow for improved alignment precision.
摘要翻译：一种用于制造碳化硅半导体器件的方法包括以下步骤。准备具有第一主表面（10a）和第二主表面（10b）的第一碳化硅层（10）。包括侧部（10c）和底部（10d）的第一凹部（1）形成在第一碳化硅层（10）的第一主表面（10a）中。第二碳化硅层（20）形成为与第一主表面（10a），侧部（10c）和底部（10d）接触。获得形成在面对第四主表面（20a）的第一凹陷（1）的位置处的第二凹陷（2）的图像。根据第二凹槽（2）的图像进行对准。第一主表面对应于相对于{0001}平面倾斜的平面。通过将第一凹部（1）的深度（D）除以第二碳化硅层（20）的厚度（T）获得的比率大于0.2。以这种方式，可以提供用于制造碳化硅半导体器件的方法以允许提高对准精度。

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