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101. 发明授权

EP0823785B1 Input circuit 失效
标题翻译：输入电路
公开(公告)号：EP0823785B1
公开(公告)日：2003-04-02
申请号：EP97113238.6
申请日：1997-07-31
申请人： NEC CORPORATION
发明人： Watarai, Seiichi
IPC分类号： H03K19/0175 , H03K19/003 , H03K19/00
CPC分类号： H03K19/003

102. 发明授权

EP0972343B1 PROGRAMMABLE DYNAMIC LINE-TERMINATION CIRCUIT 失效
标题翻译：内置的可编程动态线终端电路
公开(公告)号：EP0972343B1
公开(公告)日：2002-11-06
申请号：EP97932505.7
申请日：1997-07-03
申请人： Kaplinsky, Cecil, H.
发明人： Kaplinsky, Cecil, H.
IPC分类号： H03K19/0175
CPC分类号： H04L25/0298
摘要： A dynamic termination circuit is disclosed that has a plurality n of parallel termination elements (391-39N; 551-55n) that respond successively to a signal transition and which are selectively enabled and disabled to provide a desired impedance match with a transmission line. Each termination element includes a first dynamic resistive path between a voltage supply line (Vdd) and that termination element's output (431-43n; 651-65n) and a second dynamic resistive path between the termination element output and ground, both resistive paths including field-effect transistors (Mi1, Mi2(i=1 to n)) whose control gates are responsive to a signal received from the transmission line via an input (31; 51) to the circuit. For successive elements a series of delay elements (412-41n; 54i (i=1 to n)) are provided between the circuit input and the respective termination circuit elements.

103. 发明授权

EP1072096B1 FREMDVERSORGTER SCHNITTSTELLENADAPTER 有权
标题翻译：对外供电接口适配器
公开(公告)号：EP1072096B1
公开(公告)日：2002-10-16
申请号：EP99919106.7
申请日：1999-03-20
申请人： Moeller GmbH
发明人： CULCA, Horea-Stefan
IPC分类号： H03K19/0175 , G06F13/40
CPC分类号： H03K19/017536 , G06F13/4072
摘要： The invention relates to a coupling piece for carrying out digital transmissions between an electrical interface of a first device and an electrical interface of a second device. The devices each use different voltage levels for distinguishing between the two logical states "high" and "low". The invention is characterised by an internal circuit (23) by which means the voltage levels of the first device can be converted to the voltage levels of the second device, which correspond to the state. The higher voltage level is conveyed to this internal circuit by one of the two devices so that the low level can be converted to the higher level. The internal circuit (23) carries out the conversion with a switching process.

104. 发明授权

EP0839408B1 Circuit board insertion circuitry for high reliability backplanes 失效
标题翻译：背板布线高度可靠的电路板插入电路
公开(公告)号：EP0839408B1
公开(公告)日：2002-03-20
申请号：EP96923666.0
申请日：1996-07-05
申请人： Transwitch Corporation
发明人： BARTHOLOMAY, William, G. , PARRELLA, Eugene, L. , UPP, Daniel, C. , ICHIBA, Mikio, S.
IPC分类号： H03K19/0175
CPC分类号： H03K19/018557 , H03K19/09429
摘要： Circuit board insertion circuitry is used in conjunction with a staggered electrical connector (not shown). The insertion circuitry includes an isolated circuit (B1 and M2) which receives a high system voltage upon first stage contact between the card (100) and a high voltage bus (40), and uses that high system voltage to tristate the output of a transceiver (10) on the circuit board (100) prior to second stage contact being made between the transceiver (10) and the backplane data bus (20). Override circuitry (15) for overriding the tristating effects of the isolating circuit is provided such that when the bias circuit (15) which controls the transceiver output is properly powered, the bias circuit will control the transceiver output, and not the isolated circuit. Power fault isolation is also provided by a relatively large resistor (R1) and a Schottky diode (D1).

105. 发明公开

EP1095452A1 A CMOS DRIVER 有权
标题翻译： CMOS驱动电路
公开(公告)号：EP1095452A1
公开(公告)日：2001-05-02
申请号：EP99930730.9
申请日：1999-06-24
申请人： INTEL CORPORATION
发明人： GRIFFIN, Jed, D.
IPC分类号： H03K17/16 , H03K19/0175 , H03K19/094
CPC分类号： H03K19/00361
摘要： A CMOS input/output driver (200) having constant output impedance (Zo), the driver comprising a drive pMOSFET (208) and a drive nMOSFET (210) for driving an output node (202) HIGH and LOW, a pMOSFET (224) having a drain coupled to the output node and switchable so that its gate is coupled to the output node when the drive pMOSFET is driving the output node HIGH, and an nMOSFET having a drain coupled to the output node and switchable so that its gate is coupled to the output node when the drive nMOSFET is driving the output node LOW. The betas of the drive pMOSFET, the drive nMOSFET, the pMOSFET, and the nMOSFET are matched so that the output impedance of the drive is approximately independent of the output node voltage.

106. 发明授权

EP0547349B1 Programmable integrated circuit output pad 失效转让
标题翻译：具有可编程的输出集成电路
公开(公告)号：EP0547349B1
公开(公告)日：2000-12-27
申请号：EP92118747.2
申请日：1992-11-02
申请人： HEWLETT-PACKARD COMPANY
发明人： Knee, Derek L. , Wheless, Thomas O. , Li, Wang Kay
IPC分类号： H03K19/0175 , H03K19/003 , H03K19/0185
CPC分类号： H03K19/00361

107. 发明公开

EP1050825A1 Bussignalempfangseinheit für einen 2-Draht-Bus sowie Installationsverfahren für einen 2-Draht-Bus 有权
标题翻译： Bussignalempfangseinheitfüreinen 2-Draht-Bus sowie Installationsverfahrenfüreinen 2-Draht-Bus
公开(公告)号：EP1050825A1
公开(公告)日：2000-11-08
申请号：EP99108183.7
申请日：1999-04-26
申请人： Feller AG
发明人： Wichert, Stefan , Zurlinden, Jonas , Stalder, Martin
IPC分类号： G06F13/40 , H03K19/0175
CPC分类号： G06F13/4072 , H04L25/08
摘要： Bei einer 2-Draht-Busanordnung mit Busleitungen (1, 2) wird die busspeisefähige Bussignalempfangseinheit (3) mit einem Kurzschlussschutz versehen, welcher ein Abschalten der Busspeisespannung im Kurzschlussfall bewirkt. Zu diesem Zweck ist ein Detektionsmittel vorgesehen, welches Bussignale von einem Kurzschluss unterscheiden kann. Falls weitere busspeisefähige Busteilnehmer (13) vorgesehen sind, so erfolgt die Installation derart, dass die Busspeisung nur einem der speisefähigen Busteilnehmer (3, 13) zugeordnet wird und die Busspeisung der anderen Busteilnehmer deaktiviert wird. Dies erlaubt das Anschliessen der Busteilnehmer mit beliebiger Polung.
摘要翻译：总线信号接收单元（3）具有鉴别总线信号和总线短路的检测装置，该检测装置与用于2线总线的电压供给级的开 - 关切换的开关装置相连。检测装置可以包括用于断开总线供应级的电压极性保护功能。还包括以下的独立权利要求：（a）总线信号终端; （b）2线总线; （c）在建筑物安装中应用总线信号接收单元; （d）2线总线的安装方法; （e）向建筑物安装应用2线总线安装方法

108. 发明授权

EP0435404B1 Differential input bicmos buffer-inverters and gates 失效
标题翻译：的BiCMOS缓冲倒相器和栅极输入differentielem
公开(公告)号：EP0435404B1
公开(公告)日：2000-10-25
申请号：EP90203439.6
申请日：1990-12-19
申请人： Koninklijke Philips Electronics N.V.
发明人： Burton, Edward , Fletcher, Thomas
IPC分类号： H03K19/094 , H03K19/0175
CPC分类号： H03K19/09448 , H03K19/017527

109. 发明公开

EP1014582A1 Digital signal transmitter and receiver using source based reference logic levels 审中-公开
标题翻译： Digitaler Signalsender undEmpfängermit einer SignalquellefürReferenzlogikpegel
公开(公告)号：EP1014582A1
公开(公告)日：2000-06-28
申请号：EP99309742.7
申请日：1999-12-03
申请人： Nortel Networks Corporation
发明人： Crick, William R
IPC分类号： H03K19/003 , H03K19/0175 , G06F13/40
CPC分类号： H03K19/00346
摘要： A signal transmitter for transmitting digital logic signals and a complementary receiver, are disclosed. The signal transmitter comprises a plurality of signal drivers and at least one reference driver. The signal drivers transmit digital signals, while the reference driver transmits a constant signal representative of a digital HI or LO. The signal and reference drivers are interconnected so that any noise due to package and power supply interconnection impedances is present in all transmitted signals including any reference signals. At a receiver, the reference signal including noise is used to establish threshold levels for digital HI and LO signals. Because noise is common to all transmitted signals, the receiver is able to reduce the effects of the noise by comparing the plurality of received signals with the reference signal.
摘要翻译：公开了用于发送数字逻辑信号的信号发射机和互补接收机。信号发射器包括多个信号驱动器和至少一个参考驱动器。信号驱动器传输数字信号，而参考驱动器传输代表数字HI或LO的恒定信号。信号和参考驱动器互连，使得由于封装和电源互连阻抗引起的任何噪声都存在于包括任何参考信号的所有传输信号中。在接收机处，使用包括噪声的参考信号来建立数字HI和LO信号的阈值电平。由于噪声对所有发射信号是共同的，所以接收机能够通过将多个接收信号与参考信号进行比较来减小噪声的影响。

110. 发明公开

EP1006658A1 Low dissipation biCMOS ECL/CMOS interface 审中-公开
标题翻译： Bi CMOS CMOS ECL / CMOS Schnittstelle mit Niedrigem Verbrauch
公开(公告)号：EP1006658A1
公开(公告)日：2000-06-07
申请号：EP98830727.8
申请日：1998-12-03
申请人： STMicroelectronics S.r.l.
发明人： Ottini, Daniele , Bruccoleri, Melchiorre , Marchese, Stefano , Bollati, Giacomino
IPC分类号： H03K19/0175
CPC分类号： H03K19/017527
摘要： A BiCMOS ECL/CMOS interface circuit for converting a high frequency pseudo-ECL signal with a voltage swing in the order of few hundreds of millivolts into a CMOS signal with a voltage swing substantially equal to the supply voltage, comprising a differential input stage composed of a pair of NPN bipolar junction transistors (Q1, Q2) in a common emitter configuration, a bias current generator (IBIAS) functionally coupled between the common emitter node of said NPN transistors and ground and means driven by a respective transistor of said input pair (Q1, Q2) driving the control node of a respective output CMOS stage (M5-M7, M6-M8), is provided with first and second common-collector stages each constituted by an NPN bipolar junction transistor(Q3, Q4) and driven by a respective transistor of said pair of NPN transistors (Q1, Q2); and with a pair of identical PMOS transistors (M1, M2) with gates connected in common to a bias voltage (POL), each PMOS transistor (M1, M2) having a source coupled to the emitter of a respective transistor (Q3, Q4) of said common-collector stages and a drain connected to a load current generator (I) and to said control node of a respective output CMOS stage (M5-M7, M6-M8), for reducing current absorption without impairing performance.
摘要翻译：一种BiCMOS ECL / CMOS接口电路，用于将具有几百毫伏数量级的电压摆幅的高频伪ECL信号转换成具有基本上等于电源电压的电压摆幅的CMOS信号，包括差分输入级，其由一个共同的发射结构的一对NPN双极结晶体管（Q1，Q2），功能上耦合在所述NPN晶体管的公共发射极节点与地之间的偏置电流发生器（IBIAS）和由所述输入对的相应晶体管驱动的装置 Q1，Q2）驱动各个输出CMOS级（M5-M7，M6-M8）的控制节点，设置有由NPN双极结型晶体管（Q3，Q4）构成的第一和第二公共集电极级，并由所述一对NPN晶体管（Q1，Q2）的相应晶体管; 并且通过一对具有与偏置电压（POL）共同连接的栅极的一对相同的PMOS晶体管（M1，M2），每个PMOS晶体管（M1，M2）具有耦合到相应晶体管（Q3，Q4）的发射极的源极，的所述共集电极级和连接到负载电流发生器（I）的漏极以及相应的输出CMOS级（M5-M7，M6-M8）的所述控制节点，用于减小电流吸收而不损害性能。

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