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91. 发明授权

EP1484674B1 Maximally digitized fractional-N frequency synthesizer and modulator with maximal fractional spurious removing 有权
$Maximally digitized fractional-N frequency synthesizer and modulator with maximal fractional spurious removing$
标题翻译：最大数字化的频率合成器与一个破碎分频比和调制器，用于噪声降低
公开(公告)号：EP1484674B1
公开(公告)日：2006-10-04
申请号：EP03012840.9
申请日：2003-06-06
申请人： Zhang, Xiaopin
发明人： Zhang, Xiaopin
IPC分类号： G06F7/60 , H03M7/00 , H03L7/197 , H03D13/00
CPC分类号： H03C3/0991 , H03C3/0925 , H03C3/0933 , H03L7/091 , H03L7/093 , H03L7/1974

92. 发明公开

EP0833483A3 Phase comparator for demodulator using differential detection 失效
标题翻译：相位差检测的解调器
公开(公告)号：EP0833483A3
公开(公告)日：2006-08-16
申请号：EP97120802.0
申请日：1992-12-24
申请人： MITSUBISHI DENKI KABUSHIKI KAISHA
发明人： Kojima, Toshiharu, c/o Mitsubishi Denki K.K.
IPC分类号： H04L27/22 , H03D7/00 , H03D13/00 , H03B21/00 , H04L27/233
CPC分类号： H04L27/2332 , H03D7/00 , H03D7/161 , H03D7/165 , H03D13/001 , H03D13/003 , H03D2200/007 , H04L27/2337
摘要： Within the delayed detection type demodulator, the received signal is first quantized by a limiter amplifier (10) and then subjected to frequency conversion by a frequency converter (50). In response to the output of the frequency converter, a phase comparator (60) outputs a relative phase signal representing the phase shift of the received signal after frequency conversion relative to the phase reference signal. The phase comparator includes: an exclusive OR element (61); an absolute phase shift measurement means (62) consisting of an adder (63) and D flip-flop arrays (64 and 65); and a D flip-flop (66) serving as a phase shift polarity decision means. A delay element (40) delays the relative phase signal by one symbol period and a subtractor (41) outputs the phase difference signal representing the phase transition over each symbol period of the received signal. A decision circuit (42) obtains the demodulated data from the phase difference signal.

93. 发明公开

EP1315328A3 Multi-phase sampling 有权
标题翻译： Mehrphasen-Abtastung
公开(公告)号：EP1315328A3
公开(公告)日：2005-07-06
申请号：EP02021683.4
申请日：2002-09-27
申请人： Agilent Technologies, Inc.
发明人： Walker, Richard C.
IPC分类号： H04L7/033 , H03L7/089 , H03D13/00 , H03L7/081 , H03L7/091
CPC分类号： H04L7/033 , H03L7/081 , H03L7/091 , H03L7/0995 , H04L7/0004 , H04L7/0037
摘要： The present invention provides a multi-phase sampling system (3, 10) in which each sampler (4, 5, 6, 11, 12, 13) samples a transition and data of an incoming data signal (2, 14). By enabling each sampler to sample a transition in addition to data of the incoming data signal, phase errors associated with each of the samplers can be determined (30). The phase error determinations (24, 25, 26) provide valuable information that can be used 1) to correct the phase errors of the system sampling the incoming data signal, 2) to correct the phase errors of a multi-phase system that is transmitting the incoming data signal, and/or 3) to correct the phase errors of both a multi-phase system that is sampling an incoming data signal and of a multi-phase system that is transmitting the data signal.
摘要翻译：本发明提供一种多相采样系统（3,10），其中每个采样器（4,5,6,11,12,13）采样输入数据信号（2,14）的转换和数据。通过启用每个采样器除了输入数据信号的数据之外，可以确定与每个采样器相关联的相位误差（30）的转换。相位误差确定（24,25,26）提供了可以使用的有价值的信息1）校正系统采样输入数据信号的相位误差，2）校正正在传输的多相系统的相位误差输入数据信号，和/或3）校正正在对输入数据信号进行采样的多相系统和正在发送数据信号的多相系统的相位误差。

94. 发明公开

EP1527515A1 PHASE DETECTOR WITH SELECTION OF DIFFERENCES BETWEEN INPUT SIGNALS 审中-公开
标题翻译：与选区之间的输入SIGNALS差异的相位检波器
公开(公告)号：EP1527515A1
公开(公告)日：2005-05-04
申请号：EP03766577.5
申请日：2003-07-23
申请人： Koninklijke Philips Electronics N.V.
发明人： SANDULEANU, Mihai, A., T.
IPC分类号： H03D13/00 , H03L7/085
CPC分类号： H03D13/003 , H03D13/00 , H03L7/085
摘要： Known phase detectors have feedbackloops and do not function properly under severe conditions. By providing said phase detectors with difference establishers (1) for establishing differences between input signals and with selectors (2) for selecting one of said differences to be used as an output signal for phase locking purposes, the phase detectors operate better under more severe conditions, with any dead-zone having disappeared. Said selector (2) is a feedbackless selector, then a loop delay no longer exists, the linear range will not get any smaller for higher frequencies, the output jitter will not increase, for sampled input signals. Said selector (2) comprises latches (21,22) and a multiplexer (23). A converter (3) converts input signals into compensated input signals, via a buffer circuit (31,33) coupled to a replica circuit (32,34) per input signal, to provide input signals having substantially equal amplitudes and being compensated with process errors and temperature variations. The difference establisher (1) is based upon moduli or squares.

95. 发明公开

EP1021885A4 DIGITAL PHASE DISCRIMINATION BASED ON FREQUENCY SAMPLING 有权
标题翻译： DIGITAL鉴相器基于频率扫描
公开(公告)号：EP1021885A4
公开(公告)日：2005-04-06
申请号：EP98951028
申请日：1998-10-08
申请人： TROPIAN INC
发明人： SANDER WENDELL
IPC分类号： H03M3/02 , G01R25/00 , H03D13/00 , H04L7/00 , H04L7/033 , H04L7/04
CPC分类号： H04L7/0334 , G01R25/00 , H03D13/006 , H04L7/0045
摘要： The present invention provides a simple all digital method and apparatus (fig. 4) for determining the phase of a first clock signal (Fs) relative to a second clock signal (Fs). The first clock signal (Fs) may be a digital approximation of a periodic analog signal such as an RF signal. A sampling technique is employed that produces a stream of digital bits (X) containing relative phase information. From the stream of digital data bits is formed a digital word indicative of the relative phase (fig. 11A). The digital word may be formed using a digital filter (fig. 13). Advantageously, an extensive body of digital filtering techniques applicable to Sigma-Delta (sometimes referred to as Delta-Sigma) A/D converters (fig. 1) may be applied directly to he digital stream (X). By using an appropriately chosen weighting function, high accuracy may be obtained.

96. 发明公开

EP1365502A3 Phase detector for quadrature signals, and method 有权
标题翻译：对于正交信号及其方法相位检测器
公开(公告)号：EP1365502A3
公开(公告)日：2004-04-14
申请号：EP03009580.6
申请日：2003-04-29
申请人： DEERE & COMPANY
发明人： Mason, Dawn Marie , Easton, David Joseph
IPC分类号： H03D13/00
CPC分类号： G05B9/02 , G01P21/02 , H03D13/00
摘要： A system and method is provided for use in a control system, such as a steering control system, for validating quadrature signals. A system makes a determination of validity based on the timing of detected state changes in the quadrature signals. To accomplish this, the amount of time that elapses between successive transitions is compared to the amount of time that elapses in an adjacent time period. If the two time periods are close enough, the signals are considered valid.

97. 发明公开

EP1115205A4 PLL CIRCUIT AND RADIO COMMUNICATION TERMINAL USING PLL 失效转让
标题翻译： PLL-SCHALTUNG UND FUNKBETRIEBENESKOMMUNIKATIONSSENDEGERÄTMIT EINER PHASENREGELSCHLEIFE
公开(公告)号：EP1115205A4
公开(公告)日：2004-03-24
申请号：EP99943334
申请日：1999-09-14
申请人： HITACHI LTD , TTP COMMUNICATIONS LTD
发明人： YAMAWAKI TAIZO , ENDO TAKEFUMI , WATANABE KAZUO , HORI KAZUAKI , HILDERSLEY JULIAN
IPC分类号： H03L7/10 , H03D13/00 , H03L7/00 , H03L7/08 , H03L7/085 , H03L7/093 , H03L7/099 , H03L7/107 , H03L7/16 , H03L7/18 , H04B1/3822 , H04B1/40 , H04L7/033
CPC分类号： H03L7/10 , H03D13/007 , H03L7/08 , H03L7/085 , H03L7/093 , H03L7/099 , H03L7/16 , H03L2207/12 , H04B1/406
摘要： A PLL circuit requiring only one LPF is provided to decrease the mounting area and the number of pins and simplify its design, whereas the prior art PLL circuit requires an n number of LPFs. The PLL circuit comprises a variable-gain phase comparator (1), a mixer (2), LPPs (3), n VCOs (4-1 - 4-n), n couplers (5-1 - 5-n), and a control circuit (6) for performing the ON/OFF control of the VCO operation, and the phase difference conversion gain of the variable-gain phase comparator (1) is variable. The control circuit (6) carries out the ON/OFF control of the operation of the VCOs (4-1 - 4-n), and one of the VCOs (4-1 - 4-n) operates depending on a desired operation frequency band, while other VCOs are off. The phase difference conversion gain can be varied depending on the sensitivity of the VCOs (4-1 - 4-n), resulting in the required number of LPFs reduced to one.
摘要翻译：提供了PLL电路和使用PLL电路的无线通信终端装置。在PLL电路中，已经需要的n个LPF的数量减少到仅一个LPF，使得PLL电路可以减少安装面积和引脚数量，并且可以简化其设计。根据本发明的PLL电路包括可变增益相位比较器1，混频器2，LPF 3，n个VCO 4-1至4n，n个耦合器5-1至5-n，以及控制电路6，用于控制VCO的操作的开/关。可变增益相位比较器1是能够改变相位差增益的相位比较器。通过控制电路6，根据期望的工作频带来操作VCO 4-1至4n和VCO 4-1至4-n中的一个的操作的导通/截止; 其他VCO被控制为关闭状态。相位差转换增益根据VCO 4-1至4-n的灵敏度而变化，从而可将PLL电路所需的LPF数减少到仅一个。

98. 发明授权

EP1115198B1 Frequency detector and phase-locked loop circuit including the detector 有权
标题翻译：频率检测器，并且具有这样的检测器的锁相环电路
公开(公告)号：EP1115198B1
公开(公告)日：2004-03-03
申请号：EP00128707.7
申请日：2000-12-29
申请人： Matsushita Electric Industrial Co., Ltd.
发明人： Dosho, Shiro , Yanagisawa, Naoshi , Toyama, Masaomi
IPC分类号： H03D13/00 , H03L7/087 , H03L7/089
CPC分类号： H03D13/004 , H03L7/087 , H03L7/0891 , H03L7/18

99. 发明公开

EP1381153A1 Multiplexer input circuit with DLL phase detector 有权
标题翻译： Einangsschaltungfüreinen多路复用器eeem DLL Phasendetector
公开(公告)号：EP1381153A1
公开(公告)日：2004-01-14
申请号：EP02360209.7
申请日：2002-07-12
申请人： ALCATEL
发明人： Wedding, Berthold
IPC分类号： H03D13/00 , H03L7/085 , H04J3/04 , H04J3/06
CPC分类号： H03D13/003 , H03L7/091 , H04J3/047 , H04J3/0685 , H04L7/0037
摘要： An input circuit, in particular for a multiplexer, for phase controlling of a data input signal with a clock signal, comprises a flip-flop (1), wherein the data signal is fed to a clock input of the flip-flop and the clock signal is fed to the data input of the flip-flop, and wherein the data output of the flip-flop is used as a control signal of a locked loop.
An advantage of the invention is, that it is of simple design which makes the invention especially useful for high frequencies. The data output of the flip-flop is dependent on the phase relationship of the data input signal with respect to the clock signal.
摘要翻译：特别是用于多路复用器的输入电路，用于对具有时钟信号的数据输入信号进行相位控制，包括触发器（1），其中数据信号被馈送到触发器和时钟的时钟输入信号被馈送到触发器的数据输入端，并且其中触发器的数据输出被用作锁定环路的控制信号。本发明的一个优点是设计简单，这使得本发明对于高频特别有用。触发器的数据输出取决于数据输入信号相对于时钟信号的相位关系。

100. 发明授权

EP0683946B1 SYSTEME DE RECEPTION OU DE LECTURE SERIE D'INFORMATIONS AVEC ECHANTILLONNAGE A INTERVALLES REGULIERS 失效
标题翻译：系统，用于接收或读取的信息流作用的扫描PERIODICALLY
公开(公告)号：EP0683946B1
公开(公告)日：2003-05-28
申请号：EP95903380.4
申请日：1994-12-08
申请人： Thales
发明人： COLINEAU, Joseph , AUDOIN, Michel
IPC分类号： H04L7/02 , H03D13/00
CPC分类号： G11B20/10518 , G11B20/10037 , G11B20/10055 , G11B20/1403 , H04L7/0334

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