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1. 发明公开

EP4360210A1 CURRENT MODE SIGNAL PATH OF AN INTEGRATED RADIO FREQUENCY PULSE GENERATOR 审中-实审
公开(公告)号：EP4360210A1
公开(公告)日：2024-05-01
申请号：EP22735157.4
申请日：2022-06-20
申请人： International Business Machines Corporation
发明人： CHAKRABORTY, Sudipto , FRANK, David , BULZACCHELLI, John , JOSHI, Rajiv , FRIEDMAN, Daniel
IPC分类号： H03D7/14 , H03D7/16
CPC分类号： H03D7/165 , H03D7/1458 , H03D7/1441

2. 发明公开

EP3342039A1 LOW POWER AND AREA BOOTSTRAPPED PASSIVE MIXER WITH SHARED CAPACITANCES 有权
公开(公告)号：EP3342039A1
公开(公告)日：2018-07-04
申请号：EP16757874.9
申请日：2016-08-25
申请人： Telefonaktiebolaget LM Ericsson (PUBL)
发明人： MASTANTUONO, Daniele , MATTISSON, Sven
IPC分类号： H03D7/14 , H03D7/16 , H04L25/08
CPC分类号： H03D7/1466 , H03D7/1441 , H03D7/1458 , H03D7/165
摘要： In a passive mixer, switches and a capacitance are shared between bootstrapped mixing transistors, reducing the number of components required as compared to prior art bootstrap designs. Shared bootstrap circuits operate in an interleaved fashion between I and Q mixer circuits, at twice the LO frequency. That is, the shared bootstrap circuits in each I mixer circuit charge their capacitors in a first half-period of a clock, and connect the shared capacitor to the gate of an enabled mixing transistor in the second half-period. The shared bootstrap circuits in the Q mixer circuit charge their capacitors in the second half-period, and connect the shared capacitor to the gate of an enabled mixing transistor in the first half-period. One of two mixing transistors connected to each shared bootstrap circuit is alternately enabled during the clock signal half-periods that the shared bootstrap circuit is not charging its capacitor.

3. 发明授权

EP2773038B1 Receiving device 有权
公开(公告)号：EP2773038B1
公开(公告)日：2017-09-13
申请号：EP14152448.8
申请日：2014-01-24
申请人： FUJITSU LIMITED
发明人： Sato, Masaru
IPC分类号： H03G3/30 , H04B17/00
CPC分类号： H03D1/10 , H03D7/02 , H03D7/165 , H03G3/3052

4. 发明公开

EP3175550A1 CONVERTISSEUR NUMÉRIQUE DE FRÉQUENCE ET PROCÉDÉ DE TRAITEMENT DANS UN CONVERTISSEUR NUMÉRIQUE DE FRÉQUENCE 有权
标题翻译： CONVERTISSEURNUMÉRIQUEDEFRÉQUENCEETPROCÉDÉDE TRAITEMENT DANS UN CONVERTISSEURNUMÉRIQUEDEFRÉQUENCE
公开(公告)号：EP3175550A1
公开(公告)日：2017-06-07
申请号：EP15762490.9
申请日：2015-07-30
申请人： Thales
发明人： JOLEC, François , DOUMENJOU, Anthony
IPC分类号： H03D3/00 , H03D7/00 , H03H17/02 , H03H17/06
CPC分类号： H03D7/165 , H03D2200/0062 , H03H17/0276 , H03H17/0664 , H03H2017/0247
摘要： Digital frequency converter and method of processing in a digital frequency converter Frequency converter comprising a block for frequency transposition of samples (11
Q_1 , 11
Q_3 ), a filtering block (12
Q_1 , 12
Q 3 ), the filtered samples y(n) satisfying y(n) =c(0).x(n) + c(1).x(n-1) + c(2).x(n-2)+...+c(p-1).x(n-p+1) + c(p).x(n-p) + c(p-1).x(n-p-1)+...+...+c(1).x(n-2.p+1) + c(0).x(n-2.p), where x() are the transposed samples and c(0),...c(p) are the real coefficients of the filter; and being adapted so as to, during a cycle of determination of the value of the filtered sample y(n): - calculate first terms c(0).x(n), c(1).x(n-1), c(2).x(n-2),..., c(p).x(n-p) by multiplying the coefficients and respective transposed samples, and storing said first calculated terms; - read second terms c(p-1).x(n-p-1),..., c(1).x(n-2.p+1), c(0).x(n-2.p), calculated and stored during previous cycles of determination of the value of filtered samples y(n-m); and - determine y(n) by summing the first and second terms.
摘要翻译：数字频率转换器和数字频率转换器中的处理方法一种变频器，包括用于样本频率转置的模块（11Q_1,11Q_3），滤波模块（12Q_1,12Q 3），满足y（n）的滤波样本y（n）（1）.x（n-1）+ c（2）.x（n-2）+ ... + c（p-1）.x（n- （p-1）+ c（p）.x（np）+ c（p-1）.x（np-1）+ ... + ... + c（1）.x（n-2.p + 1）+ c（0）.x（n-2.p），其中x（）是转置样本，c（0），... c（p）是滤波器的实系数。（n）的值的确定周期期间： - 计算第一项c（0）.x（n），c（1）.x（n-1）， c（2）.x（n-2），...，c（p）.x（np），并存储所述第一计算项; - 读取第二项c（p-1）.x（np-1），...，c（1）.x（n-2.p + 1），c（0）.x（n-2.p ），在过滤样本y（nm）的值的确定的先前周期期间被计算和存储; 和 - 通过将第一和第二项相加来确定y（n）。

5. 发明公开

EP3050210A1 HARMONIC REJECTIVE PASSIVE FREQUENCY UP CONVERTER 有权
标题翻译： HARMONISCHER REJEKTIVER PASSIVERFREQUENZAUFWÄRTSWANDLER
公开(公告)号：EP3050210A1
公开(公告)日：2016-08-03
申请号：EP14780727.5
申请日：2014-09-22
申请人： Qualcomm Incorporated
发明人： VORA, Sameer Vasantlal , DUNWORTH, Jeremy Darren
IPC分类号： H03D7/14 , H03D7/16
CPC分类号： H03D7/165 , H03D7/1441 , H03D7/1458 , H03D7/1466 , H03D7/166 , H03D2200/0086
摘要： Methods and apparatuses are presented for harmonic reject upconverting a baseband signal using at least one quadrature passive upconversion mixer. In some embodiments, an apparatus may include a first quadrature passive mixer configured to receive a first baseband input and a first LO input, and a second quadrature passive mixer configured to receive a second baseband input and a second LO input. A first output of said first passive mixer may be directly connected to a first output of said second passive mixer and together coupled to a first amplifier input. A second output of said first passive mixer may be directly connected to a second output of said second passive mixer and together coupled to a second amplifier input. The transmitter may be configured to output an upconverted signal with at least one rejected harmonic spurious mixing product based on the first and second amplifier inputs.
摘要翻译：提出了使用至少一个正交无源上变频混频器对谐波抑制上变频基带信号的方法和装置。在一些实施例中，设备可以包括被配置为接收第一基带输入和第一LO输入的第一正交无源混频器，以及被配置为接收第二基带输入和第二LO输入的第二正交无源混频器。所述第一无源混频器的第一输出可以直接连接到所述第二无源混频器的第一输出端并且一起耦合到第一放大器输入端。所述第一无源混频器的第二输出可以直接连接到所述第二无源混频器的第二输出端并且一起耦合到第二放大器输入端。发射机可以被配置为基于第一和第二放大器输入，输出具有至少一个拒绝谐波杂散混合乘积的上变频信号。

6. 发明公开

EP3025425A1 SUPPRESSION OF SPURIOUS HARMONICS GENERATED IN TX DRIVER AMPLIFIERS 有权
标题翻译：德克萨斯州德克萨斯州的UNTERDRÜCKUNGUNECHTER OBERSCHWINGUNGEN
公开(公告)号：EP3025425A1
公开(公告)日：2016-06-01
申请号：EP14750265.2
申请日：2014-07-18
申请人： Qualcomm Incorporated
发明人： VORA, Sameer Vasantlal , LAU, Wing Fat Andy
IPC分类号： H03F1/32 , H03D7/14 , H03F3/189 , H03F3/24 , H03F3/60
CPC分类号： H04B1/0483 , H03D7/165 , H03D2200/0086 , H03F1/32 , H03F3/189 , H03F3/24 , H03F3/602 , H03F2200/165 , H03F2200/336
摘要： The transmission path of a communication device includes, in part, N upconverters each of which receives M phases of a signal to be transmitted. Each upconverter further receives one of N sets of phases of a LO signal. Each of the N sets includes M phases of the LO signal. The communication device further includes at least one combiner, and N amplifiers each responsive to a different one of the N upconverters to generate N amplified signals. The combiner combines the N amplified signals to generate an output signal. By selecting the gain of one of the amplifiers to be different than the gain of the remaining amplifiers, the undesired harmonics of the signal to be transmitted, caused by non-linearity of the amplifiers, is reduced. Each upconverter optionally includes a multitude of upconverters whose outputs are combined to further reduce the spurious harmonic upconversion products and the counter-intermodulation distortion (IM3).
摘要翻译：通信设备的传输路径部分地包括N个上变频器，每个上变频器接收要发送的信号的M个相位。每个上变频器还接收LO信号的N组相位中的一个。 N组中的每一个包括LO信号的M个相位。通信设备还包括至少一个组合器和N个放大器，每个放大器响应于N个上变频器中的不同的一个以产生N个放大信号。组合器组合N个放大的信号以产生输出信号。通过选择放大器之一的增益与剩余放大器的增益不同，由放大器的非线性引起的要发送的信号的不期望的谐波减小。每个上变频器可选地包括多个上变频器，其输出被组合以进一步减少寄生谐波上变频产物和反相互调制失真（IM3）。

7. 发明公开

EP2983289A1 PASSIVE MIXER WITH REDUCED SECOND ORDER INTERMODULATION 有权
标题翻译：麻醉机麻醉机麻醉机互动器ZWEITER ORDNUNG
公开(公告)号：EP2983289A1
公开(公告)日：2016-02-10
申请号：EP15002353.9
申请日：2009-10-23
申请人： Telefonaktiebolaget L M Ericsson (Publ)
发明人： Mattisson, Sven , Andreani, Pietro , Mastantuono, Daniele
IPC分类号： H03D1/04 , H03D3/04 , H03D7/14 , H03D7/12 , H03D7/16
CPC分类号： H03D1/04 , H03D7/12 , H03D7/1458 , H03D7/1466 , H03D7/165 , H03D2200/0088
摘要： The present disclosure generally relates to the field of receiver structures in radio communication systems and more specifically to passive mixers in the receiver structure and to a technique for converting a first signal having a first frequency into a second signal having a second frequency by using a third signal having a third frequency. A passive mixer for converting a first signal having a first frequency into a second signal having a second frequency by using a third signal having a third frequency comprises a cancellation component 220 for generating a first cancellation signal for cancelling second order intermodulation components by superimposing the first signal weighted by a cancellation value on the third signal; and a mixing component 231 having a first terminal 232 for receiving the first signal, a second terminal 234 for outputting the second signal, and a third terminal 236 for receiving the first cancellation signal, wherein the mixing component 231 is adapted to provide the second signal as output at the second terminal 234 by mixing the first signal provided as input at the first terminal 232 and the first cancellation signal provided as input at the third terminal 236.
摘要翻译：本公开通常涉及无线电通信系统中的接收机结构领域，更具体地涉及接收机结构中的无源混频器以及通过使用第三频率将具有第一频率的第一信号转换成具有第二频率的第二信号的技术信号具有第三频率。一种无源混频器，用于通过使用具有第三频率的第三信号将具有第一频率的第一信号转换为具有第二频率的第二信号包括消除部件220，用于产生用于通过将第一频率叠加的第二次互调分量信号由第三信号上的抵消值加权; 以及混合部件231，其具有用于接收第一信号的第一端子232，用于输出第二信号的第二端子234和用于接收第一抵消信号的第三端子236，其中混合部件231适于提供第二信号作为第二端子234处的输出，通过混合在第一端子232处作为输入提供的第一信号和在第三端子236处作为输入提供的第一抵消信号。

8. 发明公开

EP2634915A2 Quadrature radio frequency mixer with low noise and low conversion loss 有权
标题翻译： GeräuscharmerQuadraturfunkfrequenzmischer mit niedrigem Mischverlust
公开(公告)号：EP2634915A2
公开(公告)日：2013-09-04
申请号：EP13169779.9
申请日：2009-01-06
申请人： Qualcomm Incorporated
发明人： Cicalini, Alberto
IPC分类号： H03D7/14
CPC分类号： H03D7/1441 , H03D7/145 , H03D7/1458 , H03D7/165 , H03D2200/0084
摘要： In one embodiment of the invention, a method for convolution of signals is disclosed including generating four phased half duty cycle clocks each being out of phase by a multiple of ninety degrees from the others; coupling the four phased half duty cycle clocks into a four phase half duty cycle mixer; and switching switches in the four phase half duty cycle mixer in response to the four phased half duty cycle clocks to convolve a differential input signal with the four phased half duty cycle clocks to concurrently generate a differential in-phase output signal and a differential quadrature-phase output signal on a dual differential output port.
摘要翻译：在本发明的一个实施例中，公开了一种用于卷积信号的方法，包括产生四个相位半占空比时钟，每个相位与其他相位相差90度的倍数; 将四个相位半占空比时钟耦合到四相半占空比混频器中; 和四相半占空比混频器中的开关开关，以响应于四个相位半占空比时钟，以将差分输入信号与四个相位半占空比时钟进行卷积，以同时产生差分同相输出信号和差分正交输出信号，双差分输出端口的相位输出信号。

9. 发明授权

EP2394359B1 POLYPHASE HARMONIC REJECTION MIXER 有权
标题翻译：多相谐波抑制混频器
公开(公告)号：EP2394359B1
公开(公告)日：2013-08-14
申请号：EP10703984.4
申请日：2010-02-03
申请人： NXP B.V.
发明人： RU, Zhiyu , KLUMPERINK, Eric A.M. , NAUTA, Bram , BREKELMANS, Johannes H.A.
IPC分类号： H03D7/16 , H03D7/14
CPC分类号： H03D7/165 , H03D7/14 , H03D7/1458 , H03D2200/0086

10. 发明公开

EP1969716A4 MIXER CIRCUIT AND RF TRANSMITTER USING SUCH MIXER CIRCUIT 审中-公开
标题翻译：混频器电路和RF这样的混频器电路发送器
公开(公告)号：EP1969716A4
公开(公告)日：2013-05-01
申请号：EP05821962
申请日：2005-12-22
申请人： INTEL MOBILE COMM GMBH
发明人： VAN WAASEN STEFAN , LANN ANNA-MARIA , STEPHANSSON PAUL , PUSA FREDRIK , DAHLIN JAN
IPC分类号： H03D7/14 , H03F3/19 , H03F3/45 , H03G3/30 , H04B1/04
CPC分类号： H03D7/1441 , H03D7/1433 , H03D7/1458 , H03D7/165 , H03D2200/0025 , H03D2200/0033 , H03D2200/0084 , H03F1/02 , H03F3/19 , H03F3/24 , H03F3/45188 , H04B2001/045

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