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91. 发明授权

EP0481751B1 Pipeline circuitry and method for allowing the comparison of the relative difference between two asynchronous pointers and a programmable value 失效
标题翻译：流水线电路和方法，用于比较两个异步指针和一个可编程的值之间的相对差
公开(公告)号：EP0481751B1
公开(公告)日：1998-07-29
申请号：EP91309521.2
申请日：1991-10-16
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： McClure, David Charles
IPC分类号： G06F5/06
CPC分类号： G06F5/12 , G01R29/0273 , G06F7/026 , G06F2205/126

92. 发明公开

EP0735374A3 Time counting circuit and counter circuit 失效
标题翻译： Zeit-ZählerschaltungundZählerschaltung
公开(公告)号：EP0735374A3
公开(公告)日：1997-12-10
申请号：EP96104994.7
申请日：1996-03-28
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： Kusumoto, Keiichi , Dosho, Shiro , Terada, Yutaka , Matsuzawa, Akira
IPC分类号： G01R29/027
CPC分类号： G01R29/0273
摘要： There is provided a time counting circuit for measuring a pulse spacing of a pulse signal with high accuracy and with low power consumption. An inverter ring composed of an odd number of inverters connected in a ring oscillates and one signal transition occurs after another as though seemingly circulating around the inverter ring. Holding circuits connected to respective output terminals of the inverters composing the inverter ring output, on the rising edge of a pulse signal to be measured, signals outputted from the inverters at the same time. The outputted signals are then converted by a signal converting circuit to numeric data. A counter circuit connected to the output terminal of one of the inverters composing the inverter ring counts the number of circulations of signal transition. A time-difference operating circuit corrects the numeric data outputted from the signal converting circuit based on the number of circulations of signal transition outputted from the counter circuit to provide time data, while calculating and outputting the pulse spacing of the pulse signal to be measured.
摘要翻译：提供了一种用于以高精度和低功耗测量脉冲信号的脉冲间隔的时间计数电路。由连接在环上的奇数个反相器组成的逆变器环振荡，并且一个信号转换发生在另一个之后，如同在逆变器环周围似乎循环一样。连接到构成逆变器环的逆变器的各个输出端的保持电路在待测脉冲信号的上升沿同时输出从逆变器输出的信号。然后，输出的信号被信号转换电路转换成数字数据。连接到构成逆变器环的逆变器之一的输出端子的计数器电路对信号转换的循环数进行计数。时差运算电路基于从计数电路输出的信号转换的循环次数，校正从信号变换电路输出的数值，提供时间数据，同时计算并输出待测脉冲信号的脉冲间隔。

93. 发明公开

EP0740073A1 Circuit for detecting an overvoltage on an electric load 失效
标题翻译： Schaltung zur Erkennung einerÜberspannungan einem elektrischen Verbraucher
公开(公告)号：EP0740073A1
公开(公告)日：1996-10-30
申请号：EP95830168.1
申请日：1995-04-28
申请人： CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO , SGS-THOMSON MICROELECTRONICS S.r.l.
发明人： Palara, Sergio , Sueri, Stefano , Schiaccianoce, Salvatore
IPC分类号： F02P17/12 , G01R29/027 , G01R31/38
CPC分类号： H01T13/60 , F02P17/12 , G01R29/0273
摘要： The invention relates to a circuit for detecting an overvoltage in an electrical load (Z1) inserted with a first and a second terminal between a feed line (AL) and a control switch (S), the circuit having an output voltage (Vout) at an output terminal (OUT) and comprising:

at least one first threshold comparator (C1) having a first input terminal held at a first reference voltage (E1), a second input terminal connected to the feed line (AL) and an output terminal,
at least one second threshold comparator (C2) having a first input terminal held at a second reference voltage (E2), a second input terminal connected to a second terminal of the electrical load (Z1), and an output terminal,
at least one output transistor (T1) inserted with a first and a second terminal between the feed line (AL) and an output terminal (OUT) of the circuit (1), the transistor (T1) being controlled by at least one logic block (D) having inputs connected to the outputs of the threshold comparators (C1) and (C2),
at least one feedback block (R) inserted with an input terminal and an output terminal respectively between the output terminal (OUT) of circuit (1) and a further input terminal to the logic block (D).
摘要翻译：本发明涉及一种用于检测在馈电线（AL）和控制开关（S）之间插入第一和第二端子的电负载（Z1）中的过电压的电路，该电路具有输出电压（Vout）在输出端子（OUT），并且包括：具有保持在第一参考电压（E1）的第一输入端子，连接到馈电线（AL）的第二输入端子和输出端子的至少一个第一阈值比较器（C1）具有保持在第二参考电压（E2）的第一输入端的至少一个第二阈值比较器（C2），连接到电负载（Z1）的第二端的第二输入端，以及输出端，至少一个输出晶体管（T1）被插入在馈电线（AL）和电路（1）的输出端（OUT）之间的第一和第二端子处，晶体管（T1）由至少一个逻辑块（D）控制，该逻辑块（D）具有连接到阈值比较器（C1）和（C2）的输出的输入分别在电路（1）的输出端（OUT）和逻辑块（D）的另一个输入端之间分别插入有输入端和输出端的至少一个反馈块（R）。

94. 发明公开

EP0735374A2 Time counting circuit and counter circuit 失效
标题翻译：时间计数器电路和计数器电路
公开(公告)号：EP0735374A2
公开(公告)日：1996-10-02
申请号：EP96104994.7
申请日：1996-03-28
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： Kusumoto, Keiichi , Dosho, Shiro , Terada, Yutaka , Matsuzawa, Akira
IPC分类号： G01R29/027
CPC分类号： G01R29/0273
摘要： There is provided a time counting circuit for measuring a pulse spacing of a pulse signal with high accuracy and with low power consumption.
An inverter ring composed of an odd number of inverters connected in a ring oscillates and one signal transition occurs after another as though seemingly circulating around the inverter ring. Holding circuits connected to respective output terminals of the inverters composing the inverter ring output, on the rising edge of a pulse signal to be measured, signals outputted from the inverters at the same time. The outputted signals are then converted by a signal converting circuit to numeric data. A counter circuit connected to the output terminal of one of the inverters composing the inverter ring counts the number of circulations of signal transition. A time-difference operating circuit corrects the numeric data outputted from the signal converting circuit based on the number of circulations of signal transition outputted from the counter circuit to provide time data, while calculating and outputting the pulse spacing of the pulse signal to be measured.

95. 发明授权

EP0425303B1 Delay measuring circuit 失效
标题翻译：延迟测量电路。
公开(公告)号：EP0425303B1
公开(公告)日：1995-05-24
申请号：EP90311759.6
申请日：1990-10-26
申请人： AT&T GLOBAL INFORMATION SOLUTIONS INTERNATIONAL INC.
发明人： van Driest, Hans , Kruithof, Richard , van Bokhorst, Hendrik
IPC分类号： G01R31/18
CPC分类号： G01R25/08 , G01R29/0273

96. 发明授权

EP0301084B1 APPARATUS AND METHOD FOR TESTING CONTACT INTERRUPTIONS OF CIRCUIT INTERCONNECTION DEVICES 失效
标题翻译：设备和器件切换连接之间的检测联系中断。
公开(公告)号：EP0301084B1
公开(公告)日：1994-06-29
申请号：EP88902312.3
申请日：1988-02-10
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： WISSELL, Daniel
IPC分类号： G01M19/00 , G01R31/04 , G07C11/00
CPC分类号： G01R31/046 , G01R29/0273 , G01R31/026
摘要： Apparatus and method identify and measure random contact interruption events in a circuit interconnection device. A comparator circuit (41), adapted to be operated at high frequencies, identified when an interrupt even has occurred. The comparator circuit, as a result of the interruption event, causes a high frequency counter circuit (44-46) to count clock pulses. The count in the (clock) counter circuit is continuously applied to an RAM memory circuit (51-55), write-enabled at an addressed memory location. After the interrruption event is terminated, the RAM memory circuit (51-53) is no longer write enabled at the addressed location and the addressed location is changed (incremented) in preparation for the next event (38-39). The counter circuit is also reset to zero in preparation for the next interruption event. The number of counts from a clock unit having a known frequency provides the duration of the interruption event. With the use of a clock unit operated at 100 MHz, interrupt events from 10 nanoseconds to 9.99 microseconds can be identified. Because of the frequency at which the testing is performed, the input impedance of the comparator circuit must be matched to the impedance of the circuit interconnection device

97. 发明公开

EP0547292A1 Picosecond event timer 失效
标题翻译： ZeitmesserfürEreignisse im Picosekundenbereich。
公开(公告)号：EP0547292A1
公开(公告)日：1993-06-23
申请号：EP92113443.3
申请日：1992-08-06
申请人： Hewlett-Packard Company
发明人： Chu, David C. , Knotts, Thomas A.
IPC分类号： G04F10/00 , G04F10/04
CPC分类号： G01R29/0273
摘要： A circuit for time stamping event signals, e.g. zero-crossings, using coarse and fine timers. The fine timer (15) is a circuit section which subdivides a period from a phase-locked ring-oscillator (13) into 2N subparts (39). An event signal is timed by latching a digital representation of a particular subpart. The digital representation of the subpart is an N-bit dual thermometer code (41) which uniquely identifies each subpart with each adjacent subpart differing by only one bit. The subparts are made finer in time quantization than the propagation delay of one active element in the ring oscillator (13) by the use of linear combiner elements (71, 73, 75). The dual thermometer code (41), encoded post-latching into a binary code, forms the "fine" timing part of a binary word representation of the event time. The event (11) also latches the count states of a pair of lead-lag counters (150, 151) in a master-slave configuration counting ring oscillator periods. These counters change states respectively before and after the dual thermometer code turn-overs. Only one reading is chosen for recording as determined by the most significant bit of the fine code. The choice will always find an accurate and stable reading, and reject erroneous readings resulting from reading a counter in transition. The chosen counter reading, encoded to binary, forms the coarse timer (17) for the binary word representation of the event time. The coarse and fine binary words are butt-joinable to form the complete binary timing representation without further arithmetic processing.
摘要翻译：用于时间戳事件信号的电路，例如。过零点，使用粗细和定时器。精细定时器（15）是将锁相环形振荡器（13）的周期分为2N个子部分（39）的电路部分。通过锁定特定子部件的数字表示来定时事件信号。子部件的数字表示是N位双温度计代码（41），其唯一地标识每个子部分，其中每个相邻子部分仅差一位。通过使用线性组合器元件（71,73,75），子部件在时间量化中比在环形振荡器（13）中的一个有源元件的传播延迟更精细。编码后锁定成二进制码的双温度计代码（41）形成事件时间的二进制字表示的“精细”定时部分。事件（11）还在主从配置计数环形振荡器周期中锁存一对超前滞后计数器（150,151）的计数状态。这些计数器在双温度计代码转换之前和之后分别改变状态。只有一个读取被选择用于记录，由精细代码的最高有效位确定。选择将始终找到准确稳定的阅读，并拒绝在转换期间读取计数器导致的错误读数。编码为二进制的所选计数器读数形成事件时间的二进制字表示的粗定时器（17）。粗略和精细的二进制字是对接的，以形成完整的二进制定时表示，而无需进一步的算术处理。

98. 发明公开

EP0481751A3 Pipeline circuitry for allowing the comparison of the relative difference between two asynchronous pointers and a programmable value 失效
标题翻译：管道电路允许两个异步点之间的相对差异与可编程值的比较
公开(公告)号：EP0481751A3
公开(公告)日：1993-02-24
申请号：EP91309521.2
申请日：1991-10-16
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： McClure, David Charles
IPC分类号： G06F5/06
CPC分类号： G06F5/12 , G01R29/0273 , G06F7/026 , G06F2205/126
摘要： A first-in, first-out (FIFO) memory includes flag generation circuitry which utilizes a write clock counter and a read clock counter to provide the number of write clock pulses received since the previous write reset signal and the number of read clock pulses received by the FIFO since the previous read reset signal. Specific flag values are user-programmable and are stored electronically as binary numbers in registers. The connection between individual subtractor circuits and individual comparator circuits for making a difference comparison is performed by a program select decoder which utilizes the difference output of the subtractor circuit and the flag program value. False flag information is filtered by a bi-stable de-glitch circuit which includes a delay path to emulate operation of the counter, subtractor and comparator. The magnitude comparator is programmed one count away from the desired flag transition point. The filtered flag output is updated at the onset of each blanking interval, thus making it representative of the current state of the FIFO.

99. 发明公开

EP0459694A3 Circuit and method for monitoring voltage pulse widths 失效
标题翻译：用于监测电压脉冲宽度的电路和方法
公开(公告)号：EP0459694A3
公开(公告)日：1992-07-08
申请号：EP91304619.9
申请日：1991-05-22
申请人： SUNDSTRAND CORPORATION
发明人： Beg, Mirza Akmal
IPC分类号： G01R29/02 , G01R29/027
CPC分类号： G01R29/0273
摘要： The widths of pulses in an incoming pulse train are monitored by successively measuring the duration of the pulses in the pulse train and enabling a timing device when the duration of any of the pulses is more than a preselected magnitude. The timing device is reset and restarted when the duration of any of the pulses is greater than the preselected magnitude. An output signal, indicative of an acceptable condition, is produced when the timing device indicates the expiration of a predetermined time delay. An output signal, indicative of a non-acceptable condition, is produced when the duration of a pulse in the incoming pulse train exceeds the preselected magnitude. This invention encompasses both the pulse width monitoring method and circuits which perform this method.

100. 发明公开

EP0480596A3 Circuit and method for determining the duration of the time interval between two signals 有权转让
标题翻译：重复设备和方法
公开(公告)号：EP0480596A3
公开(公告)日：1992-07-01
申请号：EP91308683.1
申请日：1991-09-24
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Staab, David , Vijeh, Nader
IPC分类号： G01R29/027
CPC分类号： H04L12/44 , G01R29/0273 , H03K5/023 , H03K5/156 , H03K19/018578 , H04L12/46 , H04L25/0272 , H04L25/08 , H04L25/085 , H04L25/4904
摘要： A discrete integrated repeater device and port MAU/AUI functions shares resources among its several ports. The device includes a single multi-bit free running counter providing preselected timing intervals to a plurality of latches. A signal undergoing measurement clears the latch while a preselected timing signal sets the latch. Receipt of a timing signal at a set latch indicates success or failure of some particular condition under test. The device satisfies an IEEE 802.3 specification for execution of a link integrity test. The device is also able to selectively disable or enable the link integrity test function for particular ports. A plurality of latches, one associated with each port, is set upon carrier sense detection at the particular port. A token passing mechanism implemented with a daisy chained line coupled to each latch enables a polling of each latch to provide carrier sense information about each port in a serial format. The device shares a single PLL among all its ports by producing a logical sum of carrier sense inputs to enable activation of the PLL. A collision indication signal will override operation of the PLL to ensure data integrity and to allow the PLL to reacquire lock on its reference clock.

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