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1. 发明授权

EP0528742B1 Field effect transistor formed with wide-submicron gate 失效
标题翻译：具有栅极Submikronbreite场效应晶体管
公开(公告)号：EP0528742B1
公开(公告)日：1997-11-19
申请号：EP92480101.2
申请日：1992-07-10
申请人： International Business Machines Corporation
发明人： Hsieh, Chang-Ming , Kumar, Shantha Arakere , Hsu, Louis Lu-Chen , Tien Zu-Jean
IPC分类号： H01L21/28
CPC分类号： H01L29/66553 , H01L21/28132 , H01L29/42376 , H01L29/66545 , H01L29/6659 , H01L29/7833 , Y10S438/947

2. 发明公开

EP0601950A2 Method of producing a thin silicon-on-insulator layer 失效
标题翻译：韦尔法罕zur Herstellung einerdünnenSOI-Schicht。
公开(公告)号：EP0601950A2
公开(公告)日：1994-06-15
申请号：EP93480198.6
申请日：1993-11-19
申请人： International Business Machines Corporation
发明人： Bayer, Klaus Dietrich , Hsu, Louis Lu-Chen , Silvestri, Victor Joseph , Yapsir, Andrie S.
IPC分类号： H01L21/76 , H01L21/306
CPC分类号： H01L21/2007 , H01L21/76251 , Y10S148/012 , Y10S148/135 , Y10S438/981
摘要： A method of forming a thin silicon SOI layer by wafer bonding, the thin silicon SOI layer being substantially free of defects upon which semiconductor structures can be subsequently formed, is disclosed. The method comprises the steps of:

a) providing a first wafer comprising a silicon substrate (10) of a first conductivity type, a diffusion layer (12) of a second conductivity type formed thereon and having a first etch characteristic, a thin epitaxial layer (14) of the second conductivity type formed upon the diffusion layer and having a second etch characteristic different from the first etch characteristic of the diffusion layer, and a thin oxide layer (16) formed upon the thin epitaxial layer;
b) providing a second wafer comprising a silicon substrate (18) having a thin oxide layer (20) formed on a surface thereof;
c) wafer bonding said first wafer to said second wafer so that said thin oxide layers (16,20) bond to form a thick oxide layer (22);
d) removing the silicon substrate (10) of said first wafer in a controlled mechanical manner; and
e) removing the diffusion layer (12) of said first wafer using a selective dry low energy plasma process to expose the underlying thin epitaxial layer (14), the selective dry low energy plasma process providing an etch ratio of the first etch characteristic to the second etch characteristic such that the diffusion layer is removed with minimal formation of any shallow plasma radiation damage to the exposed underlying thin epitaxial layer. The exposed thin epitaxial layer (14) may be then used as standard to form active/passive devices.
摘要翻译：公开了一种通过晶片接合形成薄硅SOI层的方法，该薄硅SOI层基本上没有可以随后形成半导体结构的缺陷。该方法包括以下步骤：a）提供包括第一导电类型的硅衬底（10）和形成在其上并具有第一蚀刻特性的第二导电类型的扩散层（12）的第一晶片，薄的外延层（14），形成在所述扩散层上并具有与所述扩散层的第一蚀刻特性不同的第二蚀刻特性的第二导电类型和形成在所述薄外延层上的薄氧化物层（16）; b）提供包括在其表面上形成有薄氧化物层（20）的硅衬底（18）的第二晶片; c）将所述第一晶片晶片接合到所述第二晶片，使得所述薄氧化物层（16,20）结合以形成厚的氧化物层（22）; d）以受控的机械方式去除所述第一晶片的硅衬底（10）; 以及e）使用选择性干燥的低能量等离子体处理来去除所述第一晶片的扩散层（12）以暴露下面的薄外延层（14），所述选择性干燥低能量等离子体工艺将第一蚀刻特性的蚀刻比提供给第二蚀刻特征使得扩散层被去除，同时对暴露的下面的薄外延层的任何浅等离子体辐射损伤的形成最小。然后可以将暴露的薄外延层（14）用作标准以形成有源/无源器件。

3. 发明公开

EP0596824A1 Semiconductor device and wafer structure having a planar buried interconnect prepared by wafer bonding 失效转让
标题翻译：半导体装置及盘结构具有平面互连结构，通过磁盘团伙掩埋。
公开(公告)号：EP0596824A1
公开(公告)日：1994-05-11
申请号：EP93480151.5
申请日：1993-10-05
申请人： International Business Machines Corporation
发明人： Buti, Taqi N. , Joshi, Rajiv V. , Shepard, Joseph F. , Hsu, Louis Lu-Chen
IPC分类号： H01L23/535
CPC分类号： H01L25/50 , H01L21/743 , H01L21/76264 , H01L21/76275 , H01L21/76283 , H01L2924/0002 , Y10S148/012 , Y10S148/135 , Y10S438/977 , H01L2924/00
摘要： A wafer structure (10) suitable for the formation of semiconductor devices thereon and having a buried interconnect structure for interconnection of desired ones of the semiconductor devices according to a predetermined interconnection pattern and a method of making the same is disclosed. The wafer structure comprises a primary substrate (20) having a first thickness appropriate for the formation of the desired semiconductor devices. The primary substrate further comprises a) conductive interconnection pads (24) of a second thickness formed on a bottom surface of the primary substrate according to the predetermined interconnection pattern, b) first isolation pads (22) of a third thickness formed on the bottom surface of the primary substrate between the conductive interconnection pads, and c) interconnection pad caps (28) of a fourth thickness formed upon the surface of the interconnection pads opposite from the primary substrate, wherein the interconnection pad caps comprise a material suitable for wafer bonding, and further wherein the total thickness of the second thickness and the fourth thickness equals the third thickness. The structure further comprises a secondary substrate (30) having an oxide layer (32) thereon bonded to the interconnection pad caps and the first isolation pads of the primary wafer.
摘要翻译：一种晶片结构（10）适合于形成半导体器件在其上，并具有用于雅丁半导体器件的期望的人的互连掩埋互连结构到预定互连图案及其制造的方法游离缺失盘。晶片结构包括主基板（20），具有第一厚度适合于所需的半导体器件的形成。主基板进一步包括：a）形成在主基片的底表面雅丁到预定互连图案的第二厚度的导电互连焊盘（24）中，b）形成在所述底表面上的第三厚度的第一隔离垫（22）相反从主基板在所述互连焊盘的表面上形成的第四厚度的导电互连焊盘之间的主要底物，和c）互连垫帽（28），worin互连垫帽包括适合于晶片键合的材料制成，和另外worin第二厚度的总厚度和第四厚度等于第三厚度。该结构进一步包括在其上的键合到互连垫帽和主晶片的第一隔离垫的二次基板（30），具有氧化物层（32）上。

4. 发明公开

EP0570321A2 Bonded wafer structure having a buried insulator layer 失效
标题翻译： Struktur mit verbundenenKörpernmit begrabener Isolationsschicht。
公开(公告)号：EP0570321A2
公开(公告)日：1993-11-18
申请号：EP93480044.2
申请日：1993-04-19
申请人： International Business Machines Corporation
发明人： Beyer, Klaus Dietrich , Hsu, Louis Lu-Chen , Yuan, Tsorng-Dih , Hsieh, Chang-Ming , Kotecki, David Edward
IPC分类号： H01L21/76 , H01L21/20
CPC分类号： H01L21/76264 , H01L21/2007 , H01L21/76275 , H01L21/76283 , H01L21/76286 , Y10S148/012 , Y10S148/135
摘要： A wafer structure and a method of making the same, upon which semiconductor devices may be formed, comprises first and second wafers. The first wafer (20) comprises a first substrate (24) having a thin oxide layer (26a) formed on a bottom surface thereof ; the said first substrate having a characteristic thermal expansion coefficient. The second wafer (22) comprises a second substrate (28) having an insulation layer (30) formed on a top surface thereof, the insulation layer having a characteristic thermal expansion coefficient substantially matched with the characteristic thermal expansion coefficient of the first substrate and further having a high thermal conductivity. The second wafer further comprises a thin oxide layer (26b) formed on a top surface of the insulation layer, wherein the first thin oxide layer of the first wafer is bonded to the second thin oxide layer of the second wafer, to form a typical bonded wafer structure (10) that can be advantageously used in the fabrication of high speed high density integrated circuits.
摘要翻译：可以形成半导体器件的晶片结构及其制造方法包括第一和第二晶片。第一晶片（20）包括在其底表面上形成有薄氧化层（26a）的第一衬底（24）所述第一基板具有特征热膨胀系数。第二晶片（22）包括在其顶表面上具有绝缘层（30）的第二基板（28），该绝缘层具有与第一基板的特征热膨胀系数基本匹配的特征热膨胀系数具有高导热性。第二晶片还包括形成在绝缘层的顶表面上的薄氧化物层（26b），其中第一晶片的第一薄氧化物层结合到第二晶片的第二薄氧化物层，以形成典型的键合晶片结构（10），其可以有利地用于制造高速高密度集成电路。

5. 发明公开

EP0660390A3 Isolation structure using liquid phase oxide deposition 失效
标题翻译：使用GLID的沉积从液相绝缘结构。
公开(公告)号：EP0660390A3
公开(公告)日：1997-07-09
申请号：EP94480153.9
申请日：1994-11-24
申请人： International Business Machines Corporation
发明人： Galli, Carol , Ogura, Seiki , Hsu, Louis Lu-Chen , Shepard, Joseph Francis
IPC分类号： H01L21/76 , H01L21/316
CPC分类号： H01L21/76224 , H01L21/02164 , H01L21/02282
摘要： A shallow trench isolation structure is formed by a process having a reduced number of steps and thermal budget by filling trenches by liquid phase deposition of an insulating semiconductor oxide and heat treating the deposit to form a layer of high quality thermal oxide at an interface between the deposited oxide and the body of semiconductor material (e.g. substrate) into which the trench extends. This process yields an isolation structure with reduced stress and reduced tendency to develop charge leakage. First, a trench (18) is formed in a silicon substrate (12) having a thin blanket layer (14) of a hard polish-stop material and a photo resist layer (16) (used to pattern the structure) formed thereon. A channel stop region (20) is formed as standard in the trench. Next, the trench is filled with Si02 using liquid phase oxide deposition above the level of said thin layer. Then the photo resist layer is removed and the Si02 fill (22) is planarized. Finally, the Si02 fill is densified and during the thermal cycle, a thin layer (30) of thermal oxide is formed at the fill- substrate interface. The structure can be readily and easily planarized, and voids contamination of the deposited oxide are substantially eliminated by self-aligned deposition above the trench in the volume of apertures on the resist used to form the trench.

6. 发明公开

EP0706222A1 Dense flash semiconductor memory structure 失效
标题翻译： Dichte Flash-Halbleiterspeicheranordnung
公开(公告)号：EP0706222A1
公开(公告)日：1996-04-10
申请号：EP95480152.8
申请日：1995-10-03
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Acocella, Joyce Elizabeth , Hsu, Louis Lu-Chen , Rovedo, Nivo , Galli, Carol , Ogura, Seiki , Shepard, Joseph Francis
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11546 , Y10S148/117 , Y10S438/981
摘要： Improved packing density as well as improved performance and manufacturing yield is achieved in an electrically programmable memory by confining floating gate structures between isolation structures covered with a thin nitride layer. The confinement of the floating gate is achieved by planarization, preferably with a self-limiting chemical/mechanical polishing process, to the surface of the nitride layer covering the isolation structures. Gate oxide and control electrode connections can then be formed on a substantially planar surface without compromising the quality of the gate oxide or breakdown voltage the device must withstand for programming. Since severe topology is avoided over which these connections are formed, improved formation of low resistance connections, possibly including metal connections, are possible and allow scaling of transistors of the memory cells to be scaled to sizes not previously possible.
摘要翻译：通过将浮置栅极结构限制在被薄氮化物层覆盖的隔离结构之间，在电可编程存储器中实现了提高的封装密度以及改进的性能和制造产量。浮栅的限制是通过平面化，优选采用自限制化学/机械抛光工艺，覆盖覆盖隔离结构的氮化物层的表面来实现的。然后可以在基本平坦的表面上形成栅极氧化物和控制电极连接，而不会损害器件必须承受编程的栅极氧化物的质量或击穿电压。由于避免了形成这些连接的严格的拓扑结构，所以可能包括可能包括金属连接的低电阻连接的改进形成，并且允许将存储器单元的晶体管缩放到先前不可能的尺寸。

7. 发明公开

EP0660184A2 Phase shift mask using liquid phase oxide deposition 失效
标题翻译： Phasenverschiebungsmaske unter Verwendung in derflüssigen相位abgelagerten Oxyd。
公开(公告)号：EP0660184A2
公开(公告)日：1995-06-28
申请号：EP94480144.8
申请日：1994-11-24
申请人： International Business Machines Corporation
发明人： Brunner, Timothy Allan , Dove, Derek Brian , Hsu, Louis Lu-Chen
IPC分类号： G03F1/14 , G03F1/00
CPC分类号： G03F1/30
摘要： Selective deposition of silica from a liquid phase solution of silica in hydrofluorosilicic acid through openings in a pattern of polyimide or similar organic material provides an optically improved phase shift mask structure for making lithographic exposures since deposition can be made substantially anisotropic to yield deposits of substantially uniform thickness. Deposition from the liquid phase is readily controlled and highly predictable control of deposition rate can be achieved by control of temperature of a low temperature deposition process. Therefore the optical quality of the mask need not be compromised by other structures, such as etch stop layers, otherwise necessary to achieve high phase shift accuracy and the deposits of phase shift material are substantially homogeneous. The process of deposition from the liquid phase can be stopped and started at will and the mask can be fabricated by a process which is substantially free from material-dependent or material-based process restrictions. The index of refraction of the deposited material can also be adjusted by annealing. More specifically, a substrates (30) is coated with, in order, an optional conductive thin film (32), an opaque mask material (34), a relatively thick polyamide layer (36), a barrier dielectric layer (38), and a resist layer (40) then, these layers above the conductive thin film are patterned in accordance with the desired pattern of opaque material in first regions (20) and the central feature shape in second region (10) for the particular type of rim phase shift mask structure illustrated herein. The remaining resist is removed during RIE of the polyamide and the barrier dielectric is then etched away by a CF 4 plasma etch and regions of the mask which are to have 0° relative phase shift are mask by depositing and patterning a first resist pattern (42). Next, an oxide layer (44) is deposited on the unmaksed regions of the substrate to an arbitrary depth corresponding to a desired amount of phase shift. These regions (44) are masked with a further deposition and patterning of a layer of resist (50). Finally the mask in accordance with the invention is then completed by stripping of the polyamide and polyamide. This completed mask alternates opaque regions with transparent regions of three different optical path lengths in first region (20).
摘要翻译：从二氧化硅的液相溶液中选择性沉积二氧化硅在氢氟硅酸中通过聚酰亚胺或类似有机材料图案的开口提供光学改进的相移掩模结构，用于制备平版印刷曝光，因为沉积可以基本上是各向异性的，以产生基本上均匀的沉积物厚度。易于控制液相的沉积，可以通过控制低温沉积工艺的温度来实现沉积速率的高度可预测的控制。因此，掩模的光学质量不需要被其它结构（例如蚀刻停止层）所影响，否则为实现高相移精度而必需，并且相移材料的沉积基本上是均匀的。从液相沉积的过程可以停止并随意开始，并且掩模可以通过基本上不含材料依赖的或基于材料的工艺限制的方法制造。沉积材料的折射率也可以通过退火进行调整。更具体地说，基片（30）依次涂覆有可选的导电薄膜（32），不透明掩模材料（34），较厚的聚酰胺层（36），阻挡介电层（38）和然后，抗蚀剂层（40），根据在第一区域（20）中的不透明材料的期望图案和第二区域（10）中的特定类型的边缘相位的中心特征形状，图案化导电薄膜上方的这些层移位掩模结构。在聚酰胺的RIE期间除去剩余的抗蚀剂，然后通过CF4等离子体蚀刻腐蚀掉阻挡介电层，并且通过沉积和图案化第一抗蚀剂图案（42）来掩模具有0°相对相位的掩模区域，。接下来，将氧化物层（44）沉积在基板的未粘合区域上，以对应于期望的相移量的任意深度。这些区域（44）被进一步沉积和图案化抗蚀剂层（50）。最后，根据本发明的掩模然后通过剥离聚酰胺和聚酰胺来完成。该完成的掩模在第一区域（20）中交替具有三个不同光程长度的透明区域的不透明区域。

8. 发明公开

EP0570043A2 Bicmos SOI wafer having thin and thick SOI regions of silicon 失效
标题翻译： SOI-ScheibefürBICMOS mitdünnenund dicken SOI-Siliziumgebieten。
公开(公告)号：EP0570043A2
公开(公告)日：1993-11-18
申请号：EP93201175.2
申请日：1993-04-22
申请人： International Business Machines Corporation
发明人： Buti, Taqi Nasser , Hsu, Louis Lu-Chen , Jost, Mark Edwin , Ogura Seiki NMN , Schulz, Ronald Norman
IPC分类号： H01L21/82 , H01L21/76 , H01L27/06 , H01L21/304
CPC分类号： H01L21/76264 , H01L21/76275 , H01L21/76281 , H01L21/76286 , H01L21/8249 , H01L29/78657 , Y10S148/009 , Y10S438/959
摘要： A SOI BiCMOS integrated circuit has CMOS devices formed in a thin epitaxial layer of 1000Å and bipolar devices formed in a thick epitaxial layer of 1µm, the two thicknesses being formed by a process in which a set of oxide islands are formed on a first wafer; an epitaxial layer is grown from bipolar silicon regions up and over the islands in a step that forms the bottom portion of the bipolar regions; the first wafer is inverted and oxide- bonded to a second wafer with the newly grown epitaxial layer below the islands so that the new top surface has a high quality epitaxial layer; excess silicon is removed from the new surface and the surface is polished to a thickness of 1000Å over the islands by use of a nitride polish stop layer, leaving a thick layer of epitaxial silicon of 1µm in the bipolar regions and a 1000Å thick layer of epitaxial silicon in the CMOS regions.
摘要翻译： SOI BiCMOS集成电路具有形成在1000个ANGSTROM的薄外延层中的CMOS器件和形成在1μm的厚外延层中的双极器件，两个厚度通过其中一组氧化物岛形成在第一片; 在形成双极区域的底部的步骤中，从双极硅区域向上和在岛上生长外延层; 第一晶片被倒置并且氧化物结合到第二晶片，其中新生长的外延层在岛下方，使得新的顶表面具有高质量的外延层; 从新表面去除多余的硅，并且通过使用氮化物抛光停止层在岛上将表面抛光至1000的厚度，在双极性区域中留下1μm厚的外延硅的外延层，以及1000 ANGSTROM 在CMOS区域中厚的外延硅层。

9. 发明公开

EP0392954A3 A Lateral transistor and method of making same 失效
标题翻译：一种横向晶体管及其制造方法
公开(公告)号：EP0392954A3
公开(公告)日：1992-08-12
申请号：EP90480025.7
申请日：1990-02-20
申请人： International Business Machines Corporation
发明人： Desilets, Brian Henry , Hsieh, Chang-Ming , Hsu, Louis Lu-Chen
IPC分类号： H01L21/285 , H01L21/331 , H01L29/73
CPC分类号： H01L29/6625 , H01L21/763 , H01L29/41708 , H01L29/735 , Y10S148/05
摘要： A method of fabricating a lateral transistor (110) is provided, including the steps of: providing a body of semiconductor material including a device region (30) of a first conductivity type (N⁺); patterning the surface of the device region to define a first transistor region (44); filling the patterned portion of the device region surrounding the first transistor region with an insulating material to a height generally equal to the surface of said first transistor region; removing portions of the insulating material so as to define a pair of trenches (22) generally bounding opposite sides of the first transistor region; filling the pair of trenches with doped conductive material (26) of opposite conductivity type to the first transistor region; and annealing the semiconductor body whereby to form second and third transistor regions (96,98) of opposite conductivity type to the first transistor region (44) in the opposing sides of the first transistor region completing the process to provide contact electrodes (102, 104, 106).

10. 发明公开

EP0690514A3 SOI transistor having a self-aligned body contact 失效
标题翻译： SOI-Transistor mit einem selbstausrichtenden Substrat-Kontakt
公开(公告)号：EP0690514A3
公开(公告)日：1998-02-11
申请号：EP95480050.4
申请日：1995-04-27
申请人： International Business Machines Corporation
发明人： Beyer, Klaus Dietrich , Buti, Tagi Nasser , Hsieh, Chang-Ming , Hsu, Louis Lu-Chen
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/66772 , H01L29/41783 , H01L29/78612 , Y10S148/15
摘要： An SOI transistor has a self-aligned body contact (140) formed through an extension (210) to the gate, thereby forming the body contact with minimal increase in area and also avoiding the need to tie the source to the body, as in prior art schemes that passed the body contact through the source. The body contact aperture is formed by raising the source and drain to define an initial aperture, depositing a conformal layer that is etched to create aperture-defining sidewalls and etching the contact aperture using these sidewalls to define sidewall support members that support insulating sidewalls to isolate the collection electrode from both the gate and from the source and drain.
摘要翻译：制造商。涉及一种SOI FET，其包括在掺杂到第二极性并形成在绝缘基板（50）和栅极绝缘体（101）和栅极（110）上方的Si层中掺杂有第一极性的源极（116）和漏极（114）放置在源极和漏极之间的Si层的上方，并且具有连接到栅极并且还放置在栅极绝缘体上方并且位于Si层的集合部分上方的栅极延伸部（210）。收集电极放置在门延伸部的收集侧上。

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