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1. 发明公开

EP0660390A2 Isolation structure using liquid phase oxide deposition 失效
标题翻译： Isolationsstruktur unter Verwendung einer Ablagerung von Glid aus derflüssigenPhase。
公开(公告)号：EP0660390A2
公开(公告)日：1995-06-28
申请号：EP94480153.9
申请日：1994-11-24
申请人： International Business Machines Corporation
发明人： Galli, Carol , Ogura, Seiki , Hsu, Louis Lu-Chen , Shepard, Joseph Francis
IPC分类号： H01L21/76 , H01L21/316
CPC分类号： H01L21/76224 , H01L21/02164 , H01L21/02282
摘要： A shallow trench isolation structure is formed by a process having a reduced number of steps and thermal budget by filling trenches by liquid phase deposition of an insulating semiconductor oxide and heat treating the deposit to form a layer of high quality thermal oxide at an interface between the deposited oxide and the body of semiconductor material (e.g. substrate) into which the trench extends. This process yields an isolation structure with reduced stress and reduced tendency to develop charge leakage. First, a trench (18) is formed in a silicon substrate (12) having a thin blanket layer (14) of a hard polish-stop material and a photo resist layer (16) (used to pattern the structure) formed thereon. A channel stop region (20) is formed as standard in the trench. Next, the trench is filled with Si02 using liquid phase oxide deposition above the level of said thin layer. Then the photo resist layer is removed and the Si02 fill (22) is planarized. Finally, the Si02 fill is densified and during the thermal cycle, a thin layer (30) of thermal oxide is formed at the fill- substrate interface. The structure can be readily and easily planarized, and voids contamination of the deposited oxide are substantially eliminated by self-aligned deposition above the trench in the volume of apertures on the resist used to form the trench.
摘要翻译：浅沟槽隔离结构通过具有减少步数和热预算的工艺形成，通过用绝缘半导体氧化物的液相沉积填充沟槽并热处理该沉积物以在层间的界面处形成高质量的热氧化物层沉积的氧化物和沟槽延伸到其中的半导体材料（例如衬底）的主体。该方法产生具有减小的应力和减小的电荷泄漏倾向的隔离结构。首先，在具有形成在其上的硬抛光停止材料的薄橡皮布层（14）和形成在其上的光致抗蚀剂层（16）（用于图案化）的硅衬底（12）中形成沟槽（18）。在沟槽中标准形成沟道停止区域（20）。接下来，使用在所述薄层的水平面上方的液相氧化物沉积来填充沟槽。然后去除光致抗蚀剂层，并且SiO 2填充物（22）被平坦化。最后，SiO 2填充被致密化，并且在热循环期间，在填充 - 衬底界面处形成热氧化物薄层（30）。该结构可以容易且容易地平坦化，并且通过在用于形成沟槽的抗蚀剂上的孔的体积中的沟槽之上的自对准沉积，基本上消除了沉积的氧化物的空隙污染。

2. 发明公开

EP0660390A3 Isolation structure using liquid phase oxide deposition 失效
标题翻译：使用GLID的沉积从液相绝缘结构。
公开(公告)号：EP0660390A3
公开(公告)日：1997-07-09
申请号：EP94480153.9
申请日：1994-11-24
申请人： International Business Machines Corporation
发明人： Galli, Carol , Ogura, Seiki , Hsu, Louis Lu-Chen , Shepard, Joseph Francis
IPC分类号： H01L21/76 , H01L21/316
CPC分类号： H01L21/76224 , H01L21/02164 , H01L21/02282
摘要： A shallow trench isolation structure is formed by a process having a reduced number of steps and thermal budget by filling trenches by liquid phase deposition of an insulating semiconductor oxide and heat treating the deposit to form a layer of high quality thermal oxide at an interface between the deposited oxide and the body of semiconductor material (e.g. substrate) into which the trench extends. This process yields an isolation structure with reduced stress and reduced tendency to develop charge leakage. First, a trench (18) is formed in a silicon substrate (12) having a thin blanket layer (14) of a hard polish-stop material and a photo resist layer (16) (used to pattern the structure) formed thereon. A channel stop region (20) is formed as standard in the trench. Next, the trench is filled with Si02 using liquid phase oxide deposition above the level of said thin layer. Then the photo resist layer is removed and the Si02 fill (22) is planarized. Finally, the Si02 fill is densified and during the thermal cycle, a thin layer (30) of thermal oxide is formed at the fill- substrate interface. The structure can be readily and easily planarized, and voids contamination of the deposited oxide are substantially eliminated by self-aligned deposition above the trench in the volume of apertures on the resist used to form the trench.

3. 发明公开

EP0706222A1 Dense flash semiconductor memory structure 失效
标题翻译： Dichte Flash-Halbleiterspeicheranordnung
公开(公告)号：EP0706222A1
公开(公告)日：1996-04-10
申请号：EP95480152.8
申请日：1995-10-03
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Acocella, Joyce Elizabeth , Hsu, Louis Lu-Chen , Rovedo, Nivo , Galli, Carol , Ogura, Seiki , Shepard, Joseph Francis
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11546 , Y10S148/117 , Y10S438/981
摘要： Improved packing density as well as improved performance and manufacturing yield is achieved in an electrically programmable memory by confining floating gate structures between isolation structures covered with a thin nitride layer. The confinement of the floating gate is achieved by planarization, preferably with a self-limiting chemical/mechanical polishing process, to the surface of the nitride layer covering the isolation structures. Gate oxide and control electrode connections can then be formed on a substantially planar surface without compromising the quality of the gate oxide or breakdown voltage the device must withstand for programming. Since severe topology is avoided over which these connections are formed, improved formation of low resistance connections, possibly including metal connections, are possible and allow scaling of transistors of the memory cells to be scaled to sizes not previously possible.
摘要翻译：通过将浮置栅极结构限制在被薄氮化物层覆盖的隔离结构之间，在电可编程存储器中实现了提高的封装密度以及改进的性能和制造产量。浮栅的限制是通过平面化，优选采用自限制化学/机械抛光工艺，覆盖覆盖隔离结构的氮化物层的表面来实现的。然后可以在基本平坦的表面上形成栅极氧化物和控制电极连接，而不会损害器件必须承受编程的栅极氧化物的质量或击穿电压。由于避免了形成这些连接的严格的拓扑结构，所以可能包括可能包括金属连接的低电阻连接的改进形成，并且允许将存储器单元的晶体管缩放到先前不可能的尺寸。

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