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1. 发明授权

US06501702B2 Semiconductor memory integrated circuit 失效
标题翻译：半导体存储器集成电路
公开(公告)号：US06501702B2
公开(公告)日：2002-12-31
申请号：US09866065
申请日：2001-05-25
申请人： Teruo Takagiwa , Masami Masuda
发明人： Teruo Takagiwa , Masami Masuda
IPC分类号： G11C300
CPC分类号： G11C29/832 , G11C8/06 , G11C8/10 , G11C29/781
摘要： An address buffer includes a latch circuit, and is controlled by an internal clock signal sent from a clock buffer. A decoding circuit section for selecting a word line is formed of a predecoder and a row decoder for further decoding a decoded output from the predecoder. The predecoder has no latching function, and the row decoder has a latch circuit. A pulse generating circuit generates two timing pulses based on a clock signal CK1. The activation of the row decoder is controlled by the two timing pulses.
摘要翻译：地址缓冲器包括一个锁存电路，由一个从时钟缓冲器发送的内部时钟信号控制。用于选择字线的解码电路部分由预解码器和行解码器形成，用于进一步解码来自预解码器的解码输出。预解码器没有锁存功能，行解码器具有锁存电路。脉冲发生电路基于时钟信号CK1产生两个定时脉冲。行解码器的激活由两个定时脉冲控制。

2. 发明授权

US06426916B2 Memory device having a variable data output length and a programmable register 失效
标题翻译：具有可变数据输出长度的存储器件和可编程寄存器
公开(公告)号：US06426916B2
公开(公告)日：2002-07-30
申请号：US09796206
申请日：2001-02-27
申请人： Michael Farmwald , Mark Horowitz
发明人： Michael Farmwald , Mark Horowitz
IPC分类号： G11C300
CPC分类号： G11C7/1066 , G06F11/006 , G06F11/1048 , G06F12/0215 , G06F12/0661 , G06F12/0684 , G06F13/1605 , G06F13/161 , G06F13/1678 , G06F13/1689 , G06F13/1694 , G06F13/376 , G11C5/04 , G11C5/066 , G11C7/1006 , G11C7/1012 , G11C7/1045 , G11C7/1051 , G11C7/1057 , G11C7/1069 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C7/225 , G11C8/00 , G11C11/4076 , G11C11/4096 , G11C29/88 , G11C2207/105 , G11C2207/108 , Y02D10/13 , Y02D10/14
摘要： A synchronous memory device and methods of operation and controlling such a device. The method of controlling the memory device includes providing a value which is representative of a number of cycles of an external clock signal to transpire after which the memory device responds to a read request. The method further includes providing block size information to the memory device, wherein the block size information defines an amount of data to be output by the memory device in response to a read request. The method further includes receiving the amount of data, after the number of clock cycles of the external clock signal transpire.
摘要翻译：一种同步存储装置及其操作和控制方法。控制存储器件的方法包括提供表示外部时钟信号的周期数的值，在此之后存储器件响应于读取请求。该方法还包括向存储器件提供块大小信息，其中块大小信息定义响应于读取请求由存储器件输出的数据量。该方法还包括在外部时钟信号的时钟周期数量发生之后接收数据量。

3. 发明授权

US06205084B1 Burst mode flash memory 有权
标题翻译：突发模式闪存
公开(公告)号：US06205084B1
公开(公告)日：2001-03-20
申请号：US09467758
申请日：1999-12-20
申请人： Takao Akaogi
发明人： Takao Akaogi
IPC分类号： G11C300
CPC分类号： G11C7/225 , G11C7/1051 , G11C7/106 , G11C7/22 , G11C7/222 , G11C16/26 , G11C16/32
摘要： A clock generator circuit in response to an external output enable signal generates an internal clock signal that is delayed to increase the reliability of the data outputted from the flash memory. A clock trigger generator circuit by decoding address signals generates an internal clock signal to reduce the latency time of the output of data with respect to the external clock signal. A bypass signal is provided to disable the clock trigger generator circuit. An output circuit provides a bypass data path to additionally reduce the latency time of the outputting of data for a burst mode flash memory. A decoder counter selector circuit provides a “look-ahead” address decoding scheme to reduce the time needed to output data.
摘要翻译：响应于外部输出使能信号的时钟发生器电路产生延迟的内部时钟信号，以增加从闪速存储器输出的数据的可靠性。通过解码地址信号的时钟触发发生器电路产生内部时钟信号，以减少数据相对于外部时钟信号输出的等待时间。提供旁路信号来禁止时钟触发发生器电路。输出电路提供旁路数据路径以额外地减少突发模式闪速存储器输出数据的等待时间。解码器计数器选择器电路提供“先行”地址解码方案，以减少输出数据所需的时间。

4. 发明授权

US06421296B1 Double protection virtual ground memory circuit and column decoder 有权
标题翻译：双保护虚拟接地存储器电路和列解码器
公开(公告)号：US06421296B1
公开(公告)日：2002-07-16
申请号：US09849056
申请日：2001-05-04
申请人： Lai-Ching Lin , Yu-Wei Lee , Sheau-Yung Shyu
发明人： Lai-Ching Lin , Yu-Wei Lee , Sheau-Yung Shyu
IPC分类号： G11C300
CPC分类号： G11C16/0491 , G11C16/24 , G11C16/26
摘要： A double protection virtual ground memory circuit and column decoder. Through the introduction of a double protection circuit, leakage current from the virtual ground memory is reduced and power consumed by the memory circuit is lowered. Ultimately, sensing range of data within the memory by a sense amplifier is improved.
摘要翻译：双重保护虚拟接地存储器电路和列解码器。通过引入双重保护电路，来自虚拟接地存储器的泄漏电流降低，存储电路消耗的功率降低。最终，由读出放大器感测存储器内的数据范围得到改善。

5. 发明授权

US06392949B2 High performance memory architecture 有权
公开(公告)号：US06392949B2
公开(公告)日：2002-05-21
申请号：US09761460
申请日：2001-01-16
申请人： George M. Braceras , Harold Pilo
发明人： George M. Braceras , Harold Pilo
IPC分类号： G11C300
CPC分类号： G11C11/417 , G11C7/1039 , G11C11/418
摘要： A high performance memory array architecture is provided to minimize the delays within each array. The architecture of the array equalizes the access time to all memory elements by optimizing the positioning of the subarrays with respect to buffering and rebuffering elements used in the array which cause delays.

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