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1. 发明授权

US08238172B2 Semiconductor memory device and method for controlling the same 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US08238172B2
公开(公告)日：2012-08-07
申请号：US12884951
申请日：2010-09-17
申请人： Teruo Takagiwa
发明人： Teruo Takagiwa
IPC分类号： G11C7/10
CPC分类号： G11C29/82
摘要： According to one embodiment, a semiconductor memory device includes a memory cell array, and first to third latch circuits. The first latch circuits hold information as to whether an associated column is defective. A pointer is set in the second latch circuits. The third latch circuits hold write data or read data. One of the third latch circuits is activated at a time the pointer is set to an associated second latch circuit when an associated first latch circuit holds the information indicating that the associated column is not defective. The pointer is sequentially shifted among the second latch circuits in synchronization with a clock. In shifting the pointer, the pointer skips one of the second latch circuits associated with one of the first latch circuit which holds the information indicating that the associated column is defective.
摘要翻译：根据一个实施例，半导体存储器件包括存储单元阵列和第一至第三锁存电路。第一个锁存电路保存关于相关联的列是否有故障的信息。在第二个锁存电路中设置一个指针。第三个锁存电路保持写数据或读数据。当相关联的第一锁存电路保持指示相关联的列没有缺陷的信息时，指针被设置为相关联的第二锁存电路时，第三锁存电路中的一个被激活。指针与时钟同步地顺序地在第二锁存电路之间移位。在移动指针时，指针跳过与第一锁存电路中的一个相关联的第二锁存电路之一，其中保持指示相关联的列有缺陷的信息。

2. 发明申请

US20130246730A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR WRITING THEREIN 有权
标题翻译：半导体存储器件及其写入方法
公开(公告)号：US20130246730A1
公开(公告)日：2013-09-19
申请号：US13603697
申请日：2012-09-05
申请人： Ayako YAMANO , Teruo Takagiwa , Koichi Fukuda , Hitoshi Shiga , Osamu Nagao
发明人： Ayako YAMANO , Teruo Takagiwa , Koichi Fukuda , Hitoshi Shiga , Osamu Nagao
IPC分类号： G06F12/08
CPC分类号： G06F12/0891 , G06F12/0246 , G06F2212/7209 , G11C11/5635 , G11C16/00 , G11C16/16 , Y02D10/13
摘要： According to one embodiment, a semiconductor memory device includes a plurality of blocks in a memory cell, each of the blocks acting as an erasure unit of data, the block including a plurality of pages, each of the pages including a plurality of memory cell transistors, each of the memory cell transistors being configured to be an erasure state or a first retention state based on a threshold voltage of the memory cell transistor, and a controller searching data in the block with respect to, writing a first flag denoting effective into a prescribed page of the block with the erasure state, and writing the first flag denoting non-effective into a prescribed page of the block with the first retention state, reading out the prescribed page of the block with the first retention state, and determining that the block is writable when the first flag denotes effective.
摘要翻译：根据一个实施例，半导体存储器件包括存储器单元中的多个块，每个块用作数据的擦除单元，该块包括多个页，每个页包括多个存储单元晶体管每个存储单元晶体管被配置为基于存储单元晶体管的阈值电压的擦除状态或第一保持状态，以及控制器搜索块中的数据，将表示有效的第一标志写入到具有擦除状态的块的规定页面，并且将表示无效的第一标志写入具有第一保持状态的块的规定页面，以第一保留状态读出块的规定页面，并且确定当第一个标志表示有效时，块是可写的。

3. 发明授权

US08437197B2 Nonvolatile semiconductor memory and method of operating the same 有权
标题翻译：非易失性半导体存储器及其操作方法
公开(公告)号：US08437197B2
公开(公告)日：2013-05-07
申请号：US13051388
申请日：2011-03-18
申请人： Teruo Takagiwa
发明人： Teruo Takagiwa
IPC分类号： G11C11/34
CPC分类号： G11C16/3436 , G11C11/5642
摘要： According to one embodiment, a nonvolatile semiconductor memory includes memory cells arranged in a memory cell array in the form of a matrix, the memory cell storing data having two or more levels associated with two or more threshold levels, respectively, a buffer circuit including latch circuits and sense amplifier circuits, each latch circuit and each sense amplifier being associated with each column in the memory cell array, and a control circuit configured to control operations of the memory cells and the buffer circuit, the control circuit executing data writing with respect to the memory cells and first verification using judgment information indicative of a result of the data writing in a write sequence with respect to data from the outside. The judgment information is assigned to two or more threshold levels, which are not adjacent to each other, in common.
摘要翻译：根据一个实施例，非易失性半导体存储器包括以矩阵形式布置在存储单元阵列中的存储单元，所述存储单元分别存储具有与两个或多个阈值电平相关联的两个或多个电平的数据，包括锁存器电路和读出放大器电路，每个锁存电路和每个读出放大器与存储单元阵列中的每一列相关联;以及控制电路，被配置为控制存储单元和缓冲电路的操作，控制电路执行相对于存储器单元和使用关于来自外部的数据的以写入序列表示数据写入的结果的判定信息的第一验证。判断信息被分配给彼此不相邻的两个或更多个阈值级别。

4. 发明授权

US08284612B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08284612B2
公开(公告)日：2012-10-09
申请号：US12884721
申请日：2010-09-17
申请人： Masahiro Yoshihara , Teruo Takagiwa , Katsumi Abe
发明人： Masahiro Yoshihara , Teruo Takagiwa , Katsumi Abe
IPC分类号： G11C16/06
CPC分类号： G11C16/3436
摘要： According to one embodiment, a semiconductor memory device includes memory cells, holding circuits, and a logical gate chain. The memory cells are associated with columns. The holding circuits are associated with the columns and capable of holding first information indicating whether associated one of the columns is a verify-failed column or not. The logical gate chain includes a plurality of first logical gates associated with the columns and connected in series. Each of the first logical gates outputs a logical level to a next-stage first logical gate in a series connection. The logical level indicates whether the verify-failed column exists or not based on the first information in associated one of the holding circuit. The content indicated by the logical level output from each of the first logical gates is inverted using one of the first logical gates associated with the verify-failed column as a border.
摘要翻译：根据一个实施例，半导体存储器件包括存储单元，保持电路和逻辑门极链。存储单元与列相关联。保持电路与列相关联，并且能够保存指示相关联的一个列是否为验证失败列的第一信息。逻辑门链包括与列相关联并且串联连接的多个第一逻辑门。第一逻辑门中的每一个在串联连接中将逻辑电平输出到下一级第一逻辑门。逻辑电平基于保持电路中相关联的一个中的第一信息指示验证失败列是否存在。使用与验证失败列相关联的第一逻辑门之一作为边界来反转从每个第一逻辑门输出的逻辑电平指示的内容。

5. 发明授权

US08391072B2 Semiconductor memory device and method for controlling the same 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US08391072B2
公开(公告)日：2013-03-05
申请号：US12884658
申请日：2010-09-17
申请人： Teruo Takagiwa
发明人： Teruo Takagiwa
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C16/3436
摘要： According to one embodiment, a semiconductor memory device includes a plurality of memory cells, and a plurality of latch circuits. The memory cells are associated with columns and are capable of storing data. The latch circuits are associated with the columns and are capable of storing write data and/or read data for the columns. The latch circuits are selectively activated, and activated latch circuits are capable of receiving and/or outputting data.
摘要翻译：根据一个实施例，半导体存储器件包括多个存储单元和多个锁存电路。存储单元与列相关联并且能够存储数据。锁存电路与列相关联，并且能够存储用于列的写入数据和/或读取数据。锁存电路被选择性地激活，并且激活的锁存电路能够接收和/或输出数据。

6. 发明申请

US20110205806A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20110205806A1
公开(公告)日：2011-08-25
申请号：US12884721
申请日：2010-09-17
申请人： Masahiro Yoshihara , Teruo Takagiwa , Katsumi Abe
发明人： Masahiro Yoshihara , Teruo Takagiwa , Katsumi Abe
IPC分类号： G11C16/34
CPC分类号： G11C16/3436
摘要： According to one embodiment, a semiconductor memory device includes memory cells, holding circuits, and a logical gate chain. The memory cells are associated with columns. The holding circuits are associated with the columns and capable of holding first information indicating whether associated one of the columns is a verify-failed column or not. The logical gate chain includes a plurality of first logical gates associated with the columns and connected in series. Each of the first logical gates outputs a logical level to a next-stage first logical gate in a series connection. The logical level indicates whether the verify-failed column exists or not based on the first information in associated one of the holding circuit. The content indicated by the logical level output from each of the first logical gates is inverted using one of the first logical gates associated with the verify-failed column as a border.
摘要翻译：根据一个实施例，半导体存储器件包括存储单元，保持电路和逻辑门极链。存储单元与列相关联。保持电路与列相关联，并且能够保存指示相关联的一个列是否为验证失败列的第一信息。逻辑门链包括与列相关联并且串联连接的多个第一逻辑门。第一逻辑门中的每一个在串联连接中将逻辑电平输出到下一级第一逻辑门。逻辑电平基于保持电路中相关联的一个中的第一信息指示验证失败列是否存在。使用与验证失败列相关联的第一逻辑门之一作为边界来反转从每个第一逻辑门输出的逻辑电平指示的内容。

7. 发明申请

US20110141823A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR CONTROLLING THE SAME 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US20110141823A1
公开(公告)日：2011-06-16
申请号：US12884951
申请日：2010-09-17
申请人： Teruo TAKAGIWA
发明人： Teruo TAKAGIWA
IPC分类号： G11C29/04 , G11C7/10
CPC分类号： G11C29/82
摘要： According to one embodiment, a semiconductor memory device includes a memory cell array, and first to third latch circuits. The first latch circuits hold information as to whether an associated column is defective. A pointer is set in the second latch circuits. The third latch circuits hold write data or read data. One of the third latch circuits is activated at a time the pointer is set to an associated second latch circuit when an associated first latch circuit holds the information indicating that the associated column is not defective. The pointer is sequentially shifted among the second latch circuits in synchronization with a clock. In shifting the pointer, the pointer skips one of the second latch circuits associated with one of the first latch circuit which holds the information indicating that the associated column is defective.
摘要翻译：根据一个实施例，半导体存储器件包括存储单元阵列和第一至第三锁存电路。第一个锁存电路保存关于相关联的列是否有故障的信息。在第二个锁存电路中设置一个指针。第三个锁存电路保持写数据或读数据。当相关联的第一锁存电路保持指示相关联的列没有缺陷的信息时，指针被设置为相关联的第二锁存电路时，第三锁存电路中的一个被激活。指针与时钟同步地顺序地在第二锁存电路之间移位。在移动指针时，指针跳过与第一锁存电路中的一个相关联的第二锁存电路之一，其中保持指示相关联的列有缺陷的信息。

8. 发明申请

US20110141817A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR CONTROLLING THE SAME 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US20110141817A1
公开(公告)日：2011-06-16
申请号：US12884658
申请日：2010-09-17
申请人： Teruo TAKAGIWA
发明人： Teruo TAKAGIWA
IPC分类号： G11C7/10 , G11C16/34
CPC分类号： G11C11/5628 , G11C16/3436
摘要： According to one embodiment, a semiconductor memory device includes a plurality of memory cells, and a plurality of latch circuits. The memory cells are associated with columns and are capable of storing data. The latch circuits are associated with the columns and are capable of storing write data and/or read data for the columns. The latch circuits are selectively activated, and activated latch circuits are capable of receiving and/or outputting data.
摘要翻译：根据一个实施例，半导体存储器件包括多个存储单元和多个锁存电路。存储单元与列相关联并且能够存储数据。锁存电路与列相关联，并且能够存储用于列的写入数据和/或读取数据。锁存电路被选择性地激活，并且激活的锁存电路能够接收和/或输出数据。

9. 发明申请

US20130235676A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20130235676A1
公开(公告)日：2013-09-12
申请号：US13604070
申请日：2012-09-05
申请人： Teruo TAKAGIWA
发明人： Teruo TAKAGIWA
IPC分类号： G11C7/06 , G11C7/10
CPC分类号： G11C7/06 , G11C7/1006 , G11C7/106
摘要： A semiconductor memory device according to an embodiment includes a memory cell array that includes a plurality of cell columns each configured by a plurality of memory cells, and a column control circuit that includes a plurality of sense amplifier-data latch units each including a plurality of sense amplifiers that detect and amplify data of the memory cells and a plurality of data latches. One of the plurality of sense amplifier-data latch units is a first sense amplifier-data latch unit and another of the plurality of sense amplifier-data latch units is a second sense amplifier-data latch unit, the first sense amplifier-data latch unit and the second sense amplifier-data latch unit having different numbers of the cell columns capable of being handled.
摘要翻译：根据实施例的半导体存储器件包括存储单元阵列，其包括由多个存储单元构成的多个单元列，列列控制电路包括多个读出放大器 - 数据锁存单元，每个读出放大器 - 数据锁存单元包括多个读出放大器，用于检测和放大存储器单元的数据和多个数据锁存器。多个读出放大器数据锁存单元之一是第一读出放大器数据锁存单元，并且多个读出放大器数据锁存单元中的另一个是第二读出放大器数据锁存单元，第一读出放大器数据锁存单元以及第二读出放大器 - 数据锁存单元，其具有能够处理的不同数量的单元列。

10. 发明申请

US20110235431A1 NONVOLATILE SEMICONDUCTOR MEMORY AND METHOD OF OPERATING THE SAME 有权
标题翻译：非易失性半导体存储器及其操作方法
公开(公告)号：US20110235431A1
公开(公告)日：2011-09-29
申请号：US13051388
申请日：2011-03-18
申请人： Teruo Takagiwa
发明人： Teruo Takagiwa
IPC分类号： G11C16/10
CPC分类号： G11C16/3436 , G11C11/5642
摘要： According to one embodiment, a nonvolatile semiconductor memory includes memory cells arranged in a memory cell array in the form of a matrix, the memory cell storing data having two or more levels associated with two or more threshold levels, respectively, a buffer circuit including latch circuits and sense amplifier circuits, each latch circuit and each sense amplifier being associated with each column in the memory cell array, and a control circuit configured to control operations of the memory cells and the buffer circuit, the control circuit executing data writing with respect to the memory cells and first verification using judgment information indicative of a result of the data writing in a write sequence with respect to data from the outside. The judgment information is assigned to two or more threshold levels, which are not adjacent to each other, in common.
摘要翻译：根据一个实施例，非易失性半导体存储器包括以矩阵形式布置在存储单元阵列中的存储单元，所述存储单元分别存储具有与两个或多个阈值电平相关联的两个或多个电平的数据，包括锁存器电路和读出放大器电路，每个锁存电路和每个读出放大器与存储单元阵列中的每一列相关联;以及控制电路，被配置为控制存储单元和缓冲电路的操作，控制电路执行相对于存储器单元和使用关于来自外部的数据的以写入序列表示数据写入的结果的判定信息的第一验证。判断信息被分配给彼此不相邻的两个或更多个阈值级别。

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