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1. 发明申请

WO2022234128A1 VORRICHTUNG UND VERFAHREN BASIEREND AUF MEMRISTIVEN DOMINO-VERARBEITUNGSEINHEIT-BASIERTEN COMPUTERPARADIGMEN 审中-公开
公开(公告)号：WO2022234128A1
公开(公告)日：2022-11-10
申请号：PCT/EP2022/062365
申请日：2022-05-06
申请人： FRAUNHOFER-GESELLSCHAFT ZUR FÖRDERUNG DER ANGEWANDTEN FORSCHUNG E.V. , FORSCHUNGSZENTRUM JÜLICH GMBH
发明人： DU, Nan , SCHMIDT, Heidemarie , MENZEL, Stephan
IPC分类号： G11C13/00 , G11C13/0002 , G11C13/004 , G11C13/0069
摘要： Eine Vorrichtung gemäß einer Ausführungsform wird bereitgestellt. Die Vorrichtung umfasst eine Steuereinheit (110) und Speichereinheit (120). Die Speichereinheit (120) umfasst einen Speicher, der eine Mehrzahl vom Memristoren umfasst. Die Steuereinheit (110) ist ausgebildet, eine Sequenz von Verarbeitungsschritten durchzuführen. Ein erster Verarbeitungsschritt der Sequenz der Verarbeitungsschritte, mit der die Sequenz der Verarbeitungsschritte beginnt, ist ein erster von zwei oder mehreren MIMO-Verarbeitungsschritte. Ein letzter Verarbeitungsschritt der Sequenz der Verarbeitungsschritte, mit der die Sequenz der Verarbeitungsschritte endet, ist ein weiterer der zwei oder mehreren MIMO-Verarbeitungsschritte. Die Sequenz der Verarbeitungsschritte weist des Weiteren einen oder mehrere MIVO-Verarbeitungsschritte auf. Des Weiteren weist die Sequenz der Verarbeitungsschritte einen oder mehrere VIMO-Verarbeitungsschritte auf. Bei jedem MIMO-Verarbeitungsschritt der zwei oder mehreren MIMO-Verarbeitungsschritte ist die Steuereinheit (110) ausgebildet, eine Eingabe des MIMO-Verarbeitungsschritts durch Auslesen des Speicherinhalts eines der Mehrzahl der Memristoren zu erhalten, und eine Ausgabe des MIMO-Verarbeitungsschritts in einem der Mehrzahl der Memristoren zu speichern. Des Weiteren ist bei jedem VIMO-Verarbeitungsschritt der ein oder mehreren VIMO-Verarbeitungsschritte die Steuereinheit (110) ausgebildet, eine Eingabe des VIMO-Verarbeitungsschritts durch Auswertung einer Eingangsspannung zu erhalten, und eine Ausgabe des VIMO-Verarbeitungsschritts in einem der Mehrzahl der Memristoren zu speichern. Ferner ist bei jedem MIVO-Verarbeitungsschritt der ein oder mehreren MIVO-Verarbeitungsschritte die Steuereinheit (110) ausgebildet ist, eine Eingabe des MIVO-Verarbeitungsschritts durch Auslesen des Speicherinhalts eines der Mehrzahl der Memristoren zu erhalten und eine Ausgabe des MIVO-Verarbeitungsschritts als eine Ausgangsspannung auszugeben.

2. 发明申请

WO2021259072A1 SUPPRESSING UNDESIRED PROGRAMMING AT HALF-SELECTED DEVICES IN A CROSSPOINT ARRAY OF 3-TERMINAL RESISTIVE MEMORY 审中-公开
公开(公告)号：WO2021259072A1
公开(公告)日：2021-12-30
申请号：PCT/CN2021/099403
申请日：2021-06-10
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM (CHINA) CO., LIMITED
发明人： KIM, Seyoung , ONEN, Oguzhan Murat , GOKMEN, Tayfun
IPC分类号： G06N3/063 , G06N3/08 , G06N3/0472 , G11C11/54 , G11C13/0026 , G11C13/0028 , G11C13/003 , G11C13/0033 , G11C13/004 , G11C13/0069 , G11C2213/53
摘要： Aspects of the invention include performing a stochastic update for a crossbar array by generating a set of stochastic pulses for a crossbar array, the crossbar array including a plurality of row wires and a plurality of column wires, the plurality of row wires including a first row wire and the plurality of column wires including a first column wire, wherein a three terminal device is coupled to the first row wire and the first column wire at a crosspoint of the first row wire and the first column wire, and wherein a resistivity of the three terminal device is modified responsive to a coincidence of pulses from the set of stochastic pulses at the crosspoint of the first row and the first column, and wherein at least one terminal in the three terminal device is floating.

3. 发明申请

WO2021126294A1 KERNEL TRANSFORMATION TECHNIQUES TO REDUCE POWER CONSUMPTION OF BINARY INPUT, BINARY WEIGHT IN-MEMORY CONVOLUTIONAL NEURAL NETWORK INFERENCE ENGINE 审中-公开
公开(公告)号：WO2021126294A1
公开(公告)日：2021-06-24
申请号：PCT/US2020/024625
申请日：2020-03-25
申请人： SANDISK TECHNOLOGIES LLC
发明人： HOANG, Tung Thanh , CHOI, Won Ho , LUEKER-BODEN, Martin
IPC分类号： G06N3/063 , G06N3/08 , G11C13/00 , G06F7/523 , G06N3/04 , G11C11/54 , G11C13/004 , G11C13/0069
摘要： Techniques are presented for performing in-memory matrix multiplication operations for binary input, binary weight valued convolution neural network (CNN) inferencing. The weights of a filter are stored in pairs of memory cells of a storage class memory device, such as a ReRAM or phase change memory based devices. To reduce current consumption, the binary valued filters are transformed into ternary valued filters by taking sums and differences of binary valued filter pairs. The zero valued weights of the transformed filters are stored as a pair of high resistance state memory cells, reducing current consumption during convolution. The results of the in-memory multiplications are pair-wise combined to compensate for the filter transformations. To compensate for zero valued weights, a zero weight register stores the number of zero weights along each bit line and is used to initialize counter values for accumulating the multiplication operations.

4. 发明申请

WO2023278073A1 SYSTEMS AND METHODS FOR ADAPTIVE SELF-REFERENCED READS OF MEMORY DEVICES 审中-公开
公开(公告)号：WO2023278073A1
公开(公告)日：2023-01-05
申请号：PCT/US2022/030532
申请日：2022-05-23
申请人： MICRON TECHNOLOGY, INC
发明人： MIRICHIGNI, Graziano , MUZZETTO, Riccardo , BEDESCHI, Ferdinando
IPC分类号： G11C13/00 , G06F3/06 , G11C11/1673 , G11C11/1693 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0061 , G11C2013/0045 , G11C2013/0057
摘要： Methods and systems include memory devices (100) with a memory array (112) comprising a plurality of memory cells (102). The memory devices (100) include a control circuit (122) operatively coupled to the memory array (112) and configured to receive a read request for data and to apply a first voltage at a first time duration to the memory array (112) based on the read request. The control circuit (122) is additionally configured to count a number of the plurality of memory cells (102) that have switched to an active read state based on the first voltage and to derive a second time duration. The control circuit (122) is further configured to apply a second voltage at the second duration to the memory array (112). The control circuit (122) is also configured to return the data based at least on bits stored in a first and a second set of the plurality of memory cells (102).

5. 发明申请

WO2021242881A2 LOW LOSS MULTISTATE PHOTONIC MEMORIES 审中-公开
公开(公告)号：WO2021242881A2
公开(公告)日：2021-12-02
申请号：PCT/US2021/034286
申请日：2021-05-26
申请人： THE GEORGE WASHINGTON UNIVERSITY
发明人： MISCUGLIO, Mario , SORGER, Volker J.
IPC分类号： G02F1/19 , G02F1/313 , G02F3/02 , G11C13/04 , G11C13/0004 , G11C13/004 , G11C13/0069
摘要： Multistate non-volatile photonic memory devices are disclosed. The photonic devices comprise phase change materials with broadband transparencies used to store discretized information with negligible losses in the 0 state. The photonic memories comprise multiple configurations for reading and writing multi-bit words. The reading mechanisms comprises schemes based on light-absorption (FIG. 1), shift in resonances of a cavity (ring resonator, photonic crystal; FIG. 2) or interferometric schemes (FIG. 3). The photonic memory devices employ multiple techniques for writing electrically (FIG. 4 and related performance) and/or all-optically (FIGS. 7-10). The optical writing can be performed with pulsed laser light coming either from free space or on-chip using dedicated writing lines and opportune drops.

6. 发明申请

WO2021191362A1 RESISTIVE RANDOM MEMORY ARCHITECTURE WITH HIGH INTEGRATION DENSITY AND CONTROL METHOD THEREOF 审中-公开
公开(公告)号：WO2021191362A1
公开(公告)日：2021-09-30
申请号：PCT/EP2021/057772
申请日：2021-03-25
申请人： CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE , UNIVERSITÉ D'AIX-MARSEILLE , AMERICAN UNIVERSITY OF BEIRUT
发明人： HAJRI, Basma , AZIZA, Hassan , MANSOUR, Mohammad , CHEHAB, Ali
IPC分类号： G11C13/00 , G11C13/003 , G11C13/004 , G11C13/0069
摘要： The invention relates to a memory circuit comprising a first memory word (MW) comprising: a plurality of variable resistors (VR), each variable resistor forming one memory cell and having a first electrode (BE) and a second electrode (TE) connected to a bit line control circuit (BLDV); and a first selection transistor (ST, ST1) comprising a first conduction terminal connected to the first electrode (BE) of each variable resistor of the first memory word, a second conduction terminal (SL) connected to a ground of the memory circuit and a control terminal connected to a word line control circuit (WLDV), wherein each bit line control circuit is configured to set the second electrode (TE) of one of the variable resistors either to a high positive voltage (STV) to set the corresponding memory cell, or to a high negative voltage (RSV) to reset the corresponding memory cell, or to a read voltage to detect whether the corresponding memory cell is set or reset.

7. 发明申请

WO2021194996A1 THREE DIMENSIONAL DOUBLE-DENSITY MEMORY ARRAY 审中-公开
公开(公告)号：WO2021194996A1
公开(公告)日：2021-09-30
申请号：PCT/US2021/023535
申请日：2021-03-22
申请人： HSU, Fu-Chang
发明人： HSU, Fu-Chang
IPC分类号： H01L27/11551 , H01L27/11553 , H01L27/11563 , H01L27/11578 , H01L27/1158 , G11C11/1673 , G11C11/1675 , G11C11/2273 , G11C11/2275 , G11C13/004 , G11C13/0069 , G11C16/10 , G11C16/26 , G11C17/18 , G11C2213/71 , G11C2213/75 , H01L27/11206 , H01L27/11582 , H01L27/11597 , H01L27/228 , H01L27/2454 , H01L27/249
摘要： A three dimensional double-density memory array is disclosed. In an embodiment, a three-dimensional (3D) double density array comprises a string of memory devices that are configured so that a first portion of the memory devices form a first channel and a second portion of the memory devices form a second channel. The array also comprises a plurality of word lines coupled to the string of memory devices. Each word line is coupled to a memory device that forms the first channel and a memory device that forms the second channel. The array also comprises at least one drain select gate that couples the first and second channels to a bit line.

8. 发明申请

WO2021135839A1 汉明距离计算方法、芯片和设备审中-公开
公开(公告)号：WO2021135839A1
公开(公告)日：2021-07-08
申请号：PCT/CN2020/134300
申请日：2020-12-07
申请人：华为技术有限公司
发明人：李祎 , 缪向水 , 程龙 , 李健聪 , 谭海波 , 石晓钟 , 黄克骥
IPC分类号： G11C13/00 , G06K9/62 , G06K9/6215 , G11C13/0004 , G11C13/004
摘要：一种计算字符串的汉明距离的方法、及汉明距离计算芯片和设备，所述芯片包括n个运算单元，每个运算单元中包括负极相连的两个忆阻器，其电阻都处于第一阻值，所述方法包括：获取第一字符串和第二字符串；对于任意一个字符对，将该字符对中的两个字符对应的预设电位分别输入该字符对对应的运算单元的两个忆阻器的正极，其中对不同字符预设的电位之差大于使忆阻器由第一阻值阻变的阈值电压的2倍；对所述n个运算单元中的各个忆阻器施加读取电压，所述读取电压使得不改变各个忆阻器的阻值、并在各个忆阻器中产生电流；基于所述n个运算单元中的各个忆阻器中的电流，确定第一字符串与第二字符串的汉明距离。该方法节约了功耗和延时。

9. 发明申请

WO2021126296A1 SOFT BIT READ MODE SELECTION FOR NON-VOLATILE MEMORY 审中-公开
公开(公告)号：WO2021126296A1
公开(公告)日：2021-06-24
申请号：PCT/US2020/026011
申请日：2020-03-31
申请人： WESTERN DIGITAL TECHNOLOGIES, INC.
发明人： SHARON, Eran , BAZARSKY, Alex , ALROD, Idan
IPC分类号： G11C16/26 , G11C16/30 , G11C7/06 , G11C16/04 , G06F11/1068 , G06F3/0604 , G06F3/0634 , G06F3/0659 , G06F3/0679 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C16/08 , G11C2013/0045
摘要： Apparatuses, systems, and methods are presented for reading data. A controller (206) may be configured to select a read mode from a plurality of read modes for reading data from a region of a non-volatile memory array (200). The plurality of read modes may include at least a time-based soft bit read mode. The controller (206) may be configured to apply a set of bias conditions to cells (306) of a region so that bit line currents associated with the cells (306) of the region affect voltages at capacitors (804) associated with the cells (306) of the region. The controller (206) may be configured to, in response to selecting a time-based soft bit read mode, read hard bits and soft bits for a region by sensing capacitor voltages resulting from an applied set of bias conditions, at multiple integration times.

10. 发明申请

WO2022010692A1 READING A MULTI-LEVEL MEMORY CELL 审中-公开
公开(公告)号：WO2022010692A1
公开(公告)日：2022-01-13
申请号：PCT/US2021/039539
申请日：2021-06-29
申请人： MICRON TECHNOLOGY, INC.
发明人： ROBUSTELLI, Mattia , PELLIZZER, Fabio , TORTORELLI, Innocenzo , PIROVANO, Agostino
IPC分类号： G11C11/56 , G11C13/00 , G11C11/5678 , G11C13/004 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C2013/0045 , G11C2013/0078 , G11C2013/0092 , G11C7/1051 , G11C7/1096
摘要： Methods, systems, and devices for reading a multi-level memory cell are described. The memory cell may be configured to store three or more logic states. The memory device may apply a first read voltage to a memory cell to determine a logic state stored by the memory cell. The memory device may determine whether a first snapback event occurred and apply a second read voltage based on determining that the first snapback event failed to occur based on applying the first read voltage. The memory device may determine whether a second snapback event occurred and determine the logic state based on whether the first snapback event or the second snapback event occurred.

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