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1. 发明申请

WO2023047149A1 IMPROVED ECC CONFIGURATION IN MEMORIES 审中-公开
公开(公告)号：WO2023047149A1
公开(公告)日：2023-03-30
申请号：PCT/IB2021/022216
申请日：2021-09-23
申请人： MICRON TECHNOLOGY, INC.
发明人： MIRICHIGNI, Graziano , LAURENT, Christophe, Vincent, Antoine , MUZZETTO, Riccardo
IPC分类号： G11C29/42 , G11C29/52 , G06F11/10
摘要： The present disclosure relates to a method for operating an array of memory cells, the method comprising storing user data in a plurality of memory cells of the array, storing parity data associated with the user data in a plurality of parity cells of the array, and, based on the stored parity data, selecting an Error Correction Code (ECC) correction capability and/or an ECC granularity according to which an ECC operation is to be performed, wherein the selection of the ECC correction capability and/or the ECC granularity is determined by the steps of updating a first register, said first register comprising values which indicate a required ECC correction capability and/or a required ECC granularity to be applied to the memory cells based on a current status of said memory cells, wherein the values of the first register are updated based on a variation of the current status of the memory cells, and wherein an update of the values of the first register corresponds to a variation of the required ECC correction capability and/or a required ECC granularity to be applied to said memory cells, and based on the updated values of the first register, executing an ECC switch command, wherein the ECC switch command is such as to vary a previously selected ECC correction capability and/or a previously selected ECC granularity, the method further comprising: updating a second register according to the varied ECC correction capability and/or ECC granularity, said second register comprising values indicating the selected ECC correction capability and the selected ECC granularity applied to the memory cells based on the current status thereof. Related apparatuses and systems are also herein disclosed.

2. 发明申请

WO2014066843A1 APPARATUSES AND METHODS FOR MEMORY OPERATIONS HAVING VARIABLE LATENCIES 审中-公开
标题翻译：具有可变延迟的存储器操作的装置和方法
公开(公告)号：WO2014066843A1
公开(公告)日：2014-05-01
申请号：PCT/US2013/066947
申请日：2013-10-25
申请人： MIRICHIGNI, Graziano , VILLA, Corrado , PORZIO, Luca , TAN, Chee Weng , LEMARIE, Sebastien , KLINDWORTH, Andre , MICRON TECHNOLOGY, INC.
发明人： MIRICHIGNI, Graziano , VILLA, Corrado , PORZIO, Luca , TAN, Chee Weng , LEMARIE, Sebastien , KLINDWORTH, Andre
IPC分类号： G06F13/14 , G06F13/38 , G06F12/00
CPC分类号： G06F9/30047 , G06F13/161 , G06F13/1689 , G11C7/1063 , G11C7/22 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C2207/2272
摘要： Apparatuses and methods for performing memory operations are described. An example apparatus includes a memory operation controller. The memory operation controller is configured to receive memory instructions and decode the same to provide internal signals for performing memory operations for the memory instructions. The memory operation controller is further configured to provide information indicative of a time for a variable latency period of a memory instruction during the variable latency period. In an example method, a write instruction and an address to which write data is to be written is received at a memory and an acknowledgement indicative of an end of a variable latency period for the write instruction is provided. After waiting a variable bus turnaround after the acknowledgement, write data for the write instruction is received.
摘要翻译：描述用于执行存储器操作的装置和方法。示例性装置包括存储器操作控制器。存储器操作控制器被配置为接收存储器指令并对其进行解码以提供用于对存储器指令执行存储器操作的内部信号。存储器操作控制器还被配置为在可变等待时间周期期间提供指示存储器指令的可变等待时间周期的时间的信息。在示例性方法中，在存储器处接收要写入数据的写指令和地址，并且提供指示用于写指令的可变等待时间周期结束的确认。在确认之后等待可变总线周转后，接收写入指令的写入数据。

3. 发明申请

WO2023076764A1 TECHNIQUES FOR INDICATING ROW ACTIVATION 审中-公开
公开(公告)号：WO2023076764A1
公开(公告)日：2023-05-04
申请号：PCT/US2022/076275
申请日：2022-09-12
申请人： MICRON TECHNOLOGY, INC.
发明人： MIRICHIGNI, Graziano , BOLANDRINA, Efrem
IPC分类号： G11C11/408 , G11C11/4076 , G11C8/12 , G06F3/06
摘要： Methods, systems, and devices for techniques for indicating row activation are described. A memory device may receive an indication associated with an activation command, which may enable the memory device to begin some aspects of an activation operation before receiving the associated activation command. The indication may include a location of a next row to access as part of the activation command. The indication may be included in a previous activation command or in a precharge command. The memory device may begin activation operations for the next row before the precharge operation of the current row is complete. The memory device may receive the activation command for the next row after receiving the indication, and may complete the activation operations upon receiving the activation command.

4. 发明申请

WO2022058768A1 MEMORY APPARATUS AND METHOD FOR OPERATING THE SAME 审中-公开
公开(公告)号：WO2022058768A1
公开(公告)日：2022-03-24
申请号：PCT/IB2020/020055
申请日：2020-09-21
申请人： MICRON TECHNOLOGY, INC
发明人： VILLA, Corrado , MIRICHIGNI, Graziano , BEDESCHI, Ferdinando
IPC分类号： G11C29/52 , G11C29/42 , G06F11/10 , G11C11/406
摘要： The present disclosure provides a memory apparatus and a method for operating the same. The method comprises performing a read operation on a set of memory cells, detecting an error in data read from the set of memory cells based on an error correction code (ECC) operation performed on the data, and performing a scrubbing operation or a refreshing operation on the set of memory cells according to a detecting result.

5. 发明申请

WO2021011132A1 PARALLEL ACCESS FOR MEMORY SUBARRAYS 审中-公开
公开(公告)号：WO2021011132A1
公开(公告)日：2021-01-21
申请号：PCT/US2020/037221
申请日：2020-06-11
申请人： MICRON TECHNOLOGY, INC.
发明人： MIRICHIGNI, Graziano , BOLANDRINA, Efrem
IPC分类号： G11C8/16 , G11C8/12 , G11C7/10 , G06F3/06
摘要： Techniques herein may allow a row of a subarray in a bank of a memory device to be activated before a precharge operation has been completed for a previously opened row of memory cells in the same bank. Each subarray within the bank may be associated with a respective local latching circuit, which may be used to maintain phases at the subarray independent of subsequent commands to the same bank. For example, the latching circuit may internalize timing signals triggered by a precharge command for a first row such that if an activation command is received for a different subarray in the same bank at a time before the precharge operation of the first row is complete, the precharge operation may continue until the first row is closed, as the timing signals triggered by the precharge command may be maintained locally at the subarray using the latching circuit.

6. 发明申请

WO2021040969A1 BANK CONFIGURABLE POWER MODES 审中-公开
公开(公告)号：WO2021040969A1
公开(公告)日：2021-03-04
申请号：PCT/US2020/044736
申请日：2020-08-03
申请人： MICRON TECHNOLOGY, INC.
发明人： MIRICHIGNI, Graziano , MARTINELLI, Andrea , LAURENT, Christophe, Vincent Antoine
IPC分类号： G11C5/14 , G11C8/12 , G11C7/10 , G06F3/06 , G11C11/22
摘要： Methods, systems, and devices for bank-configurable power modes are described. Aspects include operating a memory device that has multiple memory banks in a first mode. While operating in the first mode, the memory device may receive a command to enter a second mode having a lower power consumption level than the first mode. The memory device may enter the second mode by switching a first subset of the memory banks to a first low power mode that operates at a first power consumption level and a second subset of the memory banks to a second low power mode that operates at a second power consumption level that may be lower than the first power consumption level. In some cases, the memory device may switch the first subset of memory banks from the first low power mode while maintaining the second subset of memory banks in the low power mode.

7. 发明申请

WO2019204018A1 TRANSACTION METADATA 审中-公开
公开(公告)号：WO2019204018A1
公开(公告)日：2019-10-24
申请号：PCT/US2019/025169
申请日：2019-04-01
申请人： MICRON TECHNOLOGY, INC.
发明人： MIRICHIGNI, Graziano , SFORZIN, Marco , AMATO, Paolo , CARACCIO, Danilo
IPC分类号： G06F13/42 , G06F13/16 , G06F11/10
摘要： Apparatuses and methods related to providing transaction metadata. Providing transaction metadata includes providing an address of data stored in the memory device using an address bus coupled to the memory device and the controller. Providing transaction metadata also includes transferring the data, associated with the address, from the memory device using a data bus coupled to the memory device and the controller. Providing transaction metadata further includes transferring a sideband signal synchronously with the data bus and in conjunction with the address bus using a transaction metadata bus coupled to the memory device and the controller.

8. 发明申请

WO2018213103A1 PROVIDING ENERGY INFORMATION TO MEMORY 审中-公开
公开(公告)号：WO2018213103A1
公开(公告)日：2018-11-22
申请号：PCT/US2018/032181
申请日：2018-05-11
申请人： MICRON TECHNOLOGY, INC.
发明人： BLODGETT, Greg A. , BALLUCHI, Daniele , CARACCIO, Danilo , MIRICHIGNI, Graziano
IPC分类号： G06F1/32
摘要： The present disclosure includes apparatuses and methods for providing energy information to memory. An embodiment includes determining, by a host, that a charge level of an energy source coupled to the host has reached or exceeded a threshold value, and transmitting, from the host to a memory device coupled to the host, signaling indicative of an energy mode for the memory device, wherein the signaling is transmitted based at least in part on determining that the charge level of the energy source has reached or exceeded the threshold.

9. 发明申请

WO2015183573A1 PROVIDING POWER AVAILABILITY INFORMATION TO MEMORY 审中-公开
标题翻译：向存储器提供电源可用性信息
公开(公告)号：WO2015183573A1
公开(公告)日：2015-12-03
申请号：PCT/US2015/030786
申请日：2015-05-14
申请人： MICRON TECHNOLOGY, INC.
发明人： MIRICHIGNI, Graziano , VILLA, Corrado
IPC分类号： G11C5/14 , G11C16/30
CPC分类号： G11C5/144 , G06F13/1668 , G11C5/14 , G11C5/142 , G11C11/4072 , G11C11/4074 , G11C16/30
摘要： The present disclosure includes apparatuses and methods for providing power availability information to memory. A number of embodiments include a memory and a controller. The controller is configured to provide power and power availability information to the memory, and the memory is configured to determine whether to adjust its operation based, at least in part, on the power availability information.
摘要翻译：本公开包括用于向存储器提供功率可用性信息的装置和方法。许多实施例包括存储器和控制器。控制器被配置为向存储器提供功率和功率可用性信息，并且存储器被配置为至少部分地基于功率可用性信息来确定是否调整其操作。

10. 发明申请

WO2023278073A1 SYSTEMS AND METHODS FOR ADAPTIVE SELF-REFERENCED READS OF MEMORY DEVICES 审中-公开
公开(公告)号：WO2023278073A1
公开(公告)日：2023-01-05
申请号：PCT/US2022/030532
申请日：2022-05-23
申请人： MICRON TECHNOLOGY, INC
发明人： MIRICHIGNI, Graziano , MUZZETTO, Riccardo , BEDESCHI, Ferdinando
IPC分类号： G11C13/00 , G06F3/06 , G11C11/1673 , G11C11/1693 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0061 , G11C2013/0045 , G11C2013/0057
摘要： Methods and systems include memory devices (100) with a memory array (112) comprising a plurality of memory cells (102). The memory devices (100) include a control circuit (122) operatively coupled to the memory array (112) and configured to receive a read request for data and to apply a first voltage at a first time duration to the memory array (112) based on the read request. The control circuit (122) is additionally configured to count a number of the plurality of memory cells (102) that have switched to an active read state based on the first voltage and to derive a second time duration. The control circuit (122) is further configured to apply a second voltage at the second duration to the memory array (112). The control circuit (122) is also configured to return the data based at least on bits stored in a first and a second set of the plurality of memory cells (102).

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