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1. 发明授权

US06751767B1 Test pattern compression method, apparatus, system and storage medium 失效
标题翻译：测试图案压缩方法，设备，系统和存储介质
公开(公告)号：US06751767B1
公开(公告)日：2004-06-15
申请号：US09671368
申请日：2000-09-28
申请人： Tamaki Toumiya
发明人： Tamaki Toumiya
IPC分类号： G01B3128
CPC分类号： G06F11/261 , G06F11/263
摘要： A system and method for test pattern compression includes a local CPU for dividing faults into a plurality of fault groups, assigning the fault groups to respective remote CPUs, that are connected to the local CPU in parallel with each other. Each remote CPU generates test patterns having undefined values assigned to pins of the logic circuit that do not participate in fault detection. The local CPU acquires pluralities of test patterns of the remote CPUs, generates new test patterns obtained by merging those test patterns that have identical pattern numbers among the pluralities of test patterns, and attempts to merge these newly generated test patterns.
摘要翻译：用于测试模式压缩的系统和方法包括用于将故障分为多个故障组的本地CPU，将故障组分配给彼此并行连接到本地CPU的各个远程CPU。每个远程CPU产生具有分配给不参与故障检测的逻辑电路引脚的未定义值的测试模式。本地CPU获取多个远程CPU的测试模式，生成通过在多个测试模式中合并具有相同模式编号的测试模式获得的新测试模式，并尝试合并这些新生成的测试模式。

2. 发明授权

US06425104B1 Method and system for test pattern generation and a computer readable medium instructing the system to perform the method 失效
标题翻译：用于测试模式生成的方法和系统以及指示系统执行该方法的计算机可读介质
公开(公告)号：US06425104B1
公开(公告)日：2002-07-23
申请号：US09472938
申请日：1999-12-28
申请人： Tamaki Toumiya
发明人： Tamaki Toumiya
IPC分类号： G01R3128
CPC分类号： G01R31/318342
摘要： The present invention discloses a method and a system for test pattern generation which is capable of reducing the processing time for test pattern generation. A target circuit for test pattern generation is divided into a plurality of subcircuits. Pattern generation order of each subcircuits is determined for reducing the total test pattern generation time.
摘要翻译：本发明公开了一种能够减少测试图形生成的处理时间的测试图形生成的方法和系统。用于测试图形生成的目标电路被分成多个子电路。确定每个子电路的图案生成顺序以减少总测试图形生成时间。

3. 发明授权

US06334199B1 Method of generating test patterns for a logic circuit, a system performing the method, and a computer readable medium instructing the system to perform the method 失效
标题翻译：生成逻辑电路的测试模式的方法，执行该方法的系统以及指示系统执行该方法的计算机可读介质
公开(公告)号：US06334199B1
公开(公告)日：2001-12-25
申请号：US09236903
申请日：1999-01-26
申请人： Toshinobu Ono , Tamaki Toumiya
发明人： Toshinobu Ono , Tamaki Toumiya
IPC分类号： G01R3128
CPC分类号： G01R31/318321
摘要： In a method of test pattern generation for logic circuits, a whole circuit is divided into a plurality of partial circuits for test pattern generation by distributed-processing. ATG (Algorithmic Test Generation) process is performed per each of the partial circuits based on the result of RTG (Random Test Generation) process. Also disclosed are a test pattern generation system performing the method, and computer readable media having program for the test pattern generation system to perform the method.
摘要翻译：在逻辑电路的测试图形生成方法中，通过分布式处理将整个电路划分成用于测试图形生成的多个部分电路。基于RTG（随机测试生成）处理的结果，每个部分电路执行ATG（算法测试生成）处理。还公开了执行该方法的测试模式生成系统，以及具有用于测试模式生成系统执行该方法的程序的计算机可读介质。

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