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1. 发明授权

US06405150B1 Program storage device containing instructions that are spaced apart by unused bits that end on word boundaries and which generate chip testing bit streams of any length 失效
标题翻译：程序存储设备包含由在字边界结束的未使用位间隔开并且生成任何长度的芯片测试位流的指令
公开(公告)号：US06405150B1
公开(公告)日：2002-06-11
申请号：US09387197
申请日：1999-08-31
申请人： James Vernon Rhodes , Robert David Conklin , Timothy Allen Barr
发明人： James Vernon Rhodes , Robert David Conklin , Timothy Allen Barr
IPC分类号： G11C700
CPC分类号： G11C29/56 , G01R31/31919
摘要： A system for testing integrated circuit chips is comprised of a pattern generator that is coupled to a memory which stores variable length instructions that specify sets of bit streams for testing the chips. Each variable length instruction includes a code which indicates the number of bit streams in the set. Each bit stream in the set consists of a selectable number of bits which start on a word boundary and vary in increments of one bit. If the code indicates that the number of bit streams in a set is only one, then that one bit stream is stored in consecutive words of the memory. If the code indicates the number bit streams in a set is more than one, then those multiple bit streams are stored in an interleaved fashion in consecutive words in the memory. A respective series of unused bits starts immediately after each bit stream and ends on a word boundary. Each series of unused bits causes the next bit stream to start on a word boundary; and, that simplifies the circuitry which the pattern generator uses to address the bit streams.
摘要翻译：用于测试集成电路芯片的系统包括模式发生器，该模式发生器耦合到存储器，该存储器存储指定用于测试芯片的位流集合的可变长度指令。每个可变长度指令包括指示集合中的比特流的数量的代码。集合中的每个比特流由可选择的位数开始于字边界并以一位的增量变化。如果代码指示集合中的比特流的数量只有一个，则该一个比特流被存储在存储器的连续字中。如果代码指示一组中的数字比特流多于一个，那么这些多个比特流以交织方式存储在存储器中的连续字中。各个未使用的系列在每个比特流之后立即开始，并在一个字边界结束。每一系列未使用的位使下一位流在字边界上开始; 并且，这简化了模式发生器用于寻址比特流的电路。

2. 发明授权

US06363510B1 Electronic system for testing chips having a selectable number of pattern generators that concurrently broadcast different bit streams to selectable sets of chip driver circuits 失效
标题翻译：用于测试具有可选数量的图案发生器的芯片的电子系统，其同时将不同的比特流广播到可选择的芯片驱动器电路组
公开(公告)号：US06363510B1
公开(公告)日：2002-03-26
申请号：US09386946
申请日：1999-08-31
申请人： James Vernon Rhodes , Robert David Conklin , Timothy Allen Barr
发明人： James Vernon Rhodes , Robert David Conklin , Timothy Allen Barr
IPC分类号： G01R3128
CPC分类号： G01R31/31917 , G01R31/31907
摘要： A system for testing integrated circuit chips is comprised of a selectable number of pattern generators, each of which is coupled via a separate bus to a selectable number of chip driver circuits. Each pattern generator also is coupled to a respective memory, which stores different bit streams that are readable one word at a time. In operation, each pattern generator selectively reads the bit streams, word by word, from its respective memory; and its sends the words that are read to all of the chip driver circuits which are coupled to its separate bus, simultaneously. While that is occurring, each chip driver converts the words which it is sent into bit serial test signals which test multiple integrated circuit chips in parallel. Since all of the pattern generators operate in parallel, and since each pattern generator sends bit streams to all of the chip driver circuits that are coupled to its bus simultaneously, a high speed of operation is attained.
摘要翻译：用于测试集成电路芯片的系统包括可选数量的图案发生器，每个图形发生器通过单独的总线耦合到可选数量的芯片驱动器电路。每个图案发生器还耦合到相应的存储器，其存储一次读取一个字的不同位流。在操作中，每个模式发生器从其各自的存储器逐个地选择性地读取位流; 并且它将同时读取的字发送到耦合到其单独总线的所有芯片驱动器电路。在这种情况下，每个芯片驱动器将其发送的字转换成并行测试多个集成电路芯片的位串行测试信号。由于所有模式发生器并行运行，并且由于每个模式发生器都向同时耦合到其总线的所有芯片驱动器电路发送位流，因此可以实现高速运行。

3. 发明授权

US06363504B1 Electronic system for testing a set of multiple chips concurrently or sequentially in selectable subsets under program control to limit chip power dissipation 失效
标题翻译：用于在程序控制下在可选子集中同时或顺序测试一组多个芯片以限制芯片功率消耗的电子系统
公开(公告)号：US06363504B1
公开(公告)日：2002-03-26
申请号：US09386945
申请日：1999-08-31
申请人： James Vernon Rhodes , Robert David Conklin , Timothy Allen Barr
发明人： James Vernon Rhodes , Robert David Conklin , Timothy Allen Barr
IPC分类号： G01B3128
CPC分类号： G01R31/31926
摘要： A system for testing integrated circuit chips includes a signal generator which generates a clock signal; and a sequential control circuit having a first input which receives the clock signal, a second input for receiving commands, and multiple outputs. A command source sends programmable sequences of the commands to the second input of the control circuit; and in response, the control circuit passes the clock signal from the first input to only certain outputs which the commands select. All of the outputs of the control circuit are coupled through respective clock transmitters to different chips which are to be tested; and so in response to the programmable commands, the clock signal is sent sequentially to the chips that are to be tested, in selectable subsets. By such sequencing, the total power dissipation of the chips that are tested can be regulated when the chips are of a type that dissipate a large amount of power when they receive the clock signal, but dissipate substantially less power when they do not receive the clock signal.
摘要翻译：用于测试集成电路芯片的系统包括产生时钟信号的信号发生器; 以及顺序控制电路，具有接收时钟信号的第一输入端，用于接收命令的第二输入端和多个输出端。命令源将命令的可编程序列发送到控制电路的第二输入; 并且作为响应，控制电路将来自第一输入的时钟信号传递到命令选择的某些输出。控制电路的所有输出通过相应的时钟发射器耦合到不同的待测试芯片; 并且因此响应于可编程命令，时钟信号以可选择的子集顺序发送到要测试的芯片。通过这样的排序，当芯片接收时钟信号时耗散大量功率的芯片可以调节被测试的芯片的总功耗，但是当它们没有接收到时钟时消耗大量的功率信号。

4. 发明授权

US06571365B1 Initial stage of a multi-stage algorithmic pattern generator for testing IC chips 失效
标题翻译：用于测试IC芯片的多级算法模式发生器的初始阶段
公开(公告)号：US06571365B1
公开(公告)日：2003-05-27
申请号：US09432969
申请日：1999-11-03
申请人： James Vernon Rhodes , Robert David Conklin
发明人： James Vernon Rhodes , Robert David Conklin
IPC分类号： G01R3128
CPC分类号： G01R31/31813
摘要： An initial stage of a multi-stage algorithmic pattern generator which generates bit streams for testing IC chips, is comprised of multiple sets of input registers which store respective addresses; and an address modifying circuit that is coupled to the input registers, which receives commands, and in response, selects one register in one set and generates a modified address by performing arithmetic operations on the address in the selected register. Also, the initial stage includes a boundary check circuit that is coupled to the address modifying circuit, which stores a respective minimum limit and a respective maximum limit for each register set. This initial stage is particularly useful in generating sequences of addresses for memory cells in a chip that is to be tested, where the cells are arranged in rows and columns. When a particular Min/Max limit for a row/column is reached, then that event is remembered by the boundary check circuit. Thereafter, when the next row/column address is generated, the boundary check circuit automatically replaces the generated address (which will exceed the limit) with the proper address. This operation of detecting a limit address in one cycle, and replacing the next generated address in a subsequent cycle, enables the cycle time of the initial stage to be shorter than it otherwise could be if detection outside the limit and replacement with the proper address, occur in a single cycle.
摘要翻译：产生用于测试IC芯片的位流的多级算法模式产生器的初始阶段包括存储各个地址的多组输入寄存器; 以及地址修改电路，其耦合到接收命令的输入寄存器，并且作为响应，选择一个寄存器中的一个寄存器，并通过对所选择的寄存器中的地址进行算术运算来产生修改的地址。此外，初始阶段包括耦合到地址修改电路的边界检查电路，其存储每个寄存器组的相应的最小限制和相应的最大限制。该初始阶段在生成要测试的芯片中的存储器单元的地址序列特别有用，其中单元以行和列排列。当达到行/列的特定最小/最大限制时，该事件被边界检查电路记住。此后，当产生下一行/列地址时，边界检查电路自动地用适当的地址替换生成的地址（其将超过限制）。这种在一个周期内检测限制地址并且在随后的周期中替换下一个生成的地址的操作使得初始阶段的周期时间比其它情况下的周期时间要短，如果检测超出极限并用适当的地址替换，发生在单个周期。

5. 发明授权

US06415409B1 System for testing IC chips selectively with stored or internally generated bit streams 失效
标题翻译：用于利用存储或内部生成的比特流选择性地测试IC芯片的系统
公开(公告)号：US06415409B1
公开(公告)日：2002-07-02
申请号：US09432966
申请日：1999-11-03
申请人： James Vernon Rhodes , Robert David Conklin , Timothy Allen Barr
发明人： James Vernon Rhodes , Robert David Conklin , Timothy Allen Barr
IPC分类号： G06F1100
CPC分类号： G01R31/31921 , G01R31/31813
摘要： A system for testing IC chips selectively with stored or internally generated bit streams is comprised of a memory which stores instructions of a first class that expressly recite a first bit stream, and stores instructions of a second class that specify operations which generate a second bit stream. A first pattern generator is coupled to the memory, which sequentially reads the instructions of the first and second classes. The first pattern generator includes a time-shared control circuit which sends the first bit stream to a test port on the chips that are tested in response to the first class instructions that are read. In addition, a second pattern generator is coupled to the first pattern generator. This second pattern generator receives the second class instructions that are read; and in response, it sequentially generates portions of the second bit stream by performing the operations which the second class instructions specify. One portion of the second bit stream is sent to the test port on the chips that are tested, while the second pattern generator generates another portion of the second bit stream.
摘要翻译：用存储或内部产生的比特流选择性地测试IC芯片的系统包括一个存储器，该存储器存储明确背诵第一位流的第一类的指令，并且存储指定生成第二位流的操作的第二类的指令。第一模式发生器耦合到存储器，其顺序地读取第一和第二类的指令。第一模式发生器包括时间共享控制电路，其将第一位流发送到响应于读取的第一类指令而被测试的芯片上的测试端口。此外，第二图案发生器耦合到第一图案发生器。该第二模式生成器接收被读取的第二类指令; 并且作为响应，通过执行第二类指令指定的操作来顺序地生成第二比特流的部分。第二比特流的一部分被发送到被测试的芯片上的测试端口，而第二模式发生器产生第二比特流的另一部分。

6. 发明授权

US06480981B1 Output stage of a multi-stage algorithmic pattern generator for testing IC chips 失效
标题翻译：用于测试IC芯片的多级算法模式发生器的输出级
公开(公告)号：US06480981B1
公开(公告)日：2002-11-12
申请号：US09432967
申请日：1999-11-03
申请人： James Vernon Rhodes , Robert David Conklin
发明人： James Vernon Rhodes , Robert David Conklin
IPC分类号： G06F1100
CPC分类号： G01R31/31813
摘要： An output stage of a multi-stage algorithmic pattern generator which generates bit streams for testing IC chips, is comprised of multiple input registers which hold input addresses and input data words; and a multiplexer circuit, having a plurality of parallel data inputs which concurrently receive the input addresses and the input data words, having control inputs for receiving a sequence of control signals, and which generates serial bit streams by selectively passing bits from the input addresses and input data words in response to the control signals. These serial bit streams from the multiplexer circuit preferably include a first bit stream which defines a data input to an integrated circuit chip that is to be tested, and a second bit stream which defines an expected output from the chip corresponding to the first bit stream. In one particular embodiment, the output stage further includes a memory address generator which generates a sequence of memory addresses, and a memory which receives the sequence of memory addresses, and in response, sends the sequence of control signals from a memory output to the control inputs of the multiplexer circuit. With this embodiment, the memory address generator can include a page register and a counter which together generate the sequence of memory addresses as multiple sub-sequences within respective pages; and the sub-sequences can be generated continuously with no gaps between them so that the serial bit streams from the multiplexer circuit will be generated continuously with no gaps between the serial bits.
摘要翻译：产生用于测试IC芯片的位流的多级算法模式发生器的输出级由保存输入地址和输入数据字的多个输入寄存器组成; 以及多路复用器电路，具有同时接收输入地址和输入数据字的多个并行数据输入，具有用于接收一系列控制信号的控制输入，并且通过选择性地传送来自输入地址的位和产生串行位流，响应于控制信号输入数据字。来自多路复用器电路的这些串行比特流优选地包括定义输入到要测试的集成电路芯片的数据的第一比特流和定义来自对应于第一比特流的芯片的预期输出的第二比特流。在一个具体实施例中，输出级还包括产生存储器地址序列的存储器地址产生器和接收存储器地址序列的存储器，并且作为响应，将控制信号序列从存储器输出发送到控制器多路复用器电路的输入。利用该实施例，存储器地址生成器可以包括页寄存器和计数器，它们一起生成存储器地址序列作为各页内的多个子序列; 并且子序列可以在它们之间不间断地连续生成，使得来自多路复用器电路的串行比特流将在串行比特之间不间断地连续生成。

7. 发明授权

US06415408B1 Multi-stage algorithmic pattern generator for testing IC chips 失效
标题翻译：用于测试IC芯片的多级算法模式发生器
公开(公告)号：US06415408B1
公开(公告)日：2002-07-02
申请号：US09432965
申请日：1999-11-03
申请人： James Vernon Rhodes , Robert David Conklin
发明人： James Vernon Rhodes , Robert David Conklin
IPC分类号： G06F1100
CPC分类号： G01R31/31926 , G01R31/31813
摘要： A multi-stage algorithmic pattern generator, which generates bit streams for testing IC chips, is comprised of an initial stage, an intermediate stage, and an output stage which are coupled together as a three stage pipeline. The initial stage sequentially generates multiple sets of virtual addresses for a virtual memory in response to a series of instructions from an external source. The intermediate stage sequentially stores each set of virtual addresses from the initial stage and translates the stored set of virtual addresses into a set of physical addresses for an actual memory that is to be tested. The output stage sequentially stores each set of physical addresses from the intermediate stage and generates output signals for testing the memory chips, by selecting bits from the stored set of physical addresses.
摘要翻译：产生用于测试IC芯片的比特流的多级算法模式生成器包括作为三级流水线耦合在一起的初级，中级和输出级。响应于来自外部源的一系列指令，初始阶段顺序地为虚拟存储器产生多组虚拟地址。中间级从初始阶段顺序地存储每组虚拟地址，并将存储的虚拟地址集合转换成用于要测试的实际存储器的一组物理地址。输出级从中间级顺序地存储每组物理地址，并通过从存储的物理地址集中选择位来产生用于测试存储器芯片的输出信号。

8. 发明授权

US06477676B1 Intermediate stage of a multi-stage algorithmic pattern generator for testing IC chips 失效
标题翻译：用于测试IC芯片的多级算法模式发生器的中间级
公开(公告)号：US06477676B1
公开(公告)日：2002-11-05
申请号：US09432968
申请日：1999-11-03
申请人： James Vernon Rhodes , Robert David Conklin
发明人： James Vernon Rhodes , Robert David Conklin
IPC分类号： G01R3128
CPC分类号： G01R31/318307 , G11C29/10 , G11C29/56
摘要： An intermediate stage of a multi-stage algorithmic pattern generator which generates bit streams for testing IC chips, is comprised of a plurality of input address registers which hold respective input addresses; and a memory address generator, coupled to the input address registers, which generates a series of memory addresses by selecting bits from the input addresses. A memory is coupled to the memory address generator, which sequentially receives each memory address in the series; and in response, this memory sends a corresponding series of translated addresses to a memory output. Multiple output registers are coupled to the memory output, and each output register stores a respective translated address in the series. With this intermediate stage, the input addresses can be virtual addresses in a virtual, or hypothetical, memory; and, those virtual addresses can be translated into physical addresses for an actual memory chip that is to be tested.
摘要翻译：产生用于测试IC芯片的比特流的多级算法模式发生器的中间级由多个输入地址寄存器组成，这些输入地址寄存器保存各自的输入地址; 以及存储器地址发生器，其耦合到输入地址寄存器，其通过从输入地址中选择位来产生一系列存储器地址。存储器耦合到存储器地址发生器，其顺序地接收串联中的每个存储器地址; 并且作为响应，该存储器将相应的一系列翻译的地址发送到存储器输出。多个输出寄存器耦合到存储器输出，并且每个输出寄存器存储该系列中相应的翻译地址。在这个中间阶段，输入地址可以是虚拟或假想的存储器中的虚拟地址; 并且，这些虚拟地址可被转换为要被测试的实际存储器芯片的物理地址。

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