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1. 发明授权

US06363504B1 Electronic system for testing a set of multiple chips concurrently or sequentially in selectable subsets under program control to limit chip power dissipation 失效
标题翻译：用于在程序控制下在可选子集中同时或顺序测试一组多个芯片以限制芯片功率消耗的电子系统
公开(公告)号：US06363504B1
公开(公告)日：2002-03-26
申请号：US09386945
申请日：1999-08-31
申请人： James Vernon Rhodes , Robert David Conklin , Timothy Allen Barr
发明人： James Vernon Rhodes , Robert David Conklin , Timothy Allen Barr
IPC分类号： G01B3128
CPC分类号： G01R31/31926
摘要： A system for testing integrated circuit chips includes a signal generator which generates a clock signal; and a sequential control circuit having a first input which receives the clock signal, a second input for receiving commands, and multiple outputs. A command source sends programmable sequences of the commands to the second input of the control circuit; and in response, the control circuit passes the clock signal from the first input to only certain outputs which the commands select. All of the outputs of the control circuit are coupled through respective clock transmitters to different chips which are to be tested; and so in response to the programmable commands, the clock signal is sent sequentially to the chips that are to be tested, in selectable subsets. By such sequencing, the total power dissipation of the chips that are tested can be regulated when the chips are of a type that dissipate a large amount of power when they receive the clock signal, but dissipate substantially less power when they do not receive the clock signal.
摘要翻译：用于测试集成电路芯片的系统包括产生时钟信号的信号发生器; 以及顺序控制电路，具有接收时钟信号的第一输入端，用于接收命令的第二输入端和多个输出端。命令源将命令的可编程序列发送到控制电路的第二输入; 并且作为响应，控制电路将来自第一输入的时钟信号传递到命令选择的某些输出。控制电路的所有输出通过相应的时钟发射器耦合到不同的待测试芯片; 并且因此响应于可编程命令，时钟信号以可选择的子集顺序发送到要测试的芯片。通过这样的排序，当芯片接收时钟信号时耗散大量功率的芯片可以调节被测试的芯片的总功耗，但是当它们没有接收到时钟时消耗大量的功率信号。

2. 发明授权

US06405150B1 Program storage device containing instructions that are spaced apart by unused bits that end on word boundaries and which generate chip testing bit streams of any length 失效
标题翻译：程序存储设备包含由在字边界结束的未使用位间隔开并且生成任何长度的芯片测试位流的指令
公开(公告)号：US06405150B1
公开(公告)日：2002-06-11
申请号：US09387197
申请日：1999-08-31
申请人： James Vernon Rhodes , Robert David Conklin , Timothy Allen Barr
发明人： James Vernon Rhodes , Robert David Conklin , Timothy Allen Barr
IPC分类号： G11C700
CPC分类号： G11C29/56 , G01R31/31919
摘要： A system for testing integrated circuit chips is comprised of a pattern generator that is coupled to a memory which stores variable length instructions that specify sets of bit streams for testing the chips. Each variable length instruction includes a code which indicates the number of bit streams in the set. Each bit stream in the set consists of a selectable number of bits which start on a word boundary and vary in increments of one bit. If the code indicates that the number of bit streams in a set is only one, then that one bit stream is stored in consecutive words of the memory. If the code indicates the number bit streams in a set is more than one, then those multiple bit streams are stored in an interleaved fashion in consecutive words in the memory. A respective series of unused bits starts immediately after each bit stream and ends on a word boundary. Each series of unused bits causes the next bit stream to start on a word boundary; and, that simplifies the circuitry which the pattern generator uses to address the bit streams.
摘要翻译：用于测试集成电路芯片的系统包括模式发生器，该模式发生器耦合到存储器，该存储器存储指定用于测试芯片的位流集合的可变长度指令。每个可变长度指令包括指示集合中的比特流的数量的代码。集合中的每个比特流由可选择的位数开始于字边界并以一位的增量变化。如果代码指示集合中的比特流的数量只有一个，则该一个比特流被存储在存储器的连续字中。如果代码指示一组中的数字比特流多于一个，那么这些多个比特流以交织方式存储在存储器中的连续字中。各个未使用的系列在每个比特流之后立即开始，并在一个字边界结束。每一系列未使用的位使下一位流在字边界上开始; 并且，这简化了模式发生器用于寻址比特流的电路。

3. 发明授权

US06363510B1 Electronic system for testing chips having a selectable number of pattern generators that concurrently broadcast different bit streams to selectable sets of chip driver circuits 失效
标题翻译：用于测试具有可选数量的图案发生器的芯片的电子系统，其同时将不同的比特流广播到可选择的芯片驱动器电路组
公开(公告)号：US06363510B1
公开(公告)日：2002-03-26
申请号：US09386946
申请日：1999-08-31
申请人： James Vernon Rhodes , Robert David Conklin , Timothy Allen Barr
发明人： James Vernon Rhodes , Robert David Conklin , Timothy Allen Barr
IPC分类号： G01R3128
CPC分类号： G01R31/31917 , G01R31/31907
摘要： A system for testing integrated circuit chips is comprised of a selectable number of pattern generators, each of which is coupled via a separate bus to a selectable number of chip driver circuits. Each pattern generator also is coupled to a respective memory, which stores different bit streams that are readable one word at a time. In operation, each pattern generator selectively reads the bit streams, word by word, from its respective memory; and its sends the words that are read to all of the chip driver circuits which are coupled to its separate bus, simultaneously. While that is occurring, each chip driver converts the words which it is sent into bit serial test signals which test multiple integrated circuit chips in parallel. Since all of the pattern generators operate in parallel, and since each pattern generator sends bit streams to all of the chip driver circuits that are coupled to its bus simultaneously, a high speed of operation is attained.
摘要翻译：用于测试集成电路芯片的系统包括可选数量的图案发生器，每个图形发生器通过单独的总线耦合到可选数量的芯片驱动器电路。每个图案发生器还耦合到相应的存储器，其存储一次读取一个字的不同位流。在操作中，每个模式发生器从其各自的存储器逐个地选择性地读取位流; 并且它将同时读取的字发送到耦合到其单独总线的所有芯片驱动器电路。在这种情况下，每个芯片驱动器将其发送的字转换成并行测试多个集成电路芯片的位串行测试信号。由于所有模式发生器并行运行，并且由于每个模式发生器都向同时耦合到其总线的所有芯片驱动器电路发送位流，因此可以实现高速运行。

4. 发明授权

US06415409B1 System for testing IC chips selectively with stored or internally generated bit streams 失效
标题翻译：用于利用存储或内部生成的比特流选择性地测试IC芯片的系统
公开(公告)号：US06415409B1
公开(公告)日：2002-07-02
申请号：US09432966
申请日：1999-11-03
申请人： James Vernon Rhodes , Robert David Conklin , Timothy Allen Barr
发明人： James Vernon Rhodes , Robert David Conklin , Timothy Allen Barr
IPC分类号： G06F1100
CPC分类号： G01R31/31921 , G01R31/31813
摘要： A system for testing IC chips selectively with stored or internally generated bit streams is comprised of a memory which stores instructions of a first class that expressly recite a first bit stream, and stores instructions of a second class that specify operations which generate a second bit stream. A first pattern generator is coupled to the memory, which sequentially reads the instructions of the first and second classes. The first pattern generator includes a time-shared control circuit which sends the first bit stream to a test port on the chips that are tested in response to the first class instructions that are read. In addition, a second pattern generator is coupled to the first pattern generator. This second pattern generator receives the second class instructions that are read; and in response, it sequentially generates portions of the second bit stream by performing the operations which the second class instructions specify. One portion of the second bit stream is sent to the test port on the chips that are tested, while the second pattern generator generates another portion of the second bit stream.
摘要翻译：用存储或内部产生的比特流选择性地测试IC芯片的系统包括一个存储器，该存储器存储明确背诵第一位流的第一类的指令，并且存储指定生成第二位流的操作的第二类的指令。第一模式发生器耦合到存储器，其顺序地读取第一和第二类的指令。第一模式发生器包括时间共享控制电路，其将第一位流发送到响应于读取的第一类指令而被测试的芯片上的测试端口。此外，第二图案发生器耦合到第一图案发生器。该第二模式生成器接收被读取的第二类指令; 并且作为响应，通过执行第二类指令指定的操作来顺序地生成第二比特流的部分。第二比特流的一部分被发送到被测试的芯片上的测试端口，而第二模式发生器产生第二比特流的另一部分。

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