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1. 发明授权

CN101669282B 运算放大器、管线型AD转换器失效
公开(公告)号：CN101669282B
公开(公告)日：2012-07-25
申请号：CN200880012777.2
申请日：2008-07-30
申请人：松下电器产业株式会社
发明人：野间崎大辅 , 冈浩二
IPC分类号： H01L27/04 , H01L21/82 , H01L21/822 , H03F3/45 , H03M1/14
CPC分类号： H03F3/45183 , H01L27/0629 , H01L27/0811 , H01L27/088 , H03F2203/45352 , H03F2203/45371 , H03F2203/45486 , H03M1/0682 , H03M1/0695 , H03M1/442
摘要：本发明提供一种运算放大器及管线型AD转换器。差动电压布线(W101a)将差动晶体管(T101a、T101a、…)之中使用的晶体管的栅极电极电连接在接受输入电压(Vinn)的输入节点上，差动电压布线(W101b)将差动晶体管(T101b、T101b、…)之中使用的晶体管的栅极电极电连接在接受输入电压(Vinp)的输入节点上。偏置电压布线(W102)将电流源晶体管(T102、T102、…)之中使用的晶体管的栅极电极电连接在接受偏置电压(WBN)的偏置节点上，偏置电压布线(W103)将负载晶体管(T103a、T103a、…、T103b、T103b…)之中使用的晶体管的栅极电极电连接在接受偏置电压(VBP)的偏置节点上。

2. 发明授权

CN105229946B 光调制器驱动器电路和光发射机有权
公开(公告)号：CN105229946B
公开(公告)日：2018-05-11
申请号：CN201480026304.3
申请日：2014-05-09
申请人：日本电信电话株式会社
发明人：长谷宗彦 , 野坂秀之 , 伊藤敏洋 , 村田浩一 , 福山裕之 , 才田隆志 , 龟井新 , 山崎裕史 , 菊池顺裕 , 小泉弘 , 野河正史 , 桂井宏明 , 鹈泽宽之 , 片冈智由 , 藤原直树 , 川上广人 , 堀越建吾 , 伊夫·布维尔 , 米山幹夫 , 相泽茂树 , 铃木昌弘
IPC分类号： H04B10/516 , H03F1/00 , H03F3/45 , H03F3/60 , H03G3/18
CPC分类号： H04B10/541 , H03F1/223 , H03F1/32 , H03F3/04 , H03F3/082 , H03F3/195 , H03F3/245 , H03F3/45085 , H03F3/45089 , H03F3/45183 , H03F3/45188 , H03F3/602 , H03F2200/18 , H03F2200/219 , H03F2200/255 , H03F2200/27 , H03F2200/336 , H03F2200/411 , H03F2200/72 , H03F2200/75 , H03F2203/45258 , H03F2203/45374 , H03F2203/45392 , H03F2203/45454 , H03F2203/45466 , H03F2203/45471 , H03F2203/45486 , H03F2203/45496 , H03F2203/45504 , H03F2203/45506 , H03F2203/45702 , H03G1/0023 , H03G1/0082 , H03G1/0088 , H03G3/00 , H03G3/001 , H03G3/3084 , H04B10/5561 , H04B10/588
摘要：光调制器驱动器电路(1)包括放大器(50、Q10、Q11、R10‑R13)和能够根据所希望的操作模式调整放大器(50)的电流量的电流量调整电路(51)。电流量调整电路(51)包括能够根据表示所希望的操作模式的二进制控制信号来单独地进行开关控制的至少两个电流源(IS10)。

3. 发明公开

CN105229946A 光调制器驱动器电路和光发射机有权
公开(公告)号：CN105229946A
公开(公告)日：2016-01-06
申请号：CN201480026304.3
申请日：2014-05-09
申请人：日本电信电话株式会社
发明人：长谷宗彦 , 野坂秀之 , 伊藤敏洋 , 村田浩一 , 福山裕之 , 才田隆志 , 龟井新 , 山崎裕史 , 菊池顺裕 , 小泉弘 , 野河正史 , 桂井宏明 , 鹈泽宽之 , 片冈智由 , 藤原直树 , 川上广人 , 堀越建吾 , 伊夫·布维尔 , 米山幹夫 , 相泽茂树 , 铃木昌弘
IPC分类号： H04B10/516 , H03F1/00 , H03F3/45 , H03F3/60 , H03G3/18
CPC分类号： H04B10/541 , H03F1/223 , H03F1/32 , H03F3/04 , H03F3/082 , H03F3/195 , H03F3/245 , H03F3/45085 , H03F3/45089 , H03F3/45183 , H03F3/45188 , H03F3/602 , H03F2200/18 , H03F2200/219 , H03F2200/255 , H03F2200/27 , H03F2200/336 , H03F2200/411 , H03F2200/72 , H03F2200/75 , H03F2203/45258 , H03F2203/45374 , H03F2203/45392 , H03F2203/45454 , H03F2203/45466 , H03F2203/45471 , H03F2203/45486 , H03F2203/45496 , H03F2203/45504 , H03F2203/45506 , H03F2203/45702 , H03G1/0023 , H03G1/0082 , H03G1/0088 , H03G3/00 , H03G3/001 , H03G3/3084 , H04B10/5561 , H04B10/588
摘要：光调制器驱动器电路(1)包括放大器(50、Q10、Q11、R10-R13)和能够根据所希望的操作模式调整放大器(50)的电流量的电流量调整电路(51)。电流量调整电路(51)包括能够根据表示所希望的操作模式的二进制控制信号来单独地进行开关控制的至少两个电流源(IS10)。

4. 发明公开

CN101669282A 运算放大器、管线型AD转换器失效
公开(公告)号：CN101669282A
公开(公告)日：2010-03-10
申请号：CN200880012777.2
申请日：2008-07-30
申请人：松下电器产业株式会社
发明人：野间崎大辅 , 冈浩二
IPC分类号： H03F3/45 , H01L27/04 , H01L21/82 , H03M1/14 , H01L21/822
CPC分类号： H03F3/45183 , H01L27/0629 , H01L27/0811 , H01L27/088 , H03F2203/45352 , H03F2203/45371 , H03F2203/45486 , H03M1/0682 , H03M1/0695 , H03M1/442
摘要：本发明提供一种运算放大器及管线型AD转换器。差动电压布线(W101a)将差动晶体管(T101a、T101a、…)之中使用的晶体管的栅极电极电连接在接受输入电压(Vinn)的输入节点上，差动电压布线(W101b)将差动晶体管(T101b、T101b、…)之中使用的晶体管的栅极电极电连接在接受输入电压(Vinp)的输入节点上。偏置电压布线(W102)将电流源晶体管(T102、T102、…)之中使用的晶体管的栅极电极电连接在接受偏置电压(WBN)的偏置节点上，偏置电压布线(W103)将负载晶体管(T103a、T103a、…、T103b、T103b…)之中使用的晶体管的栅极电极电连接在接受偏置电压(VBP)的偏置节点上。

5. 发明申请

US20090310267A1 METHOD, DESIGN STRUCTURES, AND SYSTEMS FOR CURRENT MODE LOGIC (CML) DIFFERENTIAL DRIVER ESD PROTECTION CIRCUITRY 失效
标题翻译：电流模式逻辑（CML）差分驱动器ESD保护电路的方法，设计结构和系统
公开(公告)号：US20090310267A1
公开(公告)日：2009-12-17
申请号：US12140485
申请日：2008-06-17
申请人： Robert J. Gauthier, JR. , Junjun Li , Ankit Srivastava
发明人： Robert J. Gauthier, JR. , Junjun Li , Ankit Srivastava
IPC分类号： H02H9/00
CPC分类号： H03F3/45188 , H01L27/0251 , H03F1/52 , H03F1/523 , H03F2203/45466 , H03F2203/45486 , H03F2203/45504
摘要： A hardware description language (HDL) design structure encoded on a machine readable data storage medium, the HDL design comprising elements that when processed in a computer aided design system generates a machine executable representation of a device for implementing dynamic refresh protocols for DRAM based cache. The HDL design structure further comprises an integrated circuit having a differential driver, comprising: a first driver and a second driver forming the differential driver, the drivers are coupled in parallel between a first voltage source and a second voltage source; a first switch coupled to the first driver and configured to turn off the first driver during an ESD event such that the first driver sustains stress during the ESD event; and a second switch coupled to the second driver and configured to turn off the second driver during the ESD event such that the second driver sustains stress during the ESD event.
摘要翻译：在机器可读数据存储介质上编码的硬件描述语言（HDL）设计结构，所述HDL设计包括在计算机辅助设计系统中处理时的元件，生成用于实现基于DRAM的高速缓存的动态刷新协议的设备的机器可执行表示。 HDL设计结构还包括具有差分驱动器的集成电路，包括：形成差分驱动器的第一驱动器和第二驱动器，驱动器并联耦合在第一电压源和第二电压源之间; 第一开关，其耦合到所述第一驱动器并且被配置为在ESD事件期间关闭所述第一驱动器，使得所述第一驱动器在所述ESD事件期间保持应力; 以及耦合到所述第二驱动器并被配置为在所述ESD事件期间关闭所述第二驱动器的第二开关，使得所述第二驱动器在所述ESD事件期间维持应力。

6. 发明公开

EP2996266A4 OPTICAL MODULATOR DRIVER CIRCUIT AND OPTICAL TRANSMITTER 审中-公开
标题翻译：欧洲优质调制解调器TREIBERSCHALTUNGFÜROPTISCHER SENDER
公开(公告)号：EP2996266A4
公开(公告)日：2017-03-15
申请号：EP14794331
申请日：2014-05-09
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： NAGATANI MUNEHIKO , NOSAKA HIDEYUKI , ITOH TOSHIHIRO , MURATA KOICHI , FUKUYAMA HIROYUKI , SAIDA TAKASHI , KAMEI SHIN , YAMAZAKI HIROSHI , KIKUCHI NOBUHIRO , KOIZUMI HIROSHI , NOGAWA MASAFUMI , KATSURAI HIROAKI , UZAWA HIROYUKI , KATAOKA TOMOYOSHI , FUJIWARA NAOKI , KAWAKAMI HIROTO , HORIKOSHI KENGO , BOUVIER YVES , YONEYAMA MIKIO , AISAWA SHIGEKI , SUZUKI MASAHIRO
IPC分类号： H04B10/516 , H03F1/00 , H03F1/22 , H03F1/32 , H03F3/08 , H03F3/195 , H03F3/24 , H03F3/45 , H03F3/60 , H03G1/00 , H03G3/00 , H03G3/18 , H03G3/30 , H04B10/54
CPC分类号： H04B10/541 , H03F1/223 , H03F1/32 , H03F3/04 , H03F3/082 , H03F3/195 , H03F3/245 , H03F3/45085 , H03F3/45089 , H03F3/45183 , H03F3/45188 , H03F3/602 , H03F2200/18 , H03F2200/219 , H03F2200/255 , H03F2200/27 , H03F2200/336 , H03F2200/411 , H03F2200/72 , H03F2200/75 , H03F2203/45258 , H03F2203/45374 , H03F2203/45392 , H03F2203/45454 , H03F2203/45466 , H03F2203/45471 , H03F2203/45486 , H03F2203/45496 , H03F2203/45504 , H03F2203/45506 , H03F2203/45702 , H03G1/0023 , H03G1/0082 , H03G1/0088 , H03G3/00 , H03G3/001 , H03G3/3084 , H04B10/5561 , H04B10/588
摘要： An optical modulator driver circuit (1) includes an amplifier (50, Q10, Q11, R10 - R13), and a current amount adjustment circuit (51) capable of adjusting a current amount of the amplifier (50) in accordance with a desired operation mode. The current amount adjustment circuit (51) includes at least two current sources (IS10) that are individually ON/OFF-controllable in accordance with a binary control signal representing the desired operation mode.
摘要翻译：光调制器驱动电路（1）包括放大器（50，Q10，Q11，R10-R13）和电流量调节电路（51），能够根据期望的操作调节放大器（50）的电流量模式。电流量调节电路（51）包括至少两个根据表示期望的操作模式的二进制控制信号单独地进行ON / OFF控制的电流源（IS10）。

7. 发明公开

EP1835624A2 Power management in a data acquisition system 审中-公开
标题翻译： Leistungsverwaltung在einem Datenerfassungssystem
公开(公告)号：EP1835624A2
公开(公告)日：2007-09-19
申请号：EP07004908.5
申请日：2007-03-09
申请人： Cirrus Logic, Inc.
发明人： Kejariwal, Murari , Coupe, John R.
IPC分类号： H03M1/12 , H03G1/00
CPC分类号： H03F3/45188 , H03F3/45475 , H03F2200/331 , H03F2203/45032 , H03F2203/45371 , H03F2203/45396 , H03F2203/45486 , H03F2203/45504 , H03F2203/45631 , H03F2203/45634 , H03F2203/45726 , H03G1/0029 , H03G1/0088 , H03M1/129
摘要： A data acquisition system (200) includes a programmable gain amplifier (202), an analog-to-digital converter (204), a filter (206), and control circuitry. The programmable gain amplifier (202) is operatively connected to receive an analog input signal on its input (208, 210) and generates an amplified signal on its output (212, 214) in accordance with gain control signals (gc1-gc3). The analog-to-digital converter (204) is operatively connected to receive the amplified signal from the amplifier (202) and generates a digitized signal on its output (216, 218). The filter (206) is operatively connected to receive the digitized signal from the converter (204) and generates a filtered digital signal on its output (220, 222). The control circuitry is operatively connected to the amplifier (202) and to the converter (204) and is also responsive to the gain control signals (gc1-gc3) for dynamically adjusting power between the amplifier and converter when the gain control signals (gc1-gc3) are changed.
摘要翻译：数据采集系统（200）包括可编程增益放大器（202），模数转换器（204），滤波器（206）和控制电路。可编程增益放大器（202）可操作地连接以在其输入端（208,210）上接收模拟输入信号，并根据增益控制信号（gc1-gc3）在其输出端（212,214）产生放大信号。模数转换器（204）可操作地连接以从放大器（202）接收放大的信号，并在其输出（216,218）上生成数字化信号。滤波器（206）可操作地连接以接收来自转换器（204）的数字化信号，并在其输出端（220,222）上生成滤波后的数字信号。控制电路可操作地连接到放大器（202）和转换器（204），并且还响应于增益控制信号（gc1-gc3），用于当增益控制信号（gc1-gc3）动态调整放大器和转换器之间的功率时， gc3）被更改。

8. 发明公开

EP2996266A1 OPTICAL MODULATOR DRIVER CIRCUIT AND OPTICAL TRANSMITTER 审中-公开
标题翻译：驱动电路用于光学调制器和光发射器
公开(公告)号：EP2996266A1
公开(公告)日：2016-03-16
申请号：EP14794331.0
申请日：2014-05-09
申请人： Nippon Telegraph and Telephone Corporation
发明人： NAGATANI, Munehiko , NOSAKA, Hideyuki , ITOH, Toshihiro , MURATA, Koichi , FUKUYAMA, Hiroyuki , SAIDA, Takashi , KAMEI, Shin , YAMAZAKI, Hiroshi , KIKUCHI, Nobuhiro , KOIZUMI, Hiroshi , NOGAWA, Masafumi , KATSURAI, Hiroaki , UZAWA, Hiroyuki , KATAOKA, Tomoyoshi , FUJIWARA, Naoki , KAWAKAMI, Hiroto , HORIKOSHI, Kengo , BOUVIER, Yves , YONEYAMA, Mikio , AISAWA, Shigeki , SUZUKI, Masahiro
IPC分类号： H04B10/516 , H03F1/00 , H03F3/45 , H03F3/60 , H03G3/18
CPC分类号： H04B10/541 , H03F1/223 , H03F1/32 , H03F3/04 , H03F3/082 , H03F3/195 , H03F3/245 , H03F3/45085 , H03F3/45089 , H03F3/45183 , H03F3/45188 , H03F3/602 , H03F2200/18 , H03F2200/219 , H03F2200/255 , H03F2200/27 , H03F2200/336 , H03F2200/411 , H03F2200/72 , H03F2200/75 , H03F2203/45258 , H03F2203/45374 , H03F2203/45392 , H03F2203/45454 , H03F2203/45466 , H03F2203/45471 , H03F2203/45486 , H03F2203/45496 , H03F2203/45504 , H03F2203/45506 , H03F2203/45702 , H03G1/0023 , H03G1/0082 , H03G1/0088 , H03G3/00 , H03G3/001 , H03G3/3084 , H04B10/5561 , H04B10/588
摘要： An optical modulator driver circuit (1) includes an amplifier (50, Q10, Q11, R10 - R13), and a current amount adjustment circuit (51) capable of adjusting a current amount of the amplifier (50) in accordance with a desired operation mode. The current amount adjustment circuit (51) includes at least two current sources (IS10) that are individually ON/OFF-controllable in accordance with a binary control signal representing the desired operation mode.

9. 发明公开

EP1835624A3 Power management in a data acquisition system 审中-公开
标题翻译：电源管理在数据采集系统
公开(公告)号：EP1835624A3
公开(公告)日：2009-01-07
申请号：EP07004908.5
申请日：2007-03-09
申请人： Cirrus Logic, Inc.
发明人： Kejariwal, Murari , Coupe, John R.
IPC分类号： H03M1/12 , H03G1/00
CPC分类号： H03F3/45188 , H03F3/45475 , H03F2200/331 , H03F2203/45032 , H03F2203/45371 , H03F2203/45396 , H03F2203/45486 , H03F2203/45504 , H03F2203/45631 , H03F2203/45634 , H03F2203/45726 , H03G1/0029 , H03G1/0088 , H03M1/129
摘要： A data acquisition system (200) includes a programmable gain amplifier (202), an analog-to-digital converter (204), a filter (206), and control circuitry. The programmable gain amplifier (202) is operatively connected to receive an analog input signal on its input (208, 210) and generates an amplified signal on its output (212, 214) in accordance with gain control signals (gc1-gc3). The analog-to-digital converter (204) is operatively connected to receive the amplified signal from the amplifier (202) and generates a digitized signal on its output (216, 218). The filter (206) is operatively connected to receive the digitized signal from the converter (204) and generates a filtered digital signal on its output (220, 222). The control circuitry is operatively connected to the amplifier (202) and to the converter (204) and is also responsive to the gain control signals (gc1-gc3) for dynamically adjusting power between the amplifier and converter when the gain control signals (gc1-gc3) are changed.

10. 发明申请

US20160087727A1 Optical Modulator Driver Circuit and Optical Transmitter 审中-公开
标题翻译：光调制器驱动电路和光发射机
公开(公告)号：US20160087727A1
公开(公告)日：2016-03-24
申请号：US14889127
申请日：2014-05-09
申请人： NIPPON TELEGRAPH AND TELEPHONE CORPORATION
发明人： Munehiko Nagatani , Hideyuki Nosaka , Toshihiro Itoh , Koichi Murata , Hiroyuki Fukuyama , Takashi Saida , Shin Kamei , Hiroshi Yamazaki , Nobuhiro Kikuchi , Hiroshi Koizumi , Masafumi Nogawa , Hiroaki Katsurai , Hiroyuki Uzawa , Tomoyoshi Kataoka , Naoki Fujiwara , Hiroto Kawakami , Kengo Horikoshi , Yves Bouvier , Mikio Yoneyama , Shigeki Aisawa , Masahiro Suzuki
IPC分类号： H04B10/54 , H03G3/00 , H03F3/04 , H03F3/60 , H03F1/32
CPC分类号： H04B10/541 , H03F1/223 , H03F1/32 , H03F3/04 , H03F3/082 , H03F3/195 , H03F3/245 , H03F3/45085 , H03F3/45089 , H03F3/45183 , H03F3/45188 , H03F3/602 , H03F2200/18 , H03F2200/219 , H03F2200/255 , H03F2200/27 , H03F2200/336 , H03F2200/411 , H03F2200/72 , H03F2200/75 , H03F2203/45258 , H03F2203/45374 , H03F2203/45392 , H03F2203/45454 , H03F2203/45466 , H03F2203/45471 , H03F2203/45486 , H03F2203/45496 , H03F2203/45504 , H03F2203/45506 , H03F2203/45702 , H03G1/0023 , H03G1/0082 , H03G1/0088 , H03G3/00 , H03G3/001 , H03G3/3084 , H04B10/5561 , H04B10/588
摘要： An optical modulator driver circuit (1) includes an amplifier (50, Q10, Q11, R10-R13), and a current amount adjustment circuit (51) capable of adjusting a current amount of the amplifier (50) in accordance with a desired operation mode. The current amount adjustment circuit (51) includes at least two current sources (IS10) that are individually ON/OFF-controllable in accordance with a binary control signal representing the desired operation mode.
摘要翻译：光调制器驱动电路（1）包括放大器（50，Q10，Q11，R10-R13）和电流量调节电路（51），能够根据期望的操作调节放大器（50）的电流量模式。电流量调节电路（51）包括至少两个根据表示期望的操作模式的二进制控制信号单独地进行ON / OFF控制的电流源（IS10）。

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