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1. 发明授权

US08963634B2 Load current sensing 有权
标题翻译：负载电流检测
公开(公告)号：US08963634B2
公开(公告)日：2015-02-24
申请号：US13406775
申请日：2012-02-28
申请人： Ankit Srivastava , Matthew D. Sienko , Meysam Azin , Xiaohong Quan , Peter J. Shah
发明人： Ankit Srivastava , Matthew D. Sienko , Meysam Azin , Xiaohong Quan , Peter J. Shah
IPC分类号： H03F3/04 , H03F3/217 , H03F1/04 , H03F99/00 , H03G3/20 , H03G11/00
CPC分类号： H03F3/2173 , H03F1/523 , H03F3/45179 , H03F3/45183 , H03F3/45475 , H03F2200/426 , H03F2200/462 , H03F2200/471 , H03F2200/481 , H03F2203/45522 , H03F2203/45526
摘要： Techniques for sensing current delivered to a load by a differential output stage, e.g., in a Class D amplifier. In one aspect, voltages across sense resistors coupled in series with first and second branches of the differential output stage are low-passed filtered and digitized. The sense resistors may be coupled in series with the sources of transistors of the first and second branches, wherein the transistors are selectively switchable on and off by input voltage driving voltages. The input driving voltages may correspond to a ternary voltage waveform such that during a given phase, the two transistors coupled in series with the sense resistors may be turned off. Further aspects provide for the first and second branches having cascoded NMOS and/or PMOS transistors, and the sense resistors being provided between a pair of cascoded transistors.
摘要翻译：用于感测由差分输出级（例如D类放大器）传送到负载的电流的技术。在一个方面，与差分输出级的第一和第二分支串联耦合的检测电阻之间的电压被低通滤波和数字化。感测电阻器可以与第一和第二分支的晶体管源串联耦合，其中晶体管可以通过输入电压驱动电压有选择地开关。输入驱动电压可以对应于三元电压波形，使得在给定相位期间，可以关断与感测电阻器串联耦合的两个晶体管。另外的方面提供具有级联的NMOS和/或PMOS晶体管的第一和第二分支，并且感测电阻器被提供在一对级联晶体管之间。

2. 发明授权

US08538362B2 Squelch detection circuit and method 有权
标题翻译：静噪检测电路及方法
公开(公告)号：US08538362B2
公开(公告)日：2013-09-17
申请号：US12837902
申请日：2010-07-16
申请人： Ankit Srivastava , Xiaohong Quan
发明人： Ankit Srivastava , Xiaohong Quan
IPC分类号： H04B1/10
CPC分类号： H04B1/1027 , H03G3/341 , H03K5/2481
摘要： A squelch detection circuit and method involves a first comparator coupled to a complimentary input signal pair and having a first polarity output. A second comparator coupled to the complimentary input signal pair has a second polarity output. An offset associated with complimentary input signal pair establishes a positive squelch threshold and a negative squelch threshold. A calibration unit coupled to the first comparator and the second comparator generates a digital output including threshold settings and calibration settings to the first comparator and to the second comparator. The digital output can be associated with establishing the offset and with calibrating the positive squelch threshold and the negative squelch threshold.
摘要翻译：静噪检测电路和方法包括耦合到互补输入信号对并具有第一极性输出的第一比较器。耦合到互补输入信号对的第二比较器具有第二极性输出。与补偿输入信号对相关的偏移量建立正静噪阈值和负静噪阈值。耦合到第一比较器和第二比较器的校准单元产生包括阈值设置和校准设置的数字输出到第一比较器和第二比较器。数字输出可以与建立偏移量相关联，并校准正静噪阈值和负静噪阈值。

3. 发明申请

US20080111580A1 Suppressing ringing in high speed CMOS output buffers driving transmission line load 有权
标题翻译：抑制高速CMOS输出缓冲器中的振铃驱动传输线负载
公开(公告)号：US20080111580A1
公开(公告)日：2008-05-15
申请号：US11897520
申请日：2007-08-30
申请人： Ankit Kumar Rathi , Ankit Srivastava , Paras Garg
发明人： Ankit Kumar Rathi , Ankit Srivastava , Paras Garg
IPC分类号： H03K17/16
CPC分类号： H03K17/6872 , H03K17/04206 , H03K17/0822 , H03K17/165
摘要： An output buffer circuit for improving an output during state transitions of CMOS buffers driving transmission line loads. The circuit generates variable output impedance proportional to the load transmission line impedance. The buffer includes an output stage, such as pull up/pull down drivers for receiving an input signal and generating an output signal. The pull up/pull down drivers are biased by a circuit that generates a control signal and varies its conductivity according to the control signal. The pull up/pull down drivers initially provide a relatively low impedance to reach a desired level during the initial transition period of the output and then slowly varies its impedance in response to the control signal to suppress the ringing effect. The control circuit coupled to the input node, output node and the power supply node to generate a control signal that biases the pull up/pull down driver.
摘要翻译：一种用于在驱动传输线负载的CMOS缓冲器的状态转变期间改善输出的输出缓冲器电路。电路产生与负载传输线阻抗成比例的可变输出阻抗。缓冲器包括输出级，例如用于接收输入信号并产生输出信号的上拉/下拉驱动器。上拉/下拉驱动器由产生控制信号的电路偏置，并根据控制信号改变其电导率。上拉/下拉驱动器最初提供相对较低的阻抗以在输出的初始过渡期间达到期望的电平，然后响应于控制信号缓慢地改变其阻抗以抑制振铃效应。控制电路耦合到输入节点，输出节点和电源节点，以产生偏置上拉/下拉驱动器的控制信号。

4. 发明申请

US20200163157A1 SYSTEMS AND METHODS FOR MANAGING HYPER-LOCALIZED COMMUNICATION NETWORKS 审中-公开
公开(公告)号：US20200163157A1
公开(公告)日：2020-05-21
申请号：US16685325
申请日：2019-11-15
申请人： Sarthak S. Sawarkar , Ankit Srivastava , Amit Degavekar , Sudha Haran
发明人： Sarthak S. Sawarkar , Ankit Srivastava , Amit Degavekar , Sudha Haran
IPC分类号： H04W88/06 , H04W4/029 , H04L29/08 , H04W64/00 , H04W84/12
摘要： According to various embodiments, a communication system can be configured to build gated or secured networks that require physical presence to interact on the respective communication network. In some embodiments, these secured networks are associated with a real world or physical location, such that a user must be within or proximate to the real world or physical location in order to access communication taking place on the secured network. In further embodiments, the system can manage any number of such networks simultaneously. In some examples, users are allowed to create their own secured network and associate their network with a specific location or location boundary.

5. 发明授权

US08446204B2 High voltage tolerant receiver 有权
标题翻译：高耐压接收机
公开(公告)号：US08446204B2
公开(公告)日：2013-05-21
申请号：US13014740
申请日：2011-01-27
申请人： Ankit Srivastava , Xuhao Huang , Xiaohong Quan
发明人： Ankit Srivastava , Xuhao Huang , Xiaohong Quan
IPC分类号： H03L5/00 , H03K3/00
CPC分类号： H03K3/3565 , H03K19/018521
摘要： A high voltage tolerant single ended receiver circuit includes a voltage divider that is operative to divide in half single ended input signals that are greater than the threshold voltages of the voltage divider. A pass gate circuit is operative to receive single ended signals that are below the threshold voltages of the voltage divider. Output from the voltage divider is coupled to a first input of a modified Schmitt trigger circuit to control a high threshold level of the Schmitt trigger circuit. Output from the pass gate circuit is coupled to a second input of the modified Schmitt trigger circuit to control a low threshold level of the Schmitt trigger circuit.
摘要翻译：高耐压单端接收器电路包括分压器，其可操作地将大于分压器的阈值电压的半个单端输入信号分频。通路门电路用于接收低于分压器的阈值电压的单端信号。来自分压器的输出耦合到修改的施密特触发电路的第一输入端，以控制施密特触发电路的高阈值电平。来自通路电路的输出耦合到修改的施密特触发电路的第二输入，以控制施密特触发电路的低阈值电平。

6. 发明授权

US08373267B2 Electrostatic discharge (ESD) silicon controlled rectifier (SCR) structure 有权
公开(公告)号：US08373267B2
公开(公告)日：2013-02-12
申请号：US13196404
申请日：2011-08-02
申请人： Robert J. Gauthier, Jr. , Junjun Li , Ankit Srivastava
发明人： Robert J. Gauthier, Jr. , Junjun Li , Ankit Srivastava
IPC分类号： H01L29/66 , H01L23/62
CPC分类号： H01L29/66386 , H01L24/06 , H01L27/0262 , H01L29/74 , H01L29/7436 , H01L2224/05554 , H01L2924/14 , H01L2924/00
摘要： A structure includes first and second silicon controlled rectifiers (SCRs) formed in a substrate. The first and the second SCRs each include at least one component commonly shared between the first and the second SCRs.

7. 发明申请

US20120235730A1 CHARGE PUMP SURGE CURRENT REDUCTION 审中-公开
标题翻译：充电泵浪涌电流减少
公开(公告)号：US20120235730A1
公开(公告)日：2012-09-20
申请号：US13047689
申请日：2011-03-14
申请人： Xiaohong Quan , Ankit Srivastava , Guoqing Miao
发明人： Xiaohong Quan , Ankit Srivastava , Guoqing Miao
IPC分类号： G05F3/02
CPC分类号： H02M3/07 , H02M1/36 , H02M2001/0045 , H02M2003/071 , H02M2003/072
摘要： Techniques for reducing surge current in charge pumps. In an exemplary embodiment, one or more switches coupling a terminal of a flying capacitor to a voltage supply are configured to have variable on-resistance. When the charge pump is configured to switch a gain mode from a lower gain to a higher gain, the one or more variable resistance switches are configured to have a decreasing resistance profile over time. In this manner, surge current drawn from the voltage supply at the outset of the gain switch may be limited, while the on-resistance during steady-state charging and discharging may be kept low. Similar techniques are provided to decrease the surge current from a bypass switch coupling the supply voltage to a positive output voltage of the charge pump.
摘要翻译：降低电荷泵浪涌电流的技术。在示例性实施例中，将飞跨电容器的端子耦合到电压源的一个或多个开关被配置为具有可变的导通电阻。当电荷泵被配置为将增益模式从较低增益切换到较高增益时，一个或多个可变电阻开关被配置为具有随时间减小的电阻分布。以这种方式，可以限制在增益开关开始时从电压源引出的浪涌电流，而稳态充放电期间的导通电阻可以保持较低。提供了类似的技术以减少将电源电压耦合到电荷泵的正输出电压的旁路开关的浪涌电流。

8. 发明申请

US20120194254A1 High Voltage Tolerant Receiver 有权
标题翻译：高耐压接收器
公开(公告)号：US20120194254A1
公开(公告)日：2012-08-02
申请号：US13014740
申请日：2011-01-27
申请人： Ankit Srivastava , Xuhao Huang , Xiaohong Quan
发明人： Ankit Srivastava , Xuhao Huang , Xiaohong Quan
IPC分类号： H03L5/00
CPC分类号： H03K3/3565 , H03K19/018521
摘要： A high voltage tolerant single ended receiver circuit includes a voltage divider that is operative to divide in half single ended input signals that are greater than the threshold voltages of the voltage divider. A pass gate circuit is operative to receive single ended signals that are below the threshold voltages of the voltage divider. Output from the voltage divider is coupled to a first input of a modified Schmitt trigger circuit to control a high threshold level of the Schmitt trigger circuit. Output from the pass gate circuit is coupled to a second input of the modified Schmitt trigger circuit to control a low threshold level of the Schmitt trigger circuit.
摘要翻译：高耐压单端接收器电路包括分压器，其可操作地将大于分压器的阈值电压的半个单端输入信号分频。通路门电路用于接收低于分压器的阈值电压的单端信号。来自分压器的输出耦合到修改的施密特触发电路的第一输入端，以控制施密特触发电路的高阈值电平。来自通路电路的输出耦合到修改的施密特触发电路的第二输入，以控制施密特触发电路的低阈值电平。

9. 发明申请

US20110284925A1 ELECTROSTATIC DISCHARGE (ESD) SILICON CONTROLLED RECTIFIER (SCR) STRUCTURE 有权
标题翻译：静电放电（ESD）硅控制整流器（SCR）结构
公开(公告)号：US20110284925A1
公开(公告)日：2011-11-24
申请号：US13196404
申请日：2011-08-02
申请人： Robert J. GAUTHIER, JR. , Junjun LI , Ankit SRIVASTAVA
发明人： Robert J. GAUTHIER, JR. , Junjun LI , Ankit SRIVASTAVA
IPC分类号： H01L29/73
CPC分类号： H01L29/66386 , H01L24/06 , H01L27/0262 , H01L29/74 , H01L29/7436 , H01L2224/05554 , H01L2924/14 , H01L2924/00
摘要： A structure includes first and second silicon controlled rectifiers (SCRs) formed in a substrate. The first and the second SCRs each include at least one component commonly shared between the first and the second SCRs.
摘要翻译：一种结构包括在基板中形成的第一和第二硅可控整流器（SCR）。第一和第二SCR各自包括在第一和第二SCR之间共同共享的至少一个部件。

10. 发明授权

US07826188B2 Methods, design structures, and systems for current mode logic (CML) differential driver ESD protection circuitry 失效
标题翻译：电流模式逻辑（CML）差分驱动器ESD保护电路的方法，设计结构和系统
公开(公告)号：US07826188B2
公开(公告)日：2010-11-02
申请号：US12140485
申请日：2008-06-17
申请人： Robert J. Gauthier, Jr. , Junjun Li , Ankit Srivastava
发明人： Robert J. Gauthier, Jr. , Junjun Li , Ankit Srivastava
IPC分类号： H02H9/00 , H01C7/12 , H02H1/00 , H02H1/04 , H02H3/22 , H02H9/06
CPC分类号： H03F3/45188 , H01L27/0251 , H03F1/52 , H03F1/523 , H03F2203/45466 , H03F2203/45486 , H03F2203/45504
摘要： A hardware description language (HDL) design structure encoded on a machine readable data storage medium, the HDL design comprising elements that when processed in a computer aided design system generates a machine executable representation of a device for implementing dynamic refresh protocols for DRAM based cache. The HDL design structure further comprises an integrated circuit having a differential driver, comprising: a first driver and a second driver forming the differential driver, the drivers are coupled in parallel between a first voltage source and a second voltage source; a first switch coupled to the first driver and configured to turn off the first driver during an ESD event such that the first driver sustains stress during the ESD event; and a second switch coupled to the second driver and configured to turn off the second driver during the ESD event such that the second driver sustains stress during the ESD event.
摘要翻译：在机器可读数据存储介质上编码的硬件描述语言（HDL）设计结构，所述HDL设计包括在计算机辅助设计系统中处理时的元件，生成用于实现基于DRAM的高速缓存的动态刷新协议的设备的机器可执行表示。 HDL设计结构还包括具有差分驱动器的集成电路，包括：形成差分驱动器的第一驱动器和第二驱动器，驱动器并联耦合在第一电压源和第二电压源之间; 第一开关，其耦合到所述第一驱动器并且被配置为在ESD事件期间关闭所述第一驱动器，使得所述第一驱动器在所述ESD事件期间保持应力; 以及耦合到所述第二驱动器并被配置为在所述ESD事件期间关闭所述第二驱动器的第二开关，使得所述第二驱动器在所述ESD事件期间维持应力。

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