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1. 发明专利

JP2011086837A Semiconductor device and method of forming the same 审中-公开
标题翻译：半导体器件及其形成方法
公开(公告)号：JP2011086837A
公开(公告)日：2011-04-28
申请号：JP2009239800
申请日：2009-10-16
申请人： Semiconductor Technology Academic Research Center , Tohoku Univ , 国立大学法人東北大学 , 株式会社半導体理工学研究センター
发明人： KOIKE JUNICHI , SUDO YUJI , FUJII SHIGETO , SHIMIZU NORIYOSHI , MAEKAWA KAZUYOSHI , ARITA KOJI , YAGI RYOTARO , YOSHIMARU MASAKI
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522
摘要： PROBLEM TO BE SOLVED: To form an adhesion improved layer made of oxide at the interface between a Cu wire and a cap layer in a multilayer wiring structure of a semiconductor device, and to improve reliability of the Cu wire to migration without increasing resistance of the Cu wire. SOLUTION: The multilayer wiring structure of the semiconductor device includes a first insulating layer (2) formed on a semiconductor wafer (1), the Cu wiring layer (4) provided in an opening opened on a surface of the first insulating layer, a second insulating layer (6) formed on surfaces of the first insulating layer and the Cu wiring layer, and an insulating metal oxide layer (5) formed at the interface between the Cu wiring layer and cap layer as the second insulating layer. The metal oxide layer (5) is formed by immersion plating of metal such as Sn or Zn on the Cu wiring layer (4) and then conducting heat treatment on the plated layer under the oxidation atmosphere. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：在半导体器件的多层布线结构中，在Cu线和覆盖层之间的界面处形成由氧化物形成的附着改善层，并且提高Cu线的迁移的可靠性而不增加铜线的电阻。解决方案：半导体器件的多层布线结构包括形成在半导体晶片（1）上的第一绝缘层（2），设置在第一绝缘层的表面上开口的开口中的Cu布线层（4）形成在所述第一绝缘层和所述Cu布线层的表面上的第二绝缘层（6）和形成在所述Cu布线层和所述盖层之间的界面处的绝缘金属氧化物层（5）作为所述第二绝缘层。金属氧化物层（5）通过在Cu布线层（4）上浸渍诸如Sn或Zn的金属形成，然后在氧化气氛下对镀层进行热处理。版权所有（C）2011，JPO＆INPIT

2. 发明专利

JP2011054766A Resistance change memory, and method of manufacturing the same 审中-公开
标题翻译：电阻变化记忆体及其制造方法
公开(公告)号：JP2011054766A
公开(公告)日：2011-03-17
申请号：JP2009202483
申请日：2009-09-02
申请人： Semiconductor Technology Academic Research Center , 株式会社半導体理工学研究センター
发明人： TAKAHASHI TSUNEO , ARITA MASASHI , FUJII TAKASHI , KAJI HIROMICHI , KONDO YOJI , SHIGENIWA MASAHIRO , FUJIWARA ICHIRO , YAMAGUCHI TAKESHI , YOSHIMARU MASAKI
IPC分类号： H01L27/10 , H01L45/00 , H01L49/00
摘要： PROBLEM TO BE SOLVED: To provide a resistance change memory capable of exhibiting hysteresis characteristics and memory characteristics of resistance securely with higher reproducibility than conventional techniques, and to provide a method of manufacturing the memory.
SOLUTION: The resistance change memory, constituted by sandwiching a PCMO layer of Pr
x Ca
1-x MnO
3 between a lower and an upper electrode, has a metal oxide layer inserted and formed between the PCMO layer and the upper or lower electrode. Here, the metal oxide is an oxide of metal of the upper electrode, and at least one of the upper and lower electrodes is made of one of tungsten (W), molybdenum (Mo), chromium (Cr), aluminum (Al) and silver (Ag).
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供能够以比常规技术更高的再现性可靠地显示磁滞特性和电阻的存储特性的电阻变化存储器，并提供一种制造存储器的方法。
解决方案：电阻变化记忆是通过将下一层和下层之间的第一层和第二层的第一层和第二层上电极具有插入并形成在PCMO层和上电极或下电极之间的金属氧化物层。这里，金属氧化物是上部电极的金属氧化物，上部电极和下部电极中的至少一个由钨（W），钼（Mo），铬（Cr），铝（Al）和银（Ag）。版权所有（C）2011，JPO＆INPIT

3. 发明专利

JP2010171384A Simulation device and method for designing semiconductor device, semiconductor device, and manufacturing method therefor 审中-公开
标题翻译：用于设计半导体器件的模拟装置和方法，半导体器件及其制造方法
公开(公告)号：JP2010171384A
公开(公告)日：2010-08-05
申请号：JP2009258376
申请日：2009-11-11
申请人： Semiconductor Technology Academic Research Center , 株式会社半導体理工学研究センター
发明人： MIURA MICHIKO , NAKAYAMA NORIAKI
IPC分类号： H01L21/336 , H01L29/00 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a simulation method for designing a semiconductor device estimating or reproducing the operation of the semiconductor device in practically acceptable time and with high precision.
SOLUTION: In the simulation method, between the source and the drain, at least a portion of a difference between a carrier density described in a quasi-static steady state at a first time, and a carrier density described in a transient state at a second time preceding the first time, is added to the carrier density described in a transient state at the second time, depending on a carrier's delay between the first time and the second time, and the carrier density of the first time is described in a transient state. A transient current between the source and the drain is described as the total of a steady-state current and a displacement current regarding as a time variation proportion of a quasi-static carrier density between the source and the drain. Assuming that the quasi-static carrier density satisfies the transient current, the quasi-static carrier density is described as a non-quasi-static model.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于在实际可接受的时间和高精度下设计在半导体器件中估计或再现操作的半导体器件的模拟方法。解决方案：在仿真方法中，在源极和漏极之间，在第一时间在准静态稳态中描述的载流子密度与在瞬态描述的载流子密度之间的差异的至少一部分在第一时间之后的第二时间，根据第一时间和第二时间之间的载波的延迟，在第二时间将其描述在瞬态状态中描述的载波密度，并且第一次的载波密度在一个暂时的状态。源极和漏极之间的瞬态电流被描述为关于作为源极和漏极之间的准静态载流子密度的时间变化比例的稳态电流和位移电流的总和。假设准静态载流子密度满足瞬态电流，将准静态载流子密度描述为非准静态模型。版权所有（C）2010，JPO＆INPIT

4. 发明专利

JP2010113470A Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：JP2010113470A
公开(公告)日：2010-05-20
申请号：JP2008284574
申请日：2008-11-05
申请人： Semiconductor Technology Academic Research Center , 株式会社半導体理工学研究センター
发明人： SHIOYA RYOTA , GOSHIMA MASAHIRO , SAKAI SHUICHI
IPC分类号： G06F9/34 , G06F9/38
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit enabling reduction of a circuit area without causing the performance degradation. SOLUTION: This semiconductor integrated circuit 1 includes: a first memory 30 for storing data; and a second memory 10 functioning as a cache memory for the first memory 30, and configured to perform the pipe line performance of readout processing and write-in processing for the data by a plurality of processing stages, and when it is determined the data as the object of readout processing are read from the first memory 30, the readout of the data from the first memory 30 is performed by any RR and RR/CR of the processing stages. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供能够减少电路面积而不会导致性能下降的半导体集成电路。解决方案：该半导体集成电路1包括：用于存储数据的第一存储器30; 以及作为第一存储器30的高速缓冲存储器起作用的第二存储器10，并且被配置为通过多个处理级执行读取处理和数据的写入处理的管线性能，并且当确定数据为从第一存储器30读出读出处理的对象，通过处理级的任何RR和RR / CR执行来自第一存储器30的数据的读出。版权所有（C）2010，JPO＆INPIT

5. 发明专利

JP2011041105A High-frequency signal generator circuit 有权
标题翻译：高频信号发生器电路
公开(公告)号：JP2011041105A
公开(公告)日：2011-02-24
申请号：JP2009188066
申请日：2009-08-14
申请人： Semiconductor Technology Academic Research Center , 株式会社半導体理工学研究センター
发明人： NAKANO KAZUO , AMAKAWA SHUHEI , ISHIHARA NOBORU , EKI KAZUYA
IPC分类号： H03K3/0231 , H03B28/00 , H03K5/13 , H03K5/131
CPC分类号： H03K3/0322 , G06F1/022
摘要： PROBLEM TO BE SOLVED: To provide a high-frequency signal generating circuit which is capable of operating over wide bands, at a low voltage and reducing the circuit area.
SOLUTION: A signal generating circuit 13 generates a signal of the same frequency as that of an output signal. A delay means 14 includes a plurality of delay circuits 17 and delays a signal generated by the signal generating circuit 13. A selection means 15 selects the output signals of the plurality of delay circuits 17. A combination means 19 combines signals selected by the selection means 15 and outputs an output signal. A control means 12 controls the selection means 15 based on data for setting a waveform of the output signal and a control signal for setting at least the amplitude, phase and frequency of the output signal.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够在宽带上工作的低频信号发生电路，并且减小电路面积。解决方案：信号发生电路13产生与输出信号相同频率的信号。延迟装置14包括多个延迟电路17并且延迟由信号发生电路13产生的信号。选择装置15选择多个延迟电路17的输出信号。组合装置19组合由选择装置选择的信号并输出输出信号。控制装置12基于用于设置输出信号的波形的数据和用于设置至少输出信号的幅度，相位和频率的控制信号来控制选择装置15。版权所有（C）2011，JPO＆INPIT

6. 发明专利

JP2010258481A Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2010258481A
公开(公告)日：2010-11-11
申请号：JP2010182513
申请日：2010-08-17
申请人： Semiconductor Technology Academic Research Center , 株式会社半導体理工学研究センター
发明人： MIYAO MASANOBU , NAKAJIMA HIROSHI , SADO TAIZO , MIZUSHIMA ICHIRO , YOSHIMARU MASAKI
IPC分类号： H01L21/20
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device that can have a plurality of kinds of semiconductor elements, differing in lattice constant, mixedly mounted on the same substrate.
SOLUTION: The method of manufacturing the semiconductor device includes forming an insulating film 22 at a portion of the silicon substrate 21, forming an amorphous SiGe layer 23 on the silicon substrate 21 and insulating film 22, heat-treating the silicon substrate to crystallize the amorphous SiGe layer 23 laterally on the insulating film 22 by solid-phase or liquid-phase growth, and forming an SiGe layer 23b, whose lattice constant is matched with that of a material layer to be formed later, on the silicon substrate 21 and insulating film 22.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：解决的问题：提供一种半导体器件的制造方法，该半导体器件可以具有晶格常数不同的多种半导体元件，该半导体元件混合地安装在同一衬底上。解决方案：制造半导体器件的方法包括在硅衬底21的一部分处形成绝缘膜22，在硅衬底21和绝缘膜22上形成非晶SiGe层23，将硅衬底热处理为通过固相或液相生长在绝缘膜22上横向地晶化非晶SiGe层23，并且在硅衬底21上形成晶格常数与稍后形成的材料层的晶格常数相匹配的SiGe层23b 和绝缘膜22.版权所有（C）2011，JPO＆INPIT

7. 发明专利

JP2010074636A Differential operational amplifier circuit and pipeline-type a/d conversion device employing the same 有权
标题翻译：差分运算放大器电路和使用其的管道型A / D转换器件
公开(公告)号：JP2010074636A
公开(公告)日：2010-04-02
申请号：JP2008241120
申请日：2008-09-19
申请人： Semiconductor Technology Academic Research Center , 株式会社半導体理工学研究センター
发明人： KAWAHITO SHOJI , HONDA KAZUTAKA , SHIMIZU YASUHIDE , TANI KUNIYUKI , KURAUCHI TERU , SUSHIHARA KIMIHARU , MASUKO KOICHIRO
IPC分类号： H03M1/14 , H03F1/22 , H03F3/45 , H03M1/10
CPC分类号： H03F3/45237 , H03F2203/45094 , H03F2203/45356 , H03F2203/45481 , H03F2203/45551
摘要： PROBLEM TO BE SOLVED: To perform high-accuracy settling error correction by a simple configuration available for a high-resolution A-D conversion device.
SOLUTION: In a telescopic differential operational amplifier circuit in which two auxiliary differential amplifiers are connected to two sets of cascode circuits each comprised of cascode-connected first to fourth transistors, in a sampling phase, first and second switches are turned on, a predetermined bias voltage is applied to gates of the first and fourth transistors, and an input terminal of the differential operational amplifier circuit is set to a common-mode voltage. In a hold phase, the first and second switches are turned off, gates of the first and fourth transistors are varied while following an input signal input via the input terminal, a coupling capacitor operates as a level shifter for the input signal, and the amplifier circuit performs a push-pull operation, thereby operating only in a gm driving area and not operating in a slewing area.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：通过可用于高分辨率A-D转换装置的简单配置来执行高精度建立误差校正。解决方案：在一个伸缩差分运算放大器电路中，其中两个辅助差分放大器连接到由共源共栅型第一至第四晶体管组成的两组共源共栅电路，在采样阶段，第一和第二开关导通，对第一和第四晶体管的栅极施加预定的偏置电压，并且将差分运算放大器电路的输入端子设置为共模电压。在保持阶段中，第一和第二开关被关断，第一和第四晶体管的栅极在跟随通过输入端输入的输入信号之后变化，耦合电容器作为输入信号的电平移位器工作，放大器电路执行推挽操作，从而仅在gm驱动区域中操作并且不在回转区域中操作。版权所有（C）2010，JPO＆INPIT

8. 发明专利

JP2009272915A Sample/hold circuit, and a/d conversion device 有权
标题翻译：采样/保持电路和A / D转换器件
公开(公告)号：JP2009272915A
公开(公告)日：2009-11-19
申请号：JP2008121938
申请日：2008-05-08
申请人： Semiconductor Technology Academic Research Center , 株式会社半導体理工学研究センター
发明人： KAWAHITO SHOJI , RYU TADASHI , SHIMIZU YASUHIDE , TANI KUNIYUKI , KURAUCHI TERU , SUSHIHARA KIMIHARU , MASUKO KOICHIRO
IPC分类号： H03M1/12 , G11C27/02
CPC分类号： H03M1/1009 , G11C27/026 , H03M1/1215
摘要： PROBLEM TO BE SOLVED: To provide a sample/hold circuit capable of extremely simply and stably measuring the amount of clock skew relative to a conventional technique by inputting a calibration signal without using a reference voltage source; and an A/D conversion device using it.
SOLUTION: This sample/hold circuit 1A includes sampling capacitors Cs and a sample/hold amplifier 10, and samples and holds an input signal Vin by using a switched capacitor. An adder circuit adds the input signal Vin to a ramp calibration signal Vcal by inputting, to the sample/hold amplifier 10, the ramp calibration signal Vcal generated to have a frequency identical to that of a sampling clock signal and a predetermined gradient based on the sampling clock signal through calibrating capacitors Ccal having capacitance smaller than the capacitance of the sampling capacitor Cs. In addition, this A/D conversion device is composed by using the sample/hold circuit 1A.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种采样/保持电路，其能够通过在不使用参考电压源的情况下输入校准信号来极其简单且稳定地测量相对于常规技术的时钟偏移量; 和使用它的A / D转换装置。解决方案：该采样/保持电路1A包括采样电容器Cs和采样/保持放大器10，并且通过使用开关电容器采样和保持输入信号Vin。加法器电路将输入信号Vin加到斜坡校准信号Vcal，通过将采样/保持放大器10产生的斜坡校准信号Vcal与采样时钟信号和预定梯度的频率相同，通过校准具有小于采样电容器Cs的电容的电容的电容器Ccal来采样时钟信号。此外，该A / D转换装置由采样保持电路1A构成。版权所有（C）2010，JPO＆INPIT

9. 发明专利

JP2009272757A Mems resonator, mems oscillation circuit, and mems device 有权
标题翻译： MEMS谐振器，MEMS振荡电路和MEMS器件
公开(公告)号：JP2009272757A
公开(公告)日：2009-11-19
申请号：JP2008119796
申请日：2008-05-01
申请人： Semiconductor Technology Academic Research Center , 株式会社半導体理工学研究センター
发明人： SUZUKI KENICHIRO
IPC分类号： H03H9/24 , B81B3/00 , H03B5/30
CPC分类号： H03H9/2463 , H03H3/0072 , H03H9/02259 , H03H2009/02299 , H03H2009/02496
摘要： PROBLEM TO BE SOLVED: To provide a resonator which resonates, at at least one of the fundamental frequencies and higher harmonic wave frequencies, moreover, changes the resonance frequency, and allows excitation by a small driving voltage, as compared with the conventional technologies without using overtone technology, and to provide an oscillation circuit and a MEMS (micro-electromechanical-system) device.
SOLUTION: The MEMS resonator is provided with: a movable main beam 3 which is electrically insulated from a substrate 10, and fixed at least by one fixing end; at least one movable sub-beam 4, which is formed so as to be extended from the movable main beam 3; and at least an exciting electrode 5, which is formed so as to approach the movable sub beam 4. The movable sub beam 4 is excited by an electrostatic force for vibration to resonate at the fundamental resonance frequency, and at least one of the higher harmonic wave frequencies by making the exciting electrode 5 resonate by using an AC signal.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了提供在基频和高次谐波频率中的至少一个谐振的谐振器，与传统的谐波频率相比，谐振频率改变，并且通过小的驱动电压允许激励技术，而不使用泛音技术，并提供振荡电路和MEMS（微机电系统）装置。解决方案：MEMS谐振器设置有：与基板10电绝缘并至少固定在一个固定端的可移动主梁3; 形成为从可动主梁3延伸的至少一个可移动子光束4; 以及至少形成为接近可动子光束4的激励电极5.可动副光束4被静电力激励，以便以基本共振频率谐振，并且至少一个高次谐波通过使得激励电极5通过使用AC信号而共振来产生波频。版权所有（C）2010，JPO＆INPIT

10. 发明专利

JP2011193176A Microphone array network system and sound source localization method using the system 有权
标题翻译：麦克风阵列网络系统和使用该系统的声源定位方法
公开(公告)号：JP2011193176A
公开(公告)日：2011-09-29
申请号：JP2010056796
申请日：2010-03-12
申请人： Semiconductor Technology Academic Research Center , 株式会社半導体理工学研究センター
发明人： KAWAGUCHI HIROSHI , YOSHIMOTO MASAHIKO , NOGUCHI HIROKI , TAKAGI TOMOYA , KUGATA KOJI
IPC分类号： H04R3/00 , G10L15/28 , G10L21/02 , H04R1/40
摘要： PROBLEM TO BE SOLVED: To provide a microphone array network system which controls an amount of network communication even if the number of microphone array nodes and the number of microphones within the node are increased and sound processing performance is improved, and a sound source localization method which improves the accuracy of sound source localization.
SOLUTION: A plurality of nodes that have a microphone array and a sound processing server are connected through a network. Each node has: the microphone array in which a plurality of microphones are arranged in an array; a sound collecting processor which inputs sound collecting signals and estimates a sound source direction; and a data communication part which transmits a sound source direction estimation result, the maximum response strength, and sound data to the sound processing server through data transmission. The sound processing server calculates a plurality of sound source location candidates and estimates a sound source location based on the sound source direction estimation result and the maximum response strength of each node. In addition, the sound processing server fetches sound data from a specified node, based on the sound source location estimation.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：即使提高了麦克风阵列节点的数量和节点内的麦克风的数量并且提高了声音处理性能，也提供了一种控制网络通信量的麦克风阵列网络系统，并且声音源定位方法，提高了声源定位的准确性。解决方案：具有麦克风阵列和声音处理服务器的多个节点通过网络连接。每个节点具有：阵列中布置有多个麦克风的麦克风阵列; 声音采集处理器，其输入声音采集信号并估计声源方向; 以及通过数据传输将声源方向估计结果，最大响应强度和声音数据发送到声音处理服务器的数据通信部分。声音处理服务器基于声源方向估计结果和每个节点的最大响应强度来计算多个声源位置候选并且估计声源位置。此外，声音处理服务器基于声源位置估计从指定节点取出声音数据。版权所有（C）2011，JPO＆INPIT

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