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1. 发明专利

JP2009141861A Pipeline type a/d converter 有权
标题翻译：管路式A / D转换器
公开(公告)号：JP2009141861A
公开(公告)日：2009-06-25
申请号：JP2007318466
申请日：2007-12-10
申请人： Semiconductor Technology Academic Research Center , 株式会社半導体理工学研究センター
发明人： KAWAHITO SHOJI , HONDA KAZUTAKA , SHIMIZU YASUHIDE , TANI KUNIYUKI , KURAUCHI TERU , SUSHIHARA KIMIHARU
IPC分类号： H03M1/14
CPC分类号： H03M1/002 , H03M1/0695 , H03M1/164 , H03M1/361 , H03M1/442
摘要： PROBLEM TO BE SOLVED: To provide a pipeline type A/D converter which can reduce a power consumption when compared with the prior art or can shorten a processing time while avoiding an increase in the power consumption. SOLUTION: In the pipeline type A/D converter including a plurality of A/D conversion circuits mutually connected in cascade for converting a sample and hold signal in a pipeline format, each of the A/D conversation circuits includes a pre-A/D conversation circuit wherein each A/D conversion circuit converts an analog input signal to a digital signal so as to perform A/D conversion; and a multiplication type A/D conversion circuit for D/A conversion to convert the digital signal to an analog control signal, while the D/A conversion sampling the input signal using a sampling capacitor and holding it, and then amplifying it. A precharge circuit, before the sampling operation, previously charges the sampling capacitor so as to have a predetermined output value according to digital input/output characteristics substantially conforming to input/output characteristics of the A/D conversion circuits each indicating an output signal of each A/D conversion circuit to an input signal thereof. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种与现有技术相比可以降低功耗的流水线型A / D转换器，或者可以缩短处理时间，同时避免功耗的增加。解决方案：在具有以流水线格式转换采样和保持信号的级联相互连接的多个A / D转换电路的流水线型A / D转换器中，每个A / D对话电路包括： A / D对话电路，其中每个A / D转换电路将模拟输入信号转换成数字信号，以进行A / D转换; 以及用于D / A转换的乘法型A / D转换电路，用于将数字信号转换为模拟控制信号，而D / A转换使用采样电容对输入信号进行采样，并将其放大。在采样操作之前的预充电电路预先对采样电容器进行充电，以便根据大体上符合A / D转换电路的输入/输出特性的数字输入/输出特性具有预定的输出值，每个A / D转换电路各自表示每个 A / D转换电路输入到其输入信号。版权所有（C）2009，JPO＆INPIT

2. 发明专利

JP2010074636A Differential operational amplifier circuit and pipeline-type a/d conversion device employing the same 有权
标题翻译：差分运算放大器电路和使用其的管道型A / D转换器件
公开(公告)号：JP2010074636A
公开(公告)日：2010-04-02
申请号：JP2008241120
申请日：2008-09-19
申请人： Semiconductor Technology Academic Research Center , 株式会社半導体理工学研究センター
发明人： KAWAHITO SHOJI , HONDA KAZUTAKA , SHIMIZU YASUHIDE , TANI KUNIYUKI , KURAUCHI TERU , SUSHIHARA KIMIHARU , MASUKO KOICHIRO
IPC分类号： H03M1/14 , H03F1/22 , H03F3/45 , H03M1/10
CPC分类号： H03F3/45237 , H03F2203/45094 , H03F2203/45356 , H03F2203/45481 , H03F2203/45551
摘要： PROBLEM TO BE SOLVED: To perform high-accuracy settling error correction by a simple configuration available for a high-resolution A-D conversion device.
SOLUTION: In a telescopic differential operational amplifier circuit in which two auxiliary differential amplifiers are connected to two sets of cascode circuits each comprised of cascode-connected first to fourth transistors, in a sampling phase, first and second switches are turned on, a predetermined bias voltage is applied to gates of the first and fourth transistors, and an input terminal of the differential operational amplifier circuit is set to a common-mode voltage. In a hold phase, the first and second switches are turned off, gates of the first and fourth transistors are varied while following an input signal input via the input terminal, a coupling capacitor operates as a level shifter for the input signal, and the amplifier circuit performs a push-pull operation, thereby operating only in a gm driving area and not operating in a slewing area.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：通过可用于高分辨率A-D转换装置的简单配置来执行高精度建立误差校正。解决方案：在一个伸缩差分运算放大器电路中，其中两个辅助差分放大器连接到由共源共栅型第一至第四晶体管组成的两组共源共栅电路，在采样阶段，第一和第二开关导通，对第一和第四晶体管的栅极施加预定的偏置电压，并且将差分运算放大器电路的输入端子设置为共模电压。在保持阶段中，第一和第二开关被关断，第一和第四晶体管的栅极在跟随通过输入端输入的输入信号之后变化，耦合电容器作为输入信号的电平移位器工作，放大器电路执行推挽操作，从而仅在gm驱动区域中操作并且不在回转区域中操作。版权所有（C）2010，JPO＆INPIT

3. 发明专利

JP2009272915A Sample/hold circuit, and a/d conversion device 有权
标题翻译：采样/保持电路和A / D转换器件
公开(公告)号：JP2009272915A
公开(公告)日：2009-11-19
申请号：JP2008121938
申请日：2008-05-08
申请人： Semiconductor Technology Academic Research Center , 株式会社半導体理工学研究センター
发明人： KAWAHITO SHOJI , RYU TADASHI , SHIMIZU YASUHIDE , TANI KUNIYUKI , KURAUCHI TERU , SUSHIHARA KIMIHARU , MASUKO KOICHIRO
IPC分类号： H03M1/12 , G11C27/02
CPC分类号： H03M1/1009 , G11C27/026 , H03M1/1215
摘要： PROBLEM TO BE SOLVED: To provide a sample/hold circuit capable of extremely simply and stably measuring the amount of clock skew relative to a conventional technique by inputting a calibration signal without using a reference voltage source; and an A/D conversion device using it.
SOLUTION: This sample/hold circuit 1A includes sampling capacitors Cs and a sample/hold amplifier 10, and samples and holds an input signal Vin by using a switched capacitor. An adder circuit adds the input signal Vin to a ramp calibration signal Vcal by inputting, to the sample/hold amplifier 10, the ramp calibration signal Vcal generated to have a frequency identical to that of a sampling clock signal and a predetermined gradient based on the sampling clock signal through calibrating capacitors Ccal having capacitance smaller than the capacitance of the sampling capacitor Cs. In addition, this A/D conversion device is composed by using the sample/hold circuit 1A.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种采样/保持电路，其能够通过在不使用参考电压源的情况下输入校准信号来极其简单且稳定地测量相对于常规技术的时钟偏移量; 和使用它的A / D转换装置。解决方案：该采样/保持电路1A包括采样电容器Cs和采样/保持放大器10，并且通过使用开关电容器采样和保持输入信号Vin。加法器电路将输入信号Vin加到斜坡校准信号Vcal，通过将采样/保持放大器10产生的斜坡校准信号Vcal与采样时钟信号和预定梯度的频率相同，通过校准具有小于采样电容器Cs的电容的电容的电容器Ccal来采样时钟信号。此外，该A / D转换装置由采样保持电路1A构成。版权所有（C）2010，JPO＆INPIT

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