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1. 发明专利

JP2011086837A Semiconductor device and method of forming the same 审中-公开
标题翻译：半导体器件及其形成方法
公开(公告)号：JP2011086837A
公开(公告)日：2011-04-28
申请号：JP2009239800
申请日：2009-10-16
申请人： Semiconductor Technology Academic Research Center , Tohoku Univ , 国立大学法人東北大学 , 株式会社半導体理工学研究センター
发明人： KOIKE JUNICHI , SUDO YUJI , FUJII SHIGETO , SHIMIZU NORIYOSHI , MAEKAWA KAZUYOSHI , ARITA KOJI , YAGI RYOTARO , YOSHIMARU MASAKI
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522
摘要： PROBLEM TO BE SOLVED: To form an adhesion improved layer made of oxide at the interface between a Cu wire and a cap layer in a multilayer wiring structure of a semiconductor device, and to improve reliability of the Cu wire to migration without increasing resistance of the Cu wire. SOLUTION: The multilayer wiring structure of the semiconductor device includes a first insulating layer (2) formed on a semiconductor wafer (1), the Cu wiring layer (4) provided in an opening opened on a surface of the first insulating layer, a second insulating layer (6) formed on surfaces of the first insulating layer and the Cu wiring layer, and an insulating metal oxide layer (5) formed at the interface between the Cu wiring layer and cap layer as the second insulating layer. The metal oxide layer (5) is formed by immersion plating of metal such as Sn or Zn on the Cu wiring layer (4) and then conducting heat treatment on the plated layer under the oxidation atmosphere. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：在半导体器件的多层布线结构中，在Cu线和覆盖层之间的界面处形成由氧化物形成的附着改善层，并且提高Cu线的迁移的可靠性而不增加铜线的电阻。解决方案：半导体器件的多层布线结构包括形成在半导体晶片（1）上的第一绝缘层（2），设置在第一绝缘层的表面上开口的开口中的Cu布线层（4）形成在所述第一绝缘层和所述Cu布线层的表面上的第二绝缘层（6）和形成在所述Cu布线层和所述盖层之间的界面处的绝缘金属氧化物层（5）作为所述第二绝缘层。金属氧化物层（5）通过在Cu布线层（4）上浸渍诸如Sn或Zn的金属形成，然后在氧化气氛下对镀层进行热处理。版权所有（C）2011，JPO＆INPIT

2. 发明专利

JP2011082274A Low dielectric constant insulating film 有权
标题翻译：低介电常数绝缘膜
公开(公告)号：JP2011082274A
公开(公告)日：2011-04-21
申请号：JP2009231912
申请日：2009-10-05
申请人： Semiconductor Technology Academic Research Center , Tohoku Univ , 国立大学法人東北大学 , 株式会社半導体理工学研究センター
发明人： SAGAWA SEIJI , YASUHARA SHIGEO , KADOMURA SHINGO , SHIMAYAMA TSUTOMU , YANO TAKASHI , TAJIMA KUNITOSHI , MATSUNAGA NORIAKI , YOSHIMARU MASAKI
IPC分类号： H01L21/312 , C23C16/42 , H01L21/31 , H01L21/316
摘要： PROBLEM TO BE SOLVED: To provide a low dielectric constant insulating film with low dielectric constant, high strength and high plasma damage resistance.
SOLUTION: The low dielectric constant insulating film includes a polymer including a plurality of straight chain molecules 2, 3, and 4 in which a plurality of basic molecules 1 including SiO structures are coupled in a straight chain and which are coupled by providing binder molecules 5 including the SiO structures in between and includes Si atoms, O atoms, C atoms and H atoms. When the total of three types of signal areas of a signal showing a linear SiO structure, a signal showing a network SiO structure and a signal showing a cage SiO structure among peak signals of a spectrum obtained by Fourier transform infrared spectroscopy is set to be 100%, an area ratio of the signal showing the linear SiO structure is ≥49%. When the total of a signal amount showing Si(CH
3 ) and that showing Si(CH
3 )
2 is set to be 100% among the peak signals of the spectrum, the signal amount showing Si(CH
3 )
2 is ≥66%.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供具有低介电常数，高强度和高等离子体损伤抗性的低介电常数绝缘膜。解决方案：低介电常数绝缘膜包括包含多个直链分子2,3和4的聚合物，其中包含SiO结构的多个碱性分子1以直链连接并通过提供粘合剂分子5包括其间的SiO结构，包括Si原子，O原子，C原子和H原子。当表示线性SiO结构的信号的三种类型的信号区域的总和，通过傅里叶变换红外光谱获得的频谱的峰值信号中示出网络SiO结构的信号和表示保持架SiO结构的信号的总和被设置为100 ％，表示线状SiO结构的信号的面积比为≥49％。当表示Si（CH 3 ）和显示Si（CH 3 ） 2 的信号量的总和设定为100％光谱的峰值信号，表示Si（CH 3 ） 2 的信号量为≥66％。版权所有（C）2011，JPO＆INPIT

3. 发明专利

JP2011091161A Method of forming low dielectric constant insulating film 有权
标题翻译：形成低介电常数绝缘膜的方法
公开(公告)号：JP2011091161A
公开(公告)日：2011-05-06
申请号：JP2009242692
申请日：2009-10-21
申请人： Semiconductor Technology Academic Research Center , Tohoku Univ , 国立大学法人東北大学 , 株式会社半導体理工学研究センター
发明人： SAGAWA SEIJI , YASUHARA SHIGEO , KADOMURA SHINGO , SHIMAYAMA TSUTOMU , YANO TAKASHI , TAJIMA KUNITOSHI , MATSUNAGA NORIAKI , YOSHIMARU MASAKI
IPC分类号： H01L21/312 , C23C16/30 , C23C16/48 , H01L21/31 , H01L21/768 , H01L23/522
摘要： PROBLEM TO BE SOLVED: To provide a method of forming a low dielectric constant insulating film allowing for forming the low dielectric constant insulating film with a uniform film quality at a high film forming speed. SOLUTION: The method of forming the low dielectric constant insulating film includes the steps of: irradiating a film-formed substrate placed in an atmosphere of material gas with a neutral particle beam; dissociating and polymerizing the material gas adsorbed to the surface of the film-formed substrate; and forming the low dielectric constant insulating film, wherein the irradiation of the film-formed substrate with the neutral particle beam is performed intermittently with a period no longer than 1 ms. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种形成低介电常数绝缘膜的方法，其允许以高成膜速度形成具有均匀膜质量的低介电常数绝缘膜。解决方案：形成低介电常数绝缘膜的方法包括以下步骤：用放置在中性粒子束的材料气体气氛中的成膜基片; 使吸附在膜形成基板的表面上的原料气体分离和聚合; 并且形成低介电常数绝缘膜，其中以不超过1ms的周期间歇地执行具有中性粒子束的成膜基板的照射。版权所有（C）2011，JPO＆INPIT

4. 发明专利

JP2009290025A Neutral particle irradiation type cvd apparatus 审中-公开
标题翻译：中性粒子辐射型CVD装置
公开(公告)号：JP2009290025A
公开(公告)日：2009-12-10
申请号：JP2008141565
申请日：2008-05-29
申请人： Semiconductor Technology Academic Research Center , Tohoku Univ , 国立大学法人東北大学 , 株式会社半導体理工学研究センター
发明人： SAGAWA SEIJI , YASUHARA SHIGEO , KADOMURA SHINGO , YANO TAKASHI , TAJIMA KUNITOSHI , MATSUNAGA NORIAKI , YOSHIMARU MASAKI
IPC分类号： H01L21/31 , C23C16/50 , H01L21/304 , H01L21/3065 , H01L21/316
摘要： PROBLEM TO BE SOLVED: To provide a neutral particle irradiation type CVD apparatus capable of suppressing gas dissociation due to high-energy electrons or UV light and forming an excellent film having a planned molecular structure.
SOLUTION: A neutral particle beam generating means 11 excites a rare gas to generate plasma, imparts an electric field to the charged particles in the plasma to impart a predetermined energy, and neutralizes the charged particles to generate a neutral particle beam NB. A reaction chamber 10 is configured such that a material gas is introduced, part of the material gas is dissociated by the neutral particle beam under control of energy generated by a neutral particle generating means and polymerized, and a film is deposited on a substrate 14.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：提供一种能够抑制由高能电子或紫外光引起的气体解离的中性粒子照射型CVD装置，形成具有规划的分子结构的优异的膜。解决方案：中性粒子束产生装置11激发稀有气体产生等离子体，向等离子体中的带电粒子施加电场以赋予预定能量，并中和带电粒子以产生中性粒子束NB。反应室10被配置为使得材料气体被引入，部分材料气体在中性粒子发生装置产生的能量的控制下被中性粒子束解离并聚合，并且膜沉积在基底14上。版权所有（C）2010，JPO＆INPIT

5. 发明专利

JP2009290026A Film forming method of semiconductor device which uses neutral particle 有权
标题翻译：使用中性粒子的半导体器件的成膜方法
公开(公告)号：JP2009290026A
公开(公告)日：2009-12-10
申请号：JP2008141566
申请日：2008-05-29
申请人： Semiconductor Technology Academic Research Center , Tohoku Univ , 国立大学法人東北大学 , 株式会社半導体理工学研究センター
发明人： SAGAWA SEIJI , YASUHARA SHIGEO , KADOMURA SHINGO , YANO TAKASHI , TAJIMA KUNITOSHI , MATSUNAGA NORIAKI , YOSHIMARU MASAKI
IPC分类号： H01L21/316 , C23C16/52 , H01L21/31
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device film forming method using neutral particles, which can suppress gas dissociation due to high-energy electrons or UV light and can form an excellent film having a planned molecular structure.
SOLUTION: The method includes steps of exciting a rare gas to generate plasma, imparting an electric field to the charged particles in the plasma to impart a predetermined energy, and neutralizing the charged particles to generate a neutral particle beam NB, irradiating the material gas with the neutral particle beam NB having a controlled energy, dissociating the predetermined molecules to dissociate, and forming a film 30 on a substrate 14.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：提供一种使用中性粒子的半导体器件成膜方法，其可以抑制由高能电子或紫外光引起的气体解离，并且可以形成具有计划分子结构的优异的膜。解决方案：该方法包括激发稀有气体以产生等离子体，赋予等离子体中的带电粒子赋予预定能量的电场，中和带电粒子以产生中性粒子束NB，照射具有受控能量的中性粒子束NB的材料气体，使预定分子解离以解离，并在基底14上形成膜30.（C）2010，JPO＆INPIT

6. 发明专利

JP2009231355A Semiconductor device and method of forming the same 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：JP2009231355A
公开(公告)日：2009-10-08
申请号：JP2008071835
申请日：2008-03-19
申请人： Semiconductor Technology Academic Research Center , Tohoku Univ , 国立大学法人東北大学 , 株式会社半導体理工学研究センター
发明人： KOIKE JUNICHI , FUJII SHIGETO , IIJIMA JUN , SHIMIZU NORIYOSHI , MAEKAWA KAZUYOSHI , ARITA KOJI , YAGI RYOTARO , YOSHIMARU MASAKI
IPC分类号： H01L21/3205 , H01L21/768
CPC分类号： H01L21/76853 , H01L21/288 , H01L21/76834 , H01L21/76849 , H01L21/76856 , H01L21/76861 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To form a new interface layer having excellent adhesion, oxidation resistance, and diffusion barrier property at the interface between a lower Cu wire and an upper insulating layer in a multilayer wiring structure of a semiconductor device. SOLUTION: The multilayer wiring structure of semiconductor device includes a first insulating layer (2) formed on a semiconductor wafer (1), a Cu wiring layer (4) formed on the first insulating layer (2), a second insulating layer (6) formed on the Cu wiring layer (4), and a metal oxide layer (5) formed at the interface between the Cu wiring layer (4) and the second insulating layer (6). The metal oxide layer (5) is formed by immersion plating of metal such as Sn or Zn on the Cu wiring layer (4) and then conducting heat treatment to the plated layer under the oxidation atmosphere. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：在半导体器件的多层布线结构中，在下部Cu线和上部绝缘层之间的界面处形成具有优异的粘附性，抗氧化性和扩散阻挡性的新界面层。解决方案：半导体器件的多层布线结构包括形成在半导体晶片（1）上的第一绝缘层（2），形成在第一绝缘层（2）上的Cu布线层（4），第二绝缘层（6），形成在所述Cu布线层（4）和所述第二绝缘层（6）之间的界面处的金属氧化物层（5）。金属氧化物层（5）通过在Cu布线层（4）上浸渍诸如Sn或Zn的金属形成，然后在氧化气氛下对镀层进行热处理。版权所有（C）2010，JPO＆INPIT

7. 发明专利

JP2007335599A Photon detecting sensor for plasma process, and plasma processing equipment 有权
标题翻译：用于等离子体工艺的光电检测传感器和等离子体处理设备
公开(公告)号：JP2007335599A
公开(公告)日：2007-12-27
申请号：JP2006165133
申请日：2006-06-14
申请人： Handotai Rikougaku Kenkyu Center:Kk , Tohoku Univ , 国立大学法人東北大学 , 株式会社半導体理工学研究センター
发明人： SAGAWA SEIJI , YOSHIMARU MASAKI , HIRATA MASAKI , KADOMURA SHINGO , NISHITANI AKITO , HASHIMOTO JUN , ORITA TOSHIYUKI , KONISHI MAMORU , ICHIHASHI YOSHINARI
IPC分类号： H01L21/3065 , H05H1/00
摘要： PROBLEM TO BE SOLVED: To provide a photon detecting sensor capable of detecting abnormal discharge, in three dimensional stretch that occurs in plasma process. SOLUTION: The photon detecting sensor for plasma process comprises a semiconductor substrate 2, a first insulating film layer 8 provided on the semiconductor substrate 2, a first wiring layer 6 embedded in the first insulating film layer 8, a second insulating film layer 12 formed on the first insulating film layer 8, a second wiring layer 10 embedded in the second insulating film layer 12, a third wiring layer 14 formed to comprise an opening 14a on the second insulating film layer 12, and detecting devices 20 and 22 for detecting plasma induced electromotive force generated between the first wiring layer 6 and the third wiring layer 14. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供在等离子体处理中发生的三维拉伸中能够检测异常放电的光子检测传感器。解决方案：用于等离子体处理的光子检测传感器包括半导体衬底2，设置在半导体衬底2上的第一绝缘膜层8，嵌入第一绝缘膜层8中的第一布线层6，第二绝缘膜层 12，其形成在第一绝缘膜层8上，第二布线层10嵌入第二绝缘膜层12中，第三布线层14形成为包括在第二绝缘膜层12上的开口14a，以及检测装置20和22用于检测在第一布线层6和第三布线层14之间产生的等离子体感应电动势。版权所有（C）2008，JPO＆INPIT

8. 发明专利

JP2011054766A Resistance change memory, and method of manufacturing the same 审中-公开
标题翻译：电阻变化记忆体及其制造方法
公开(公告)号：JP2011054766A
公开(公告)日：2011-03-17
申请号：JP2009202483
申请日：2009-09-02
申请人： Semiconductor Technology Academic Research Center , 株式会社半導体理工学研究センター
发明人： TAKAHASHI TSUNEO , ARITA MASASHI , FUJII TAKASHI , KAJI HIROMICHI , KONDO YOJI , SHIGENIWA MASAHIRO , FUJIWARA ICHIRO , YAMAGUCHI TAKESHI , YOSHIMARU MASAKI
IPC分类号： H01L27/10 , H01L45/00 , H01L49/00
摘要： PROBLEM TO BE SOLVED: To provide a resistance change memory capable of exhibiting hysteresis characteristics and memory characteristics of resistance securely with higher reproducibility than conventional techniques, and to provide a method of manufacturing the memory.
SOLUTION: The resistance change memory, constituted by sandwiching a PCMO layer of Pr
x Ca
1-x MnO
3 between a lower and an upper electrode, has a metal oxide layer inserted and formed between the PCMO layer and the upper or lower electrode. Here, the metal oxide is an oxide of metal of the upper electrode, and at least one of the upper and lower electrodes is made of one of tungsten (W), molybdenum (Mo), chromium (Cr), aluminum (Al) and silver (Ag).
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供能够以比常规技术更高的再现性可靠地显示磁滞特性和电阻的存储特性的电阻变化存储器，并提供一种制造存储器的方法。
解决方案：电阻变化记忆是通过将下一层和下层之间的第一层和第二层的第一层和第二层上电极具有插入并形成在PCMO层和上电极或下电极之间的金属氧化物层。这里，金属氧化物是上部电极的金属氧化物，上部电极和下部电极中的至少一个由钨（W），钼（Mo），铬（Cr），铝（Al）和银（Ag）。版权所有（C）2011，JPO＆INPIT

9. 发明专利

JP2010258481A Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2010258481A
公开(公告)日：2010-11-11
申请号：JP2010182513
申请日：2010-08-17
申请人： Semiconductor Technology Academic Research Center , 株式会社半導体理工学研究センター
发明人： MIYAO MASANOBU , NAKAJIMA HIROSHI , SADO TAIZO , MIZUSHIMA ICHIRO , YOSHIMARU MASAKI
IPC分类号： H01L21/20
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device that can have a plurality of kinds of semiconductor elements, differing in lattice constant, mixedly mounted on the same substrate.
SOLUTION: The method of manufacturing the semiconductor device includes forming an insulating film 22 at a portion of the silicon substrate 21, forming an amorphous SiGe layer 23 on the silicon substrate 21 and insulating film 22, heat-treating the silicon substrate to crystallize the amorphous SiGe layer 23 laterally on the insulating film 22 by solid-phase or liquid-phase growth, and forming an SiGe layer 23b, whose lattice constant is matched with that of a material layer to be formed later, on the silicon substrate 21 and insulating film 22.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：解决的问题：提供一种半导体器件的制造方法，该半导体器件可以具有晶格常数不同的多种半导体元件，该半导体元件混合地安装在同一衬底上。解决方案：制造半导体器件的方法包括在硅衬底21的一部分处形成绝缘膜22，在硅衬底21和绝缘膜22上形成非晶SiGe层23，将硅衬底热处理为通过固相或液相生长在绝缘膜22上横向地晶化非晶SiGe层23，并且在硅衬底21上形成晶格常数与稍后形成的材料层的晶格常数相匹配的SiGe层23b 和绝缘膜22.版权所有（C）2011，JPO＆INPIT

10. 发明专利

JP2012144786A Neutral particle irradiation type cvd apparatus 有权
标题翻译：中性粒子辐射型CVD装置
公开(公告)号：JP2012144786A
公开(公告)日：2012-08-02
申请号：JP2011004981
申请日：2011-01-13
申请人： Semiconductor Technology Academic Research Center , 株式会社半導体理工学研究センター
发明人： SAMUKAWA SEIJI , YASUHARA SHIGEO , KADOMURA SHINGO , SHIMAYAMA TSUTOMU , YANO HISASHI , TAJIMA KUNITOSHI , MATSUNAGA NORIAKI , YOSHIMARU MASAKI
IPC分类号： C23C16/505 , C23C16/455 , H01L21/31 , H01L21/314 , H01L21/316
摘要： PROBLEM TO BE SOLVED: To provide a neutral particle irradiation type CVD apparatus into which a raw material gas is introduced onto a wafer in parallel with neutral particles, and improves the in-plane uniformity of a film formed on the wafer.SOLUTION: The CVD apparatus includes: a cathode electrode 22 having a plurality of openings 22a through which neutral particles taken out from a plasma generation part 12 for generating plasma by exciting a noble gas with a coil 18, are introduced onto a wafer 14 within a reaction chamber 10; and a gas supply part 31 for supplying the raw material gas to the wafer 14 from above the wafer in parallel with the neutral particles.
摘要翻译：要解决的问题：提供一种中性粒子照射型CVD装置，其中原料气体与中性粒子平行地引入到晶片上，并且提高了在晶片上形成的膜的面内均匀性。解决方案：CVD装置包括：阴极电极22，其具有多个开口22a，通过该多个开口22a将从用于通过用线圈18激发惰性气体产生等离子体的等离子体产生部分12中取出的中性粒子引入到晶片 14; 以及用于从晶片上方平行于中性粒子向原料气体供给原料气体的气体供给部31。版权所有（C）2012，JPO＆INPIT

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