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1. 发明授权

US06855640B2 Apparatus and process for bulk wet etch with leakage protection 失效
公开(公告)号：US06855640B2
公开(公告)日：2005-02-15
申请号：US10083990
申请日：2002-02-26
申请人： Zhe Wang , Qingxin Zhang , Pang Dow Foo , Hanhua Feng
发明人： Zhe Wang , Qingxin Zhang , Pang Dow Foo , Hanhua Feng
IPC分类号： H01L21/00 , H01L21/306 , H01L21/302
CPC分类号： H01L21/67086 , H01L21/30608 , H01L21/6708
摘要： When using hot alkaline etchants such as KOH, the wafer front side, where various devices and/or circuits are located, must be isolated from any contact with the etchant. This has been achieved by using two chambers that are separated from each other by the wafer that is to be etched. Etching solution in one chamber is in contact with the wafer's back surface while deionized water in the other chamber contacts the front surface. The relative liquid pressures in the chambers is arranged to be slightly higher in the chamber of the front surface so that leakage of etchant through a pin hole from back surface to front surface does not occur. As a further precaution, a monitor to detect the etchant is located in the DI water so that, if need be, etching can be terminated before irreparable damage is done.

2. 发明授权

US06908825B2 Method of making an integrated circuit inductor wherein a plurality of apertures are formed beneath an inductive loop 失效
标题翻译：制造集成电路电感器的方法，其中在感应环下形成多个孔
公开(公告)号：US06908825B2
公开(公告)日：2005-06-21
申请号：US10298418
申请日：2002-11-14
申请人： Shuming Xu , Hanhua Feng , Pang Dow Foo , Bai Xu , Uppili Sridhar
发明人： Shuming Xu , Hanhua Feng , Pang Dow Foo , Bai Xu , Uppili Sridhar
IPC分类号： H01F17/00 , H01L21/02 , H01L27/08 , H01L21/764
CPC分类号： H01L28/10 , H01F17/0006 , H01L27/08
摘要： The invention relates to a method of making an integrated circuit inductor that comprises a silicon substrate and an oxide layer on the silicon substrate. In one aspect, the method comprises depositing an inductive loop on the oxide layer, and making a plurality of apertures in the oxide layer beneath the inductive loop. The method also comprises providing a plurality of bridges adjacent the apertures and provided by portions of the oxide layer between an inner region within the inductive loop and an outer region of the oxide layer without the inductive loop, the inductive loop being supported on the bridges. The method comprises forming a trench in the silicon substrate beneath the bridges, to provide an air gap between the inductive loop and the silicon substrate.
摘要翻译：本发明涉及一种制造集成电路电感器的方法，该集成电路电感器包括硅衬底和硅衬底上的氧化物层。在一个方面，该方法包括在氧化物层上沉积感应回路，以及在感应回路下面的氧化物层中形成多个孔。该方法还包括提供邻近孔的多个桥，并且由感应环内的内部区域和氧化物层的外部区域之间的氧化物层的部分提供，而没有感应环路，感应环路被支撑在桥上。该方法包括在桥下方的硅衬底中形成沟槽，以在感应环路和硅衬底之间提供气隙。

3. 发明授权

US06495903B2 Integrated circuit inductor 失效
标题翻译：集成电路电感
公开(公告)号：US06495903B2
公开(公告)日：2002-12-17
申请号：US09737439
申请日：2000-12-13
申请人： Shuming Xu , Hanhua Feng , Pang Dow Foo , Bai Xu , Uppili Sridhar
发明人： Shuming Xu , Hanhua Feng , Pang Dow Foo , Bai Xu , Uppili Sridhar
IPC分类号： H01L2900
CPC分类号： H01L28/10 , H01F17/0006 , H01L27/08
摘要： An inductor has a spiral aluminum track deposited on an oxide layer over a silicon substrate. The substrate is etched away to form a trench, which extends around beneath the track and provides an air gap having a low dielectric constant. The oxide layer has an inner region within the track, an outer region outside the track and a bridging region extending between the other regions. The bridging region is comprised of intact bridges and gaps therebetween, which are open to the trench and through which an etchant has access to the silicon substrate to form the trench by etching.
摘要翻译：电感器具有沉积在硅衬底上的氧化物层上的螺旋状铝轨道。将衬底蚀刻掉以形成沟槽，该沟槽在轨道下方延伸并提供具有低介电常数的气隙。氧化物层具有轨道内的内部区域，轨道外部的外部区域和在其它区域之间延伸的桥接区域。桥接区域由完整的桥和它们之间的间隙组成，它们对沟槽开放，蚀刻剂可以通过该沟槽进入硅衬底以通过蚀刻形成沟槽。

4. 发明授权

US06436810B1 Bi-layer resist process for dual damascene 失效
标题翻译：双镶嵌双层抗蚀剂工艺
公开(公告)号：US06436810B1
公开(公告)日：2002-08-20
申请号：US09671508
申请日：2000-09-27
申请人： Rakesh Kumar , Leong Tee Koh , Pang Dow Foo
发明人： Rakesh Kumar , Leong Tee Koh , Pang Dow Foo
IPC分类号： H01L214763
CPC分类号： H01L21/76811 , H01L21/0277 , H01L21/31144 , H01L21/76813
摘要： The current invention teaches the use of e-beam patterning techniques for forming contact and via holes of diameter less than about 0.15 microns down to 0.05 microns. E-beam lithography has higher resolution (down to 30-50 nanometers) as compared to 130-150 nanometer when using deep ultra violet (DUV) photolithography patterning techniques. In addition the invention uses a mix and match approach by employing a conventional I-line, or deep UV, resist to form the trench pattern and e-beam lithography tools to form the contact and vial hole patterns. A simplified process scheme is developed where contact/via holes are formed first on solvent developable e-beam resist and the trench pattern is formed on aqueous developable photoresist coated on top of the e-beam resist.
摘要翻译：本发明教导了使用电子束图案化技术来形成直径小于约0.15微米至0.05微米的接触孔和通孔。当使用深紫外（DUV）光刻图案化技术时，电子束光刻相比于130-150纳米具有更高的分辨率（低至30-50纳米）。此外，本发明使用混合匹配方法，通过采用常规I线或深UV抗蚀剂形成沟槽图案和电子束光刻工具以形成接触和小瓶孔图案。开发了简单的处理方案，其中首先在溶剂可显影的电子束抗蚀剂上形成接触/通孔，并且沟槽图案形成在涂覆在电子束抗蚀剂顶部的含水可显影光致抗蚀剂上。

5. 发明授权

US06007728A Design of a novel tactile sensor 失效
标题翻译：新颖的触觉传感器的设计
公开(公告)号：US06007728A
公开(公告)日：1999-12-28
申请号：US961126
申请日：1997-10-30
申请人： Lian Jun Liu , Mnoon Yan Loke , Pang Dow Foo
发明人： Lian Jun Liu , Mnoon Yan Loke , Pang Dow Foo
IPC分类号： B25J13/08 , B25J19/02 , G01L1/18 , G01L5/22 , B44C1/22
CPC分类号： G01L1/18 , B25J13/082 , B25J19/02 , G01L5/228
摘要： An apparatus for sensing an applied force comprising a deflectable bridge, formed in a substrate and spanning a recessed area. The deflectable bridge also has a sensing element. The force is applied to the bridge and in response thereto, an output characteristic of the sensing element changes in proportion to the magnitude of the applied force. The apparatus can further comprise a sensing bump in contact with the bridge, wherein the force is applied to the bridge through the sensing bump.
摘要翻译：一种用于感测施加的力的装置，包括形成在衬底中并跨越凹陷区域的可偏转桥。可偏转桥还具有传感元件。力被施加到桥，并且响应于此，感测元件的输出特性与所施加的力的大小成比例地变化。该装置还可以包括与桥接触的感测凸块，其中通过感测凸块将力施加到桥。

6. 发明授权

US06503847B2 Room temperature wafer-to-wafer bonding by polydimethylsiloxane 失效
标题翻译：通过聚二甲基硅氧烷的室温晶片与晶片的接合
公开(公告)号：US06503847B2
公开(公告)日：2003-01-07
申请号：US09841940
申请日：2001-04-26
申请人： Yu Chen , Quanbo Zou , Uppili Sridhar , Pang Dow Foo
发明人： Yu Chen , Quanbo Zou , Uppili Sridhar , Pang Dow Foo
IPC分类号： H01L2131
CPC分类号： B81C3/001 , C08J5/124 , C09J183/04 , H01L21/2007
摘要： A method of forming bonds between similar and dissimilar material surfaces particularly the surfaces of silicon wafers having various devices disposes thereon, wherein such bonds can be formed at room temperature and do not require the application of high pressures or voltages. The bonding material is polydimethylsiloxane, which is transparent and bio-compatible.
摘要翻译：在类似和不同材料表面之间形成粘合的方法，特别是具有各种装置的硅晶片的表面，其中可以在室温下形成这种键，并且不需要施加高压或高压。粘合材料是聚二甲基硅氧烷，其是透明的和生物相容的。

7. 发明授权

US06383855B1 High speed, low cost BICMOS process using profile engineering 失效
标题翻译：使用轮廓工程的高速，低成本BICMOS工艺
公开(公告)号：US06383855B1
公开(公告)日：2002-05-07
申请号：US09186505
申请日：1998-11-04
申请人： Minghui Gao , Haijun Zhao , Abhijit Bandyopadhyay , Pang Dow Foo
发明人： Minghui Gao , Haijun Zhao , Abhijit Bandyopadhyay , Pang Dow Foo
IPC分类号： H01L218238
CPC分类号： H01L21/8249
摘要： A bipolar complementary metal oxide semiconductor device has a c-well fabricated using profile engineering (a multi-energy implant using accurate dosages and energies determined by advance simulation) to provide a higher c-well implant dose while creating a narrow region with relatively low concentration in the collector depletion range to avoid low base-collector breakdown. This achieves a much lower collector series resistance to pull-up a frequency response, a collector sheet resistance which can be as low as 150 &OHgr;/sq., and fT may be increased to 20 GHz or higher.
摘要翻译：双极互补金属氧化物半导体器件具有使用轮廓工程（使用由先进模拟确定的精确剂量和能量的多能量注入）的c-阱制造，以提供更高的c-阱注入剂量，同时产生具有相对低浓度的窄区域在集电极耗尽范围内，以避免基极集电极故障。这实现了更低的集电极串联电阻上拉频率响应，集电极薄层电阻可以低至150欧姆/平方，fT可以增加到20GHz或更高。

8. 发明授权

US06765300B1 Micro-relay 失效
标题翻译：微型继电器
公开(公告)号：US06765300B1
公开(公告)日：2004-07-20
申请号：US09890575
申请日：2002-02-11
申请人： Dirk Wagenaar , Kay Krupka , Helmut Schlaak , Uppili Sridhar , Victor D. Samper , Pang Dow Foo
发明人： Dirk Wagenaar , Kay Krupka , Helmut Schlaak , Uppili Sridhar , Victor D. Samper , Pang Dow Foo
IPC分类号： H01L2348
CPC分类号： B81C1/00666 , B81C2201/0167 , H01H59/0009 , H01L2924/0002 , H01L2924/00
摘要： A microstructure relay is provided, having a body that includes upper and lower portions. The lower portion is formed from a substrate, and the upper portion is formed on the substrate to avoid bonding of the lower portion to the upper portion. A support member is fixed to the body at a first end of the support member to form a cantilever, wherein an upper surface of the support member and a lower surface of the upper portion of the body form a cavity. A first contact region is located on the upper surface at a second end of the support member. The first contact region comprises a first contact, wherein pivoting the support member toward the lower surface causes the first contact to be electrically coupled to a counter contact.
摘要翻译：提供一种微结构继电器，其具有包括上部和下部的主体。下部由基板形成，上部形成在基板上，以避免下部与上部的接合。支撑构件在支撑构件的第一端处固定到主体以形成悬臂，其中支撑构件的上表面和主体的上部的下表面形成空腔。第一接触区域位于支撑构件的第二端的上表面上。第一接触区域包括第一触点，其中支撑构件向下表面转动使得第一接触件电耦合到反接触。

9. 发明授权

US06670272B2 Method for reducing dishing in chemical mechanical polishing 失效
标题翻译：减少化学机械抛光中凹陷的方法
公开(公告)号：US06670272B2
公开(公告)日：2003-12-30
申请号：US09976117
申请日：2001-10-12
申请人： Shaoyu Wu , Joon Mo Kang , Pang Dow Foo
发明人： Shaoyu Wu , Joon Mo Kang , Pang Dow Foo
IPC分类号： H01L21302
CPC分类号： H01L21/3212
摘要： A method is described for reducing dishing in a chemical mechanical polishing process performed on a semiconductor wafer having a dielectric layer with trenches and a copper layer deposited over the dielectric layer and filling the trenches in the dielectric layer. The method comprises steps of removing excess copper above the plane of the dielectric surface using a main polishing operation, whereby copper residues are formed above the plane of the dielectric surface, and applying chemical treatment to the surface of the semiconductor wafer in the initial stage of an overpolishing operation, wherein a protective layer over the copper residues and surfaces of copper-filled trenches is formed. The method further comprises steps of removing the copper residues and protective layer thereon above the plane of the dielectric layer in the overpolishing operation, and removing the protective layer over the surfaces of the copper-filled trenches in the overpolishing operation.
摘要翻译：描述了一种用于减少在具有沉积在电介质层上并且填充介电层中的沟槽的沟槽和铜层的电介质层的半导体晶片上进行的化学机械抛光工艺中的凹陷的方法。该方法包括以下步骤：使用主抛光操作在电介质表面的平面上除去多余的铜，由此在电介质表面平面上形成铜残留物，并在初始阶段对半导体晶片的表面进行化学处理一种过度抛光操作，其中形成铜残留物和铜填充沟槽表面上的保护层。该方法还包括以下步骤：在过抛光操作中，在电介质层的平面上方去除铜残留物和保护层，并且在抛光操作中除去铜填充沟槽表面上的保护层。

10. 发明授权

US06664596B2 Stacked LDD high frequency LDMOSFET 失效
公开(公告)号：US06664596B2
公开(公告)日：2003-12-16
申请号：US10272137
申请日：2002-10-16
申请人： Jun Cai , Pang Dow Foo , Narayanan Balasubramanian
发明人： Jun Cai , Pang Dow Foo , Narayanan Balasubramanian
IPC分类号： H01L2976
CPC分类号： H01L29/0847 , H01L29/0634 , H01L29/66659 , H01L29/7835
摘要： A novel silicon RF LDMOSFET structure based on the use of a stacked LDD, is disclosed. The LDD has been modified from a single layer of N type material to a stack of three layers. These are upper and lower N type layers with a P type layer between them. The upper N type layer is heavily doped to reduce the on-resistance of the device, while the lower N type layer is lightly doped to reduce the output capacitance, thereby improving the high frequency performance. The middle P layer is heavily doped which allows it to bring about pinch-off of the two N layers, thereby raising the device's breakdown voltage. A process for manufacturing the device, as well as experimental data concerning its performance are also given.

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