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1. 发明授权

US06908825B2 Method of making an integrated circuit inductor wherein a plurality of apertures are formed beneath an inductive loop 失效
标题翻译：制造集成电路电感器的方法，其中在感应环下形成多个孔
公开(公告)号：US06908825B2
公开(公告)日：2005-06-21
申请号：US10298418
申请日：2002-11-14
申请人： Shuming Xu , Hanhua Feng , Pang Dow Foo , Bai Xu , Uppili Sridhar
发明人： Shuming Xu , Hanhua Feng , Pang Dow Foo , Bai Xu , Uppili Sridhar
IPC分类号： H01F17/00 , H01L21/02 , H01L27/08 , H01L21/764
CPC分类号： H01L28/10 , H01F17/0006 , H01L27/08
摘要： The invention relates to a method of making an integrated circuit inductor that comprises a silicon substrate and an oxide layer on the silicon substrate. In one aspect, the method comprises depositing an inductive loop on the oxide layer, and making a plurality of apertures in the oxide layer beneath the inductive loop. The method also comprises providing a plurality of bridges adjacent the apertures and provided by portions of the oxide layer between an inner region within the inductive loop and an outer region of the oxide layer without the inductive loop, the inductive loop being supported on the bridges. The method comprises forming a trench in the silicon substrate beneath the bridges, to provide an air gap between the inductive loop and the silicon substrate.
摘要翻译：本发明涉及一种制造集成电路电感器的方法，该集成电路电感器包括硅衬底和硅衬底上的氧化物层。在一个方面，该方法包括在氧化物层上沉积感应回路，以及在感应回路下面的氧化物层中形成多个孔。该方法还包括提供邻近孔的多个桥，并且由感应环内的内部区域和氧化物层的外部区域之间的氧化物层的部分提供，而没有感应环路，感应环路被支撑在桥上。该方法包括在桥下方的硅衬底中形成沟槽，以在感应环路和硅衬底之间提供气隙。

2. 发明授权

US06495903B2 Integrated circuit inductor 失效
标题翻译：集成电路电感
公开(公告)号：US06495903B2
公开(公告)日：2002-12-17
申请号：US09737439
申请日：2000-12-13
申请人： Shuming Xu , Hanhua Feng , Pang Dow Foo , Bai Xu , Uppili Sridhar
发明人： Shuming Xu , Hanhua Feng , Pang Dow Foo , Bai Xu , Uppili Sridhar
IPC分类号： H01L2900
CPC分类号： H01L28/10 , H01F17/0006 , H01L27/08
摘要： An inductor has a spiral aluminum track deposited on an oxide layer over a silicon substrate. The substrate is etched away to form a trench, which extends around beneath the track and provides an air gap having a low dielectric constant. The oxide layer has an inner region within the track, an outer region outside the track and a bridging region extending between the other regions. The bridging region is comprised of intact bridges and gaps therebetween, which are open to the trench and through which an etchant has access to the silicon substrate to form the trench by etching.
摘要翻译：电感器具有沉积在硅衬底上的氧化物层上的螺旋状铝轨道。将衬底蚀刻掉以形成沟槽，该沟槽在轨道下方延伸并提供具有低介电常数的气隙。氧化物层具有轨道内的内部区域，轨道外部的外部区域和在其它区域之间延伸的桥接区域。桥接区域由完整的桥和它们之间的间隙组成，它们对沟槽开放，蚀刻剂可以通过该沟槽进入硅衬底以通过蚀刻形成沟槽。

3. 发明授权

US06667516B2 RF LDMOS on partial SOI substrate 失效
公开(公告)号：US06667516B2
公开(公告)日：2003-12-23
申请号：US10186528
申请日：2002-07-01
申请人： Shuming Xu , Hanhua Feng , Pang-Dow Foo
发明人： Shuming Xu , Hanhua Feng , Pang-Dow Foo
IPC分类号： H01L2994
CPC分类号： H01L29/66659 , H01L29/0653 , H01L29/4175 , H01L29/41766 , H01L29/66636 , H01L29/7835 , Y10S438/923
摘要： In the prior art LDMOSFET devices capable of handling high power have been made by locating the source contact on the bottom surface of the device, allowing for good heat sinking, with connection to the source region being made through a sinker. However, this structure has poor high frequency characteristics. Also in the prior art, good high frequency performance has been achieved by introducing a dielectric layer immediately below the source/drain regions (SOI) but this structure has poor power handling capabilities. The present invention achieves both good high frequency behavior as well as good power capability in the same device. Instead of inserting a dielectric layer over the entire cross-section of the device, the dielectric layer is limited to being below the heavily doped section of the drain with a small amount of overlap into the lightly doped section. The structure is described in detail together with a process for manufacturing it.

4. 发明授权

US06461902B1 RF LDMOS on partial SOI substrate 失效
标题翻译： RF LDMOS在部分SOI衬底上
公开(公告)号：US06461902B1
公开(公告)日：2002-10-08
申请号：US09618263
申请日：2000-07-18
申请人： Shuming Xu , Hanhua Feng , Pang-Dow Foo
发明人： Shuming Xu , Hanhua Feng , Pang-Dow Foo
IPC分类号： H01L2100
CPC分类号： H01L29/66659 , H01L29/0653 , H01L29/4175 , H01L29/41766 , H01L29/66636 , H01L29/7835 , Y10S438/923
摘要： In the prior art LDMOSFET devices capable of handling high power have been made by locating the source contact on the bottom surface of the device, allowing for good heat sinking, with connection to the source region being made through a sinker. However, this structure has poor high frequency characteristics. Also in the prior art, good high frequency performance has been achieved by introducing a dielectric layer immediately below the source/drain regions (SOI) but this structure has poor handling capabilities. The present invention achieves both good high frequency behavior as well as good power capability in the same device. Instead of inserting a dielectric layer over the entire cross-section of the device, the dielectric layer is limited to being below the heavily doped section of the drain with a small amount of overlap into the lightly doped section. The structure is described in detail together with a process for manufacturing it.
摘要翻译：在现有技术中，能够处理高功率的LDMOSFET器件已经通过将源极接触定位在器件的底表面上，通过连接到源极区域通过沉降片而实现良好的散热。然而，该结构具有差的高频特性。同样在现有技术中，通过在源极/漏极区域（SOI）之下引入介电层已经实现了良好的高频性能，但是该结构具有差的处理能力。本发明在同一设备中实现了良好的高频行为以及良好的功率能力。代替在器件的整个横截面上插入电介质层，电介质层被限制在漏极的重掺杂部分之下，在轻掺杂部分中具有少量的重叠。详细描述该结构及其制造方法。

5. 发明授权

US08614480B2 Power MOSFET with integrated gate resistor and diode-connected MOSFET 有权
标题翻译：功率MOSFET集成栅极电阻和二极管连接的MOSFET
公开(公告)号：US08614480B2
公开(公告)日：2013-12-24
申请号：US13540862
申请日：2012-07-03
申请人： Jun Wang , Shuming Xu , Jacek Korec
发明人： Jun Wang , Shuming Xu , Jacek Korec
IPC分类号： H01L29/66
CPC分类号： H01L27/0629 , H01L27/0727 , H01L29/1083 , H01L29/402 , H01L29/4175 , H01L29/41766 , H01L29/456 , H01L29/66659 , H01L29/7835 , H01L29/861
摘要： A power MOSFET is formed in a semiconductor device with a parallel combination of a shunt resistor and a diode-connected MOSFET between a gate input node of the semiconductor device and a gate of the power MOSFET. A gate of the diode-connected MOSFET is connected to the gate of the power MOSFET. Source and drain nodes of the diode-connected MOSFET are connected to a source node of the power MOSFET through diodes. The drain node of the diode-connected MOSFET is connected to the gate input node of the semiconductor device. The source node of the diode-connected MOSFET is connected to the gate of the power MOSFET. The power MOSFET and the diode-connected MOSFET are integrated into the substrate of the semiconductor device so that the diode-connected MOSFET source and drain nodes are electrically isolated from the power MOSFET source node through a pn junction.
摘要翻译：在半导体器件的栅极输入节点和功率MOSFET的栅极之间，在半导体器件中形成并联组合的分流电阻器和二极管连接的MOSFET的功率MOSFET。二极管连接的MOSFET的栅极连接到功率MOSFET的栅极。二极管连接的MOSFET的源极和漏极节点通过二极管连接到功率MOSFET的源极节点。二极管连接的MOSFET的漏极节点连接到半导体器件的栅极输入节点。二极管连接的MOSFET的源节点连接到功率MOSFET的栅极。功率MOSFET和二极管连接的MOSFET集成到半导体器件的衬底中，使得二极管连接的MOSFET源极和漏极节点通过pn结与功率MOSFET源节点电隔离。

6. 发明授权

US07589378B2 Power LDMOS transistor 有权
标题翻译：电源LDMOS晶体管
公开(公告)号：US07589378B2
公开(公告)日：2009-09-15
申请号：US11676613
申请日：2007-02-20
申请人： Christopher Boguslaw Kocon , Shuming Xu , Jacek Korec
发明人： Christopher Boguslaw Kocon , Shuming Xu , Jacek Korec
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/4175 , H01L29/41758 , H01L29/41766 , H01L29/4933 , H01L29/7802 , H01L29/7816 , H01L29/7823
摘要： A laterally diffused metal-oxide-semiconductor transistor device includes a substrate having a first conductivity type with a semiconductor layer formed over the substrate. A source region and a drain extension region of the first conductivity type are formed in the semiconductor layer. A body region of a second conductivity type is formed in the semiconductor layer. A conductive gate is formed over a gate dielectric layer that is formed over a channel region. A drain contact electrically connects the drain extension region to the substrate and is laterally spaced from the channel region. The drain contact includes a highly-doped drain contact region formed between the substrate and the drain extension region in the semiconductor layer, wherein a topmost portion of the highly-doped drain contact region is spaced from the upper surface of the semiconductor layer. A source contact electrically connects the source region to the body region.
摘要翻译：横向扩散的金属氧化物半导体晶体管器件包括具有在衬底上形成的半导体层的第一导电类型的衬底。在半导体层中形成第一导电类型的源极区域和漏极延伸区域。在半导体层中形成第二导电类型的体区。导电栅极形成在沟道区域上形成的栅极电介质层上。漏极接触将漏极延伸区域电连接到衬底并且与沟道区域横向间隔开。漏极接触包括形成在半导体层中的衬底和漏极延伸区域之间的高掺杂漏极接触区域，其中高掺杂漏极接触区域的最高部分与半导体层的上表面间隔开。源极触点将源极区域电连接到主体区域。

7. 发明申请

US20080054994A1 Dual-Gate Metal-Oxide-Semiconductor Device 失效
标题翻译：双栅极金属氧化物半导体器件
公开(公告)号：US20080054994A1
公开(公告)日：2008-03-06
申请号：US11927950
申请日：2007-10-30
申请人： Muhammed Shibib , Shuming Xu
发明人： Muhammed Shibib , Shuming Xu
IPC分类号： G05F1/10 , H01L21/336 , H01L29/78
CPC分类号： H01L29/7835 , H01L29/402 , H01L29/7831
摘要： An MOS device includes first and second source/drain regions of a first conductivity type formed in a semiconductor layer of a second conductivity type proximate an upper surface of the semiconductor layer, the first and second source/drain regions being spaced apart relative to one another. A non-uniformly doped channel region of the first conductivity type is formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions. An insulating layer is formed on the upper surface of the semiconductor layer. A first gate is formed on the insulating layer at least partially between the first and second source/drain regions and above at least a portion of the channel region, and at least a second gate formed on the insulating layer above at least a portion of the channel region and between the first gate and the second source/drain region. The second gate has a length which is substantially greater than a length of the first gate, the first and second gates being electrically isolated from one another.
摘要翻译： MOS器件包括在半导体层的上表面附近形成在第二导电类型的半导体层中的第一导电类型的第一和第二源极/漏极区域，第一和第二源极/漏极区域相对于彼此间隔开。第一导电类型的非均匀掺杂沟道区形成在靠近半导体层的上表面的半导体层中，并且至少部分地在第一和第二源/漏区之间。绝缘层形成在半导体层的上表面上。至少部分地在第一和第二源极/漏极区域之间并且在沟道区域的至少一部分上方形成第一栅极，并且至少在绝缘层上形成的至少一部分第二栅极并且在第一栅极和第二源极/漏极区域之间。第二栅极的长度远大于第一栅极的长度，第一栅极和第二栅极彼此电隔离。

8. 发明授权

US07297606B2 Metal-oxide-semiconductor device including a buried lightly-doped drain region 有权
标题翻译：金属氧化物半导体器件包括埋入的轻掺杂漏极区域
公开(公告)号：US07297606B2
公开(公告)日：2007-11-20
申请号：US11116903
申请日：2005-04-28
申请人： Muhammed Ayman Shibib , Shuming Xu
发明人： Muhammed Ayman Shibib , Shuming Xu
IPC分类号： H01L21/336
CPC分类号： H01L29/402 , H01L29/0615 , H01L29/0847 , H01L29/0873 , H01L29/4175 , H01L29/66659 , H01L29/7835
摘要： An MOS device includes a semiconductor layer of a first conductivity type, a source region of a second conductivity type formed in the semiconductor layer, and a drain region of the second conductivity type formed in the semiconductor layer and spaced apart from the source region. A gate is formed proximate an upper surface of the semiconductor layer and at least partially between the source and drain regions. The MOS device further includes a buried LDD region of the second conductivity type formed in the semiconductor layer between the gate and the drain region, the buried LDD region being spaced laterally from the drain region, and a second LDD region of the first conductivity type formed in the buried LDD region and proximate the upper surface of the semiconductor layer. The second LDD region is self-aligned with the gate and spaced laterally from the gate such that the gate is non-overlapping relative to the second LDD region.
摘要翻译： MOS器件包括形成在半导体层中的第一导电类型的半导体层，第二导电类型的源极区和形成在半导体层中并与源极区隔开的第二导电类型的漏极区。栅极形成在半导体层的上表面附近，并且至少部分地在源区和漏区之间形成。 MOS器件还包括形成在栅极和漏极区域之间的半导体层中的第二导电类型的埋入LDD区域，所述掩埋LDD区域与漏极区域横向间隔开，并且形成第一导电类型的第二LDD区域在掩埋的LDD区域中并且靠近半导体层的上表面。第二LDD区域与栅极自对准并且与栅极横向隔开，使得栅极相对于第二LDD区域不重叠。

9. 发明授权

US07282765B2 Power LDMOS transistor 有权
标题翻译：电源LDMOS晶体管
公开(公告)号：US07282765B2
公开(公告)日：2007-10-16
申请号：US11180155
申请日：2005-07-13
申请人： Shuming Xu , Jacek Korec
发明人： Shuming Xu , Jacek Korec
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L29/7816 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/4175 , H01L29/41758 , H01L29/41766 , H01L29/4933 , H01L29/7802 , H01L29/7811 , H01L29/7823
摘要： An LDMOS device comprises a substrate having a first conductivity type and a lightly doped epitaxial layer thereon having an upper surface. Source and drain regions of the first conductivity type are formed in the epitaxial layer along with a channel region of a second conductivity type formed therebetween. A conductive gate is formed over a gate dielectric layer. A drain contact electrically connects the drain region to the substrate, comprising a first trench formed from the upper surface of the epitaxial layer to the substrate and having a side wall along the epitaxial layer, a highly doped region of the first conductivity type formed along the side wall of the first trench, and a drain plug in the first trench adjacent the highly doped region. A source contact is provided and an insulating layer is formed between the conductive gate and the source contact.
摘要翻译： LDMOS器件包括具有第一导电类型的衬底和其上具有上表面的轻掺杂外延层。第一导电类型的源区和漏区与其间形成的第二导电类型的沟道区一起形成在外延层中。导电栅极形成在栅极电介质层上。漏极接触将漏极区域电连接到衬底，包括从外延层的上表面到衬底形成的第一沟槽，并且沿着外延层具有侧壁，沿着所述外延层形成的第一导电类型的高掺杂区域沿着所述第一沟槽的侧壁以及与所述高掺杂区域相邻的所述第一沟槽中的排水塞。提供源极触点，并且在导电栅极和源极触点之间形成绝缘层。

10. 发明申请

US20070034942A1 Power LDMOS transistor 有权
标题翻译：电源LDMOS晶体管
公开(公告)号：US20070034942A1
公开(公告)日：2007-02-15
申请号：US11202981
申请日：2005-08-12
申请人： Shuming Xu , Jacek Korec
发明人： Shuming Xu , Jacek Korec
IPC分类号： H01L31/00
CPC分类号： H01L29/7835 , H01L29/1083 , H01L29/402 , H01L29/4175 , H01L29/41766 , H01L29/4933
摘要： A LDMOS transistor comprises a trench formed through the epitaxial layer at least to the top surface of the substrate, the trench having a bottom surface and a sidewall contacting the source region and the portion of the channel region extending under the source region. A first insulating layer is formed over the upper surface and sidewall surfaces of the conductive gate. A continuous layer of conductive material forming a source contact and a gate shield electrode is formed along the bottom surface and the sidewall of the trench and over the first insulating layer to cover the top and sidewall surfaces of the conductive gate. A second insulating layer is formed over an active area of the transistor, including over the continuous layer of conductive material and filling the trench. A drain electrode can extend over the second insulating layer to substantially cover the active area.
摘要翻译： LDMOS晶体管包括至少通过外延层形成的沟槽，至少到衬底的顶表面，沟槽具有接触源极区域和在源极区域下延伸的沟道区域的部分的底表面和侧壁。在导电栅极的上表面和侧壁表面上形成第一绝缘层。形成源极接触和栅极屏蔽电极的连续导电材料层沿着沟槽的底表面和侧壁形成，并且在第一绝缘层上方覆盖导电栅极的顶表面和侧壁表面。在晶体管的有源区域上形成第二绝缘层，包括在连续的导电材料层上并填充沟槽。漏电极可以在第二绝缘层上延伸以基本覆盖有源区。

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